Method and apparatus for object-oriented interrupt system

[0002] This is a continuation of application Ser. No 09/047,938 filed Mar. 26, 1998, now U.S. Pat. No. 6,052,739.

[0003] 1. Field of the Invention

[0004] The invention relates generally to apparatus and methods for providing interrupts in computer systems and, more particularly, to interrupt systems implemented in computer systems employing object-oriented software.

[0005] 2. Description of the Related Art

[0006] Computer systems operate, in general, by executing a series of specific instructions contained in “programs” stored in memory. However, the computer must also respond to randomly occurring external and internal events called “interrupts”, such as a user pressing a key on a keyboard or a printer signaling for more data to print. The computer must suspend normal processing and temporarily divert the flow of control from the stored program to another program called an “interrupt handler” routine.

[0007] Interrupt processing is performed by the operating system (“OS”) software of both computers operating traditional software known as “procedural programming,” and more recent systems employing software developed using object-oriented programing techniques. However, prior art object-oriented interrupt management systems have a number of limitations that affect both the portability and performance of the OS. That is, it would be desirable to provide an interrupt system to allow operating systems to be used with many different types of CPUs. Moreover, it would be desirable to provide increased speed and efficiency in handling interrupts by the operating system. The apparatus and methods of the present invention are designed to overcome all of these current limitations, providing with a portable and high performance interrupt management system.

[0008] Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the methods, apparatus, and articles of manufacture particularly pointed out in the written description and claims hereof, as well as the appended drawings.

[0009] To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, the invention provides a method for processing interrupts in an object-oriented computer system having a CPU, a memory containing a microkernel, a plurality of device constituting sources capable of generating interrupts, a plurality of drivers each associated with one of the sources, and a system database. The method comprises the steps of creating a device entry in the database for each of the devices, creating an interrupt source tree in the database comprising a plurality of source tree entries each comprising an object representing one of the sources, and implementing an interrupt registration interface comprising methods which install and remove interrupt management software components associated with each source in a corresponding source tree entry. The method further comprises the steps of cross-referencing each of the device entries with a corresponding one of the source tree entries, responding to an interrupt generated by a device by causing a single interrupt dispatcher to execute and identifying the device to the interrupt dispatcher; and processing the interrupt with a handler invoked by the interrupt dispatcher and corresponding to the identified device.

[0010] In another aspect, the invention includes apparatus for processing interrupts in an object-oriented computer system having a CPU, a plurality of devices constituting sources capable of generating interrupts, and a plurality of drivers each associated with one of the sources. The apparatus comprises a plurality of interrupt management software components supplied by the drivers each associated with an interrupt source; a memory containing a database having a device entry for each of the devices; an interrupt source tree comprising a plurality of interrupt source tree entries each comprising an object representing at least one of the sources and cross referenced to a corresponding device entry, each of the interrupt source tree entries including a reference to at least one of the interrupt management software components; and a single interrupt dispatcher for responding to an interrupt identified by the CPU by executing a corresponding interrupt management software component specified by an interrupt source tree entry corresponding to the identified device.

[0011] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

[0012] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate one embodiment of the invention and, together with the description, serve to explain the principles of the invention.

[0013] In the drawings:

[0014] FIG. 1 is a hardware blocked diagram of a computer system embodying the present invention;

[0015] FIG. 2 is a diagram of object-oriented software of the computer system of FIG. 1;

[0016] FIG. 3 is a diagram showing an example of the relationship between interrupt sources;

[0017] FIG. 4 is a diagram showing a portion of an interrupt source tree corresponding to the example of FIG. 3;

[0018] FIG. 5 is an example of a bus interrupt source entry;

[0019] FIG. 6 is a diagram showing interrupt and device namespace cross-referencing;

[0020] FIG. 7 is a diagram illustrating the relationship between software and various levels of the interrupt source tree;

[0021] FIG. 8 is a diagram illustrating interrupt handler synchronization;

[0022] FIG. 9 is a diagram illustrating the concept of deferred interrupt handling;

[0023] FIG. 10 is a diagram showing an interrupt dispatcher and its relationship to run time and microkernel software;

[0024] FIG. 11 is a diagram showing bus add device interrupt handlers;

[0025] FIG. 12 is a diagram showing interrupt source class hierarchy; and

[0026] FIG. 13 is a diagram illustrating improvements in performance by the present invention of an Ethernet read interrupt operation.

[0027] The invention is contained in an object-oriented operating system. The disclosed embodiment is implemented in the Java programming environment provided by Sun Microsystems, Inc. However, the invention is not so limited and may be incorporated into other computer systems, as is understood by those skilled in the art. Sun, Sun Microsystems, the Sun logo, Java, and Java-based trademarks are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries.

[0028] Reference will now be made in detail to an implementation consistent with the present invention, as illustrated in the drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the following description to refer to the same or like parts.

[0029] FIG. 1 shows a computer system 10 suitable for use with the present invention. Computer system 10 includes a central processing unit (CPU) 12 which may be, for example, a Sun SPARC, a Motorola Power PC or an Intel Pentium computer system 10 may represent a wide variety of computing devices. For example, system 10 may represent a standard personal computer, as widely used in homes and offices. Alternatively system 10 may comprise a much more specialized “smart” system, such as a set-top box for use in receiving high definition television, or a multi-function cellular telephone.

[0030] CPU 12 is connected to memory 14 which may include various types of memory such as random access memory (RAM) and read only memory (ROM). CPU 12 is also connected to an expansion bus 16 which may be, for example, a PCI bus. Various types of input and output devices 19, 20, and 22 are connected to bus 16. For example, input device 18 maybe a modem or network interface card connecting system 10 to a telephone line or local area network. Input device 20 may be, for example, a keyboard and output device 22 may be, for example, a printer. System 10 may optionally include a mass storage device 24, such as a hard disk drive connected by an I/O bus 26 which may be, for example, a SCSI bus. System 10 also includes a direct memory access (DMA) controller 23, under control of CPU 12, which can provide direct transfer of data between memory 14 and PCI bus 16.

[0031] Referring now to FIG. 2, there is shown a diagram of software stored in memory 14 of FIG. 1. FIG. 2 shows software logically arranged in a series of layers. An upper layer 32 is “platform-independent.” The term “platform” generally refers to a CPU physical memory, and permanently attached devices and buses. Thus, the software contained in platform-independent layer 32 is written in a manner that it may be used with any platform, based on any CPU, either existing or to be developed in the future, without modification. A second layer 34 is platform-dependent. Thus, software of layer 34 must be customized for the particular platform of computer system 10.

[0032] Platform-independent layer 32 includes an application program layer 36 which performs specific operations for the user, such as desktop publishing, managing a telephone call, or database management. Application layer 36 interfaces with a runtime system 38 which includes a component known as a “Java™ Virtual Machine” (JVM). The JVM is a software component which receives instructions in the form of machine-independent byte codes produced by applications programs and interprets the byte codes. The JVM interfaces with a specific platform to execute desired functions. The disclosed embodiment employs a Java Virtual Machine, but other types of virtual machines are usable, as known to those skilled in the art. The operation of the JVM is well known to those skilled in the art and is discussed in, for example, the book Java! by Tim Ritchey, published by New Riders Publishing of Indianapolis, Ind., and The Java Virtual Machine Specificationby Lindham and Yellin, Addison-Wellesley, 1997.

[0033] Runtime layer 38 also includes a device interface portion 42 which supports operation of devices such as buses 16 and 26 and devices 18, 20, 22 (FIG. 1). In particular, device interface 42 includes device managers 46 and miscellaneous managers 48. Device interface 42 also includes device drivers 50 which are object-oriented programs written for each of the devices 18, 20, and 22. Note that device drivers 50 are included in platform-independent layer 32, and thus, once written, may be used to support devices 18, 20, and 22 on any platform both existing and to be developed in the future. Similarly, device interface 42 includes platform-independent bus managers, 51 which are object-oriented programs written for buses, such as PCI bus 16 and SCSI bus 26 of FIG. 1. Device interface 42 includes memory classes 52.

[0034] Device interface 42 also includes a system loader 54 and a system database which support operation of computer system. System database 56 permits client software to store and retrieve configuration information on computer system 10. In particular, system database 56 contains configuration information for devices which are present, what system software services are installed, what user and group attributes have been selected, and any application-specific information required. In the described embodiment, the system database is referred to as a Java System Database (JSD). Additional details of the JSD are set forth in Appendix A in the microfiche.

[0035] Runtime system 38 includes additional functions 58 supporting operations such as input/output, network operations, graphics, printing, multimedia, etc.

[0036] Platform-dependent layer 34 includes a platform interface 60, an OS native layer 61, a microkernel 62, and a boot interface 64. Platform interface 60 includes virtual machine system function library handlers 66 which may be written in Java program language to provide support for system function calls received from virtual machine 40. Platform interface 60 further includes interrupt classes 68 also written in the Java programming language which support interrupt operations of computer system 10 and bus managers 44. Finally, platform interface 60 includes direct memory access (DMA) classes 70 and memory classes 72, each written in the Java programming language.

[0037] Microkernel 62 and OS Native Methods 61 consists of software components written in a language specific to CPU 12 (“native ” language) which support essential low-level hardware functions of CPU 12, such as resource allocation, interrupt process, security, etc. In particular, microkernel 62 includes, a plurality of kernel functions 74 including thread management, exceptions, timing, physical memory management, hardware interrupt processing, platform control, process management, library management, I/O support, and monitor functions. These functions may be performed by the Chorus microkernel commercially available from Sun Microsystems. Microkernel 62 also include debug function 76. OS Native methods 61 consists of interrupt native methods 78, DMA native methods 80 and memory native methods 82.

[0038] The final component of platform-dependent layer 34 is boot interface 64. Boot interface 64 provides for loading and initialization of software into memory 14 (FIG. 1) when computer system 10 is initially powered up. Boot interface 64 may load software stored in, for example, a floppy disk, mass storage 24 (FIG. 1), or software received from a network via input device 18.

[0039] Next, a general description of a method for processing interrupts will be described. When the software for computer system 10 is loaded, boot interface 64 and bus managers 44 construct a system database. The system database includes a device namespace and an interrupt namespace. The device namespace is also created by boot interface 64 and bus managers 44 and contains entries in the form of objects for the CPU, for each bus, and for each device of computer system 10. The interrupts namespace contains an entry, in the form of an object, for each interrupt source, that is, each device or bus capable of generating an interrupt.

[0040] The objects of the interrupt namespace are organized in the form of an Interrupt Source Tree, wherein each object is an Interrupt Source Entry (ISE). Each entry of the device namespace is cross referenced with an ISE, that is, an entry in the interrupts namespace.

[0041] Each ISE includes a reference to one or more components of interrupt processing code. These components include interrupt handlers, interrupt enablers, interrupt disabler, and interrupt acknowledgers supplied by the device drivers.

[0042] When an interrupt occurs, the microkernel generates an interrupt vector identifying the device which caused the interrupt, causes an interrupt dispatcher to execute, and supplies the dispatcher with the interrupt vector. The interrupt dispatcher references device namespace of the system database and determines the entry therein corresponding to the device identified by the interrupt vector. The interrupt dispatcher then determines the ISE cross referenced to the identified device and determines the interrupt handler specified by the ISE to process the interrupt from the identified device. The interrupt dispatcher then causes the determined interrupt handler to execute.

[0043] The material below provides an overview of the interrupt classes and interfaces which form a part of the present invention and which implement the process described above. The first section describes how an interrupt source (i.e. a device, bus, or CPU) is abstractly represented and then published to drivers. The second overview section describes what kinds of code can be associated with a device that interrupts and how code is registered to handle and manage interrupts. The third overview section describes how interrupt handlers are coordinated and synchronized. The fourth overview section describes how interrupt handlers are dispatched in response to an interrupt.

[0044] Abstracting Interrupt Sources

[0045] Interrupt Source Objects

[0046] An interrupt is the means by which a device requests attention from software, such as a device driver. A device may be embedded within the CPU, attached directly to the CPU's external bus, or attached to another expansion bus such as PCI. The present invention represents any device that is capable of interrupting as an interrupt source.

[0047] Interrupt sources are related to other interrupt sources. For example, a device on the CPU's bus interrupts the CPU at some CPU-specific level. The CPU's interrupt level is a source of interrupt as is the device itself. When a device on a PCI bus generates an interrupt, the signal is propagated over one or more bus bridges until the CPU itself is interrupted.

[0048] The topology of interrupt routing and the device topology are similar, but not always identical. Because of the possible differences between device and interrupt topology, a separate class of object is required to represent an interrupt source.

[0049] The present invention creates interrupt source objects to represent the CPU, each CPU interrupt level, and each bus-device combination using a level. FIG. 3 illustrates the concept of an interrupt source object for the CPU, each CPU-level (2 in this case), a bus interrupt source, and two device interrupt sources.

[0050] Interrupt Source Object Organization

[0051] The interrupt classes of the present invention manage the set of known interrupt sources. The set of active and possible interrupt source objects are organized in a hierarchical fashion within the JSD's interrupts namespace.

[0052] Interrupt Source Tree (IST)

[0053] The interrupts namespace (hereafter referred to as the Interrupt Source Tree (or IST) is pre-created in the Java System Database (JSD). Each JSD entry within the interrupt source tree represents a device capable of requesting attention via an interrupt. Each tier of the IST represents a finer and finer granularity of interrupt source from CPU (the tree root) to CPU-levels and buses (parent entries) and finally to devices (leaf entries).

[0054] Representing interrupt sources using a tree that is separate from the device tree has its advantages. Interrupt routing for example, doesn't always follow the device to bus connectivity. Some platforms require software to route and decode interrupt information, others have sophisticated hardware assist.

[0055] Designing device drivers and bus managers to handle all the various combinations of interrupt decode and dispatching logic is a nearly impossible task. The IST acts as a buffer, isolating and protecting portable device driver and bus manager software from the platform's interrupt hardware.

[0056] Each platform may require a differently shaped tree to convey the logic and flow of interrupt processing. The IST frees platform designers to use the latest and greatest interrupt controllers without fear that a driver will break. Device drivers never access interrupt controllers associated with a CPU (i.e. a PIC) or a bus bridge controller.

[0057] FIG. 4 shows how the previous example of related interrupt sources (See FIG. 3) is represented in the IST.

[0058] Interrupt Source Entries (ISE)

[0059] Each interrupt source is represented using a JSD entry called an Interrupt Source Entry (ISE). ISEs are Java objects that are accessed (sometimes concurrently) from both Java and native code.

[0060] An interrupt source entry sub-classes the JSD's base SystemEntry class.

[0061] import java.system.database. Entry;

[0062] public InterruptSourceEntry extends SystemEntry implements interruptRegistration ( . . . )

[0063] The ISE implements an interrupt registration interface consisting of methods that install and remove driver supplied code.

[0064] When creating an ISE to represent a bus, the maximum number of associated child (or device) ISEs must be specified. Pre-creating child “slots” has a number of advantages for the native code that must access an ISE at hardware interrupt level.

[0065] The first advantage for native code, is that all memory associated with the object can be easily locked down to prevent page faults. Most microkernels cannot support handling page faults at interrupt level.

[0066] Secondly, a bus ISE can store references to device ISEs in a pre-created array instead of using the SystemEntry's linked-list approach. Using an array within an ISE, allows bus managers to number the child devices and use that number as an array index. This is especially important at hardware interrupt level. Indexing into an array using JNI is much simpler than running a linked-list.

[0067] FIG. 5 illustrates a bus ISE's array of child ISEs.

[0068] IST Construction

[0069] The IST is built dynamically as JavaOS initializes the platform. First, the platform manager creates the interrupts namespace root, and installs itself as the manager of this namespace. (See JSD spec regarding. namespace managers) Next, the platform manager creates a single root CPU Interrupt Source Entry (ISE), and then proceeds to create a child ISE for each CPU interrupt level (capable of interrupt on this platform).

[0070] Device and Interrupt Namespace Coordination

[0071] As the device manager matches devices with drivers and buses with bus managers, the tree grows and handlers are installed. The platform manager and each bus manager that is activated grows the tree by adding child interrupt source entries. Each new child ISE is cross-referenced with a device entry in the device namespace, using a JSD property. FIG. 6 illustrates how the device and interrupt namespaces are cross-referenced.

[0072] IST Topology and Management

[0073] The Platform Manager, each bus manager, and each driver interact with ISEs and the IST in some manner.

[0074] Platform Manager Creates CPU and CPU-levels

[0075] The Platform Manager creates the interrupts namespace, and then creates a single CPU object and multiple CPU-level objects. Each JavaOS platform comes with built-in handlers (native and Java) for each CPU-level.

[0076] Bus Managers Grow and Shrink the IST

[0077] Bus managers, including the platform's CPU bus manager (i.e. Platform Manager) maintain the IST on behalf of drivers and other bus managers. For each device under the control of a bus manager, at least one entry in the IST is created to represent that device's interrupt source.

[0078] Device Drivers Use Entries in the ISE

[0079] Drivers construct interrupt source objects and then ask the appropriate bus manager to install it in the IST FIG. 7 illustrates what code manages which levels of the IST.

[0080] Interrupt Code Registration

[0081] This second overview section describes how code is registered to handle and manage interrupts.

[0082] Interrupt Code Types

[0083] Four kinds of code can be registered with an interrupt source entry: interrupt handlers, interrupt enablers, interrupt disablers, and interrupt acknowledgers.

[0084] An interrupt handler executes in response to an interrupt. Its job is to satisfy the device's request for attention, secure any realtime data, and return control to the operating system as soon as possible. The present invention provides three types of interrupt handlers, as set forth below.

[0085] An interrupt enabler places the device in a state where interrupts are possible or un-masked. A CPU interrupt enabler enables all interrupts sharing the CPU interrupt controller (internal or external). A CPU-level enabler un-masks just a single level of interrupt. A bus or device enabler un-masks just those interrupts from the bus or device.

[0086] An interrupt disabler places the device in a state where interrupts are impossible or masked.

[0087] An interrupt acknowledger communicates to hardware the fact that the OS and/or device driver has handled (or acknowledged) the interrupt. Acknowledgment can take place before or after a handler is actually dispatched.

[0088] Interrupt Handlers

[0089] The present invention recognizes three levels of interrupt processing, each level defining a handler and an execution context for that kind of handler. The microkernel oversees two of the three levels of interrupt processing. The third (Java-centric) level of interrupt processing is supported by the Java Virtual Machine using Java threads.

[0090] Each kind of handler associated with an interrupt processing level runs in its own special interrupt execution context. A single interrupt source can have none, any, or all of these handler kinds assigned to process interrupts working as a team of handlers.

[0091] Each level of interrupt processing can communicate state and data to any other level using the interrupt source entry as a common data exchange point. Two of these interrupt processing levels are deferred. A deferred interrupt level is desirable for non-realtime processing, and is triggered from native code only.

[0092] The three kinds of interrupt processing are:

[0093] First-level realtime native interrupt processing

[0094] Second-level deferred native interrupt processing

[0095] Third-level deferred Java interrupt processing

[0096] First Level Handler

[0097] The first kind of interrupt handler is a native interrupt handler that executes at CPU interrupt level. This handler is composed of native code that may or may not have been compiled from ‘C’. This handler does obey ‘C’ calling conventions defined for the processor, even if the handler is composed of assembly language.

[0098] Upon entry to the first-level handler, the microkernel has already saved processor registers and may have switched to a separate interrupt stack. The choice of which stack to run first-level handlers on is up-to the microkernel.

[0099] Many microkernels will dedicate an interrupt stack per-CPU for this purpose. Others will just execute the handler on the stack of the current thread, unwinding the stack upon the completion of the handler's processing.

[0100] The code in this kind of handler runs when invoked by the microkernel. Interrupt level execution context provides the following support services to the first-level handler. A first-level interrupt handler can use JNI (Java Native Interface) to:

[0101] Read and write data within the interrupt source object.

[0102] Traverse the IST and subsequently dispatch other first-level interrupt handlers.

[0103] Signal the object, so that waiting threads at second, third, or main execution levels run.

[0104] A first-level handler's job is to satisfy the immediate real-time needs of a device such as reading data from a device with limited buffering capability.

[0105] After satisfying the realtime needs of a device, a first-level interrupt handler can cause a second or third-level handler to be queued by the microkernel. A first-level handler can choose to pass state and/or data to deferred second and third level handlers through the interrupt source object using JNI to get and set data within the object.

[0106] The handler's ‘C’ function prototype matches that of an interrupt source object's native method prototype with a single long parameter that contains the current time since boot in microseconds. The handler returns an integer that signals whether or not the interrupt was processed by the handler. A native CPU-level interrupt handler is defined thusly:

[0107] typedef long firstLevelHandler(void*ise, int64_t when);

[0108] Multiple first-level interrupt handlers can be executing simultaneously, each at a different level. This is true in single CPU and also in a SMP system. In a SMP system however, the microkernel serializes the execution of each interrupt level so that 2 CPUs don't attempt to execute the same handler simultaneously.

[0109] First-level interrupt handlers are the highest priority code in the system, preempting other interrupt handlers and threads. Consequently, the time spent in a first-level interrupt handler should be kept to a minimum.

[0110] Second Level Handler

[0111] The second kind of interrupt handler runs in the context of a native interrupt thread. This handler is also composed of native code that obeys ‘C’ calling conventions, and is structured as a native method with a single parameter.

[0112] Like a first-level handler, a second-level handler has a limited number of support services at its disposal. Native handlers (first and second levels) may only use JNI to get and set ISE data and to invoke other native methods associated with the same ISE.

[0113] A second level interrupt handler is queued to run under two circumstances. A first-level interrupt handler can queue a second-level handler, or if no first-level handler exists, the microkernel will, automatically queue the second-level handler in response to an interrupt;

[0114] A native second-level interrupt handler is defined thusly:

[0115] typedef long secondLevelHandler(void*ise, int64_t when);

[0116] The native interrupt thread is created by the microkernel during the second-level handler registration process. The stack allocated for a native thread is at least a page in length.

[0117] Second-level interrupt handlers run after first-level interrupt handlers, and may preempt third-level handlers and other Java or native threads.

[0118] Third Level Handler

[0119] A Java interrupt handler runs in the context of a Java thread and therefore may use the full resources of the language, JavaOS, and JDK.

[0120] The Java interrupt handler can run in the context of any Java thread, including a pre-created Java system thread.

[0121] A third-level interrupt handler is queued to run under the following circumstances. If no first or second level handler exists for an interrupt source, the microkernel queues the third-level handler when the device interrupts.

[0122] A third-level interrupt handler can also run if queued by either a first or second level handler. Third-level interrupt handlers run after first and second-level interrupt handlers, and may preempt other low-priority threads.

[0123] A third-level Java based interrupt handler method in the DeviceInterruptSource class is defined as below and is over-ridden by the derived specific device driver classes to do some useful work.

[0124] public boolean handleThirdLevelInterrupt(long when)

[0125] return true;

[0126] }

[0127] Interfaces for Interrupt Code

[0128] Handlers, enablers, disablers, and acknowledgers must be registered with an interrupt source object before being recognized by JavaOS. When a new entry is added to the IST, the ISE inherits its parent's registered code. Later, code specific to the child is registered.

[0129] Java interfaces are defined for each kind of interrupt management code.

[0130] Interrupt Handler Interfaces

[0131] public interface DeviceInterruptManager extends

[0132] InterruptManagement {

[0133] public boolean setFirstLevelIntrHandler (int

[0134] firstLevelIntrHandler);

[0135] public boolean setSecondLevelIntrHandler (int

[0136] secondLevelIntrHandler);

[0137] public boolean handleThirdLevelInterrupt (long when);

[0138] . . .

[0139] }

[0140] The DeviceInterruptSource class implements the DeviceInterruptManager interface. The setFirstLevelIntrHandler method of this interface takes an integer parameter which is used to set an integer variable meant for storing the ‘C’ address of the native first level interrupt handler. A child class of DeviceInterruptSource that needs a first level handler should call it's native method to fetch the address of the first level interrupt handler. Next it should call the setFirstLevelIntrHandler method to store this value into the ISE. Once this ISE is inserted into the IST, the CpuLevelInterruptSource class methods can invoke the first level interrupt handler for this device using the ‘C’ function pointer stored in the ISE.

[0141] The second level interrupt handlers are handled similar to the first level interrupt handlers.

[0142] The third level Java based Interrupt handler, handleThirdLevelInterrupt has a dummy implementation in the DeviceInterruptSource class that is overridden in the child classes.

[0143] Interrupt Management Interfaces

[0144] public interface InterruptEnabler ( . . . )

[0145] public interface InterruptDisabler ( . . . )

[0146] public interface InterruptAcknowledger ( . . . )

[0147] Interrupt Level Management

[0148] First-level interrupt handlers are necessary when a device may lose data if not attended to in a timely fashion. The duration of a first-level interrupt handier should be measured in microseconds.

[0149] Second-level interrupt handlers are useful when doing extended realtime processing such as is necessary with multi-media applications.

[0150] Third-level interrupt handlers are useful when doing non-realtime processing such as mouse and keyboard event handling. Third-level interrupt handlers may experience sporadic latencies due to the necessity to synchronize with the virtual machine's garbage collector. If these latencies are unacceptable to the management of a device, a second-level interrupt handler should be used.

[0151] It is the job of the driver to choose when to use each level of interrupt processing. The present invention greatly simplifies the job of synchronizing multiple levels of interrupt processing.

[0152] Synchronizing Interrupt Handlers

[0153] With interrupt handling comes the problem of synchronization. The present invention allows a driver's non-interrupt level code to synchronize with all three levels of interrupt processing. We examine second and third-level handler synchronization first.

[0154] Each thread that executes second and third level handlers acquires the Java monitor associated with the ISE before executing the handler. A driver can thus prevent a second or third-level handler from running by just acquiring the ISE's monitor. If an interrupt handler was already running the driver will block until the handler releases the monitor. If the monitor was free, the driver will acquire the monitor and block any subsequent monitor acquisition attempt by a handler, until the driver releases the monitor.

[0155] Synchronizing with code not executing within a thread context (i.e. first-level handlers) requires the driver to enable and disable the interrupt source itself. Each interrupt source object implements an interface containing enable and disable methods for this purpose.

[0156] FIG. 8 illustrates the use of Java monitors in interrupt processing.

[0157] Queuing a Deferred Interrupt Handler

[0158] Native first-level and second-level interrupt handlers can choose to defer work to higher interrupt levels on a per-interrupt basis. A simple mechanism is required to allow drivers to defer work.

[0159] To defer work from a lower interrupt-level to a higher-interrupt level, an interrupt handler merely notes the current interrupt source object. Notifying the interrupt source object, causes the virtual machine to wake-up threads waiting on the interrupt.

[0160] For example, a third level interrupt handler can run in the context of a precreated Java System Thread or in the context of any other thread. The waiting thread maintains a loop something like:

[0161] public void run {

[0162] while (true) {

[0163] try {

[0164] long when =waitForNextInterrupt( );

[0165] handleThirdLevelInterrupt (when);

[0166] } catch (Throwable e) {

[0167] }

[0168] FIG. 9 illustrates the concept of deferred Interrupt handling:

[0169] Interrupt Dispatching

[0170] This section of the document describes the processing of interrupts, using three levels of handlers.

[0171] Dispatching an interrupt handler requires access to the IST. The IST is made accessible to the native methods of the JavaOS CpuLevelInterruptSource class during platform initialization.

[0172] The native portion of the interrupt class makes sure that each entry in the tree (a Java object) is locked down in the Java heap for the duration of its lifetime. A pointer to the ISE representing the CPU is stored in a static variable for safekeeping and access by the native interrupt dispatcher when called upon to handle an interrupt.

[0173] Interrupt Dispatcher

[0174] The JavaOS interrupt dispatcher is a component of native code that executes first and second-level interrupt handlers. The interrupt dispatcher is layered upon the microkernel, and actually registers itself as a handler of all interrupt vectors that the microkernel exports. FIG. 10 shows the interrupt dispatcher layered upon the microkernel.

[0175] The microkernel has no knowledge of the IST. The interrupt dispatcher presents itself to the microkernel as the sole handler of all interrupts. This design asks little of an underlying microkernel besides a simple interface to install and remove CPU vector interrupt handlers.

[0176] The following ‘C’ interface supports the interrupt dispatcher:

[0177] void (*native_handler) (int level);

[0178] void set_native_intr_handler (int level, native_handler func);

[0179] The “level” parameter designates a CPU level (or vector). The “func ” parameter designates a native interrupt handler. Passing in a null handler removes the handler. The microkernel passes the current interrupt level to the native handler as the sole parameter.

[0180] Bus and Device Interrupt Handling

[0181] Each bus and device has an associated interrupt handler. Bus interrupt handlers perform a special decoding function that actually augments the handler invocation logic used by the interrupt dispatcher.

[0182] A bus handler's job is to determine which device interrupt handler should be invoked next. The device interrupt handler is invoked by the bus interrupt handler using JNI. In the case of layered buses, multiple bus interrupt handlers may be invoked to decode an interrupt. Eventually a device handler will be invoked that actually processes the device's interrupt.

[0183] Bus and device interrupt handlers can exist at all levels of interrupt processing depending upon platform requirements and performance considerations. The process is always the same however. Bus interrupt handlers determine the source of the interrupt on a particular bus. Device interrupt handlers process the interrupt. The only difference at each level is the execution context: interrupt or thread, native or Java.

[0184] FIG. 11 illustrates bus and device interrupt handlers.

[0185] FIG. 12 illustrates the InterruptSource class hierarchy.

[0186] Performance Improvements

[0187] The present invention enables Java-level threads to directly process interrupts just by waiting on an InterruptSource object. This programming model eliminates the need to switch to a specially designated Java-level System Thread to invoke a handler.

[0188] For example, prior art networking drivers install an interrupt handler that wakes-up a “reader” thread within the driver. The present invention allows the “reader” thread to directly wait for the interrupt instead of relying on the special system interrupt thread to run. FIG. 13 shows performance improvement for an Ethernet Read interrupt.

[0189] The following section describes in greater detail the classes and interfaces of the present invention.

[0190] Public Interface InterruptSourceEntry Extends Entry

[0191] The classes described above are stored on a computer readable medium, such as floppy disks, a CD-ROM, or optical disk. Alternatively, they are supplied to computer system 10 in a read-only memory, or provided in the form of a computer data carrier wave over a network.

[0192] It will be apparent to those skilled in the art that various modifications and variations can be made in the disclosed process and product without departing from the scope or spirit of the invention. Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.