Auto-ranging current integration circuit

[0002] This application claims the benefit of provisional patent application No. 60/297,909 to Tang, filed Jun. 12, 2001.

[0003] 1. Field of the Invention

[0004] This invention relates to the field of current integration circuits.

[0005] 2. Description of the Related Art

[0006] It is often necessary to know the magnitude of a particular current over time. This can be determined with a current integrator.

[0007] Current integrators are well-known; a basic implementation is shown in FIG. 1. An operational amplifier A1 receives the current to be integrated I_inat its inverting input, with its non-inverting input grounded. A fixed integration capacitor C is connected between the op amp's output and inverting input. A switch SR is connected across capacitor C, which resets the integrator when closed. Input current I_in, is integrated on capacitor C to produce an output voltage V_outfrom A1.

[0008] This arrangement suffers a number of shortcomings, however. If V_maxis the maximum output voltage that A1 can produce, then the maximum charge Q_maxthat can be stored on integration capacitor C without causing A1's output to become saturated is given by Q_max=V_max*C. Thus, to achieve a high Q_maxrequires a large C value.

[0009] The minimum charge Q_minthat can be detected is also often of interest. This is also largely determined by the value of C. A small C value gives the circuit a high integration gain; i.e., V_outchanges quickly for a given input current. Thus, a small C value allows small charges to be detected, but also results in a small Q_maxvalue. A large C value gives a lower integration gain (V_outchanges more slowly for the same input current) and a larger Q_maxvalue, but also increases the minimum charge Q_minthat can be detected. These conflicting requirements act to narrow the range of input currents which can be accurately integrated with the FIG. 1 circuit.

[0010] One approach to solving this problem in shown in FIG. 2. An array of integration capacitors such as C_a, C_band C_care used to allow different integration gains to be selected, using respective switches S_a, S_band S_c. However, this arrangement conventionally requires that the capacitors, and thus the integration gain, be selected before the input current is integrated. If the magnitude of the input current or charge is unknown, it is difficult to select the correct capacitance to provide an integration gain which maximizes the integrator's signal-to-noise ratio.

[0011] An auto-ranging current integration circuit is presented which overcomes the problems noted above.

[0012] The present circuit includes an operational amplifier which receives an input current to be integrated. Initially, a first integration capacitor is connected between the op amp's output and inverting input, which integrates the input current and causes the op amp's output voltage to increase. Additional integration capacitors may be switchably connected in parallel with the first integration capacitor.

[0013] A control circuit operates the switches which select the additional integration capacitors. The control circuit is arranged to close one of the switches and thereby connect an additional integration capacitor in parallel with the first capacitor whenever the op amp's output exceeds a predetermined reference voltage, but before the output becomes saturated. In this way, a small integration capacitance is automatically employed for a small input current, and larger capacitance values are automatically switched in for larger input currents—which lowers the integration gain, prevents the output from saturating, and keeps the current integration circuit's signal-to-noise ratio high.

[0014] Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.

[0015] FIG. 1 is a schematic diagram of a known current integrator.

[0016] FIG. 2 is a schematic diagram of another known current integrator.

[0017] FIG. 3 is a schematic diagram of a current integration circuit in accordance with the present invention.

[0018] FIG. 4 is an alternative embodiment of a current integration circuit in accordance with the present invention.

[0019] FIG. 5 is a schematic diagram of a preferred embodiment of a current integration circuit in accordance with the present invention.

[0020] FIG. 6 is an alternative embodiment of a preferred embodiment of a current integration circuit in accordance with the present invention.

[0021] The basic principles of a current integration circuit per the present invention are illustrated in FIG. 3. An input current I_into be integrated is connected to the inverting input of an operational amplifier A1; A1's non-inverting input is connected to a bias voltage, such as ground.

[0022] An integration capacitor C1 is connected between A1's output and inverting input. Input current I_inis integrated on C1, which results in an output voltage V_outbeing produced by Al. One or more additional integration capacitors C2, . . . ,Cn are connected in series with respective integration switches S2, . . . ,Sn; when an integration switch is closed, its respective integration capacitor is connected in parallel with C1. The integration switches are opened and closed by means of respective control signals 10, 20 applied to the control inputs of respective switches.

[0023] The control signals 10, 20 are provided by a control circuit 30. Control circuit 30 receives the output V_outfrom A1 at one input, and a reference voltage V_refat a second input. Control circuit 30 is arranged to give the current integration circuit an auto-ranging capability. It does this by detecting when V_outexceeds reference voltage V_ref, and closing one of integration switches S2, . . . ,Sn before A1's output becomes saturated. Thus, if input current I_inis small, only integration capacitor C1 is connected to A1; this makes the circuit's integration gain and signal-to-noise ratio high. If A1's output increases such that it is close to saturation, control circuit 30 switches in another integration capacitor; this lowers the integration gain and thereby prevents I_infrom saturating A1's output. If the integration capacitance is still too small, control circuit 30 switches in additional integration capacitors as needed. In this way, the integrated charge is preserved and the integration of input current is not interrupted.

[0024] A current integration circuit in accordance with the present invention provides a number of advantages. For example, integration switches S2, . . . ,Sn may be operated during current integration, whereas in the prior art of FIG. 2, switches S_a-S_care selected before current integration begins.

[0025] A quantizer, such as an analog-to-digital (A/D) converter, might be connected to receive the output of the present current integration circuit. The invention's auto-ranging capability is useful for increasing the dynamic range of charges that can be measured with such a quantizer. For example, if there are two additional integration capacitors C2 and C3, with C2 three times larger than C1 and C3 twelve times larger than C1, the maximum integration capacitance would be 16 times the size of C1. If the total capacitance (C1+C2+C3) were chosen to accommodate a particular full-scale charge, then using just C1 for small charges would increase the circuit's dynamic range by a factor of 16, which is the equivalent of 4 bits.

[0026] The present invention preferably includes a reset switch SR which is connected between the op amp's output and inverting input and is also controlled by control circuit 30. In operation, prior to integrating I_in, reset switch SR and each of switches S2, . . . ,Sn are closed, thereby resetting or discharging the integration capacitors. All the switches are then opened, allowing an unknown input current I_into be integrated using C1. If I_inis such that A1's output approaches saturation, control circuit 30 closes additional integration switches as needed, in the manner described above.

[0027] The positions of additional integration capacitors C2, . . . ,Cn and integration switches S2, . . . ,Sn may be reversed without greatly affecting the operation of the integrator. This implementation is shown in FIG. 4.

[0028] A preferred embodiment of the invention is shown in FIG. 5. Integration capacitors C1, . . . ,Cn are arrayed as before, with each capacitor (including C1 in this embodiment) connected in series with a respective integration switch S1, . . . ,Sn. Reset switch SR is connected between A1's output and inverting input, and an input switch S_inis connected between the input current to be integrated (I_in) and A1's input.

[0029] Control circuit 30 preferably comprises a comparator A2 which receives V_outat one input and V_refat a second input; A2's output goes high (“toggles”) when V_outexceeds V_ref, and goes low when V_outfalls back below V_ref. A2's output is used to clock a number of D-type flip-flops FF₁, FF₂, . . . ,FF_n−1. The flip-flops are connected in series, with the Q output of one flip-flop connected to the D input of the next flip-flop; the D input of the first flip-flop in the series is connected to a logic “1”. The Q outputs of FF₁, FF₂, . . . ,FF_n−1are connected to the control inputs of respective ones of switches S2, . . . ,Sn. Control circuit 30 also includes control logic 40, which acts to initiate and terminate an integration cycle.

[0030] In operation: initially, control logic 40 resets D flip-flops FF₁, FF₂, . . . ,FF_n−1, opens input switch S_in, and closes each of S1, . . . ,Sn and SR to reset the integration capacitors. Means for simultaneously closing each of switches S1, . . . ,Sn are not shown, but are well-known to those of ordinary skill in the art of logic circuit design. Switches S1, . . . ,Sn are then opened. An integration cycle is begun by closing S_inand S1, such that unknown input current I_inis integrated using C1. C1 is preferably the smallest integration capacitor in the array, as this will optimize the signal-to-noise ratio for a small input current.

[0031] Output voltage V_outwill increase as the integration continues. If input current I_inis sufficiently large, the output of A1 will approach saturation—which occurs when V_outreaches V_max. Reference voltage V_refis preferably set to a value less than V_max, and also slightly lower than the maximum input of the quantizer, such that the output of comparator A2 toggles before A1's output saturates or before the quantizer saturates.

[0032] When V_outexceeds V_ref, the output of comparator A2 goes high, which provides a clock tick to each of the D flip-flops. The D input of FF₁is hard-wired to a logic “1”, so that when clocked, FF₁'s Q output goes high and closes integration switch S2. This connects integration capacitor C2 in parallel with C1, which lowers V_outand the circuit's integration gain; with V_outnow less than V_ref, the output of comparator A2 goes low. The integrated charge is now preserved and shared between C1 and C2, and integration of the input current is not interrupted.

[0033] If V_outagain exceeds V_refdue to the magnitude of I_in, A2's output will again go high and clock the D flip-flops. The Q output of FF₁, set to a logic “1” by the previous clock, is applied to the D input of FF₂, so that the new clock causes the Q output of FF₂to go high and close integration switch S3. This connects capacitor C3 in parallel with C2 and C1, lowers the circuit's integration gain and V_out(such that A2's output goes low again), and causes the integrated charge to be shared between C1, C2 and C3.

[0034] If the integration capacitance is still too small, additional capacitors are added one by one in the same manner. The integration cycle ends when control logic 40 resets D flip-flops FF₁, FF₂, . . . ,FF_n−1, opens input switch S_in, and closes each of integration switches S1, . . . ,Sn and SR to again reset the integration capacitors. In this way, the integration gain is automatically adjusted to avoid the saturation of A1's output, and to keep the circuit's signal-to-noise ratio high.

[0035] Note that the embodiment of control circuit 30 shown in FIG. 5 is exemplary; many other circuits could be used to detect the impending saturation of A1's output and to control switches S1, . . . ,Sn accordingly to prevent saturation.

[0036] As with the circuit of FIG. 3, the positions of integration capacitors C1, . . . ,Cn and integration switches S1, . . . ,Sn in the circuit shown in FIG. 5 may be reversed without greatly affecting the operation of the integrator. This implementation is shown in FIG. 6. Integration switches S1, . . . ,Sn, SR and S_inare preferably FET switches, made from one or more FET transistors. The gate of each FET serves as the switch's control input, and its drain and source serve as the switch's signal terminals. Flip-flops FF₁-FF_n−1are arranged to provide control signals which turn on their respective FET switches such that the resistance between their signal terminals is reduced to near zero. Note that other types of switches, including electromechanical switches, could also be used—as long as they are switchable by means of a control signal and present a near-zero resistance between their signal terminals when closed.

[0037] The closure of switches S2, . . . ,Sn causes the current integration circuit's output to change quickly when additional capacitance is switched in; this in turn causes transient voltages to appear at A1's inverting input. These transient voltages can adversely impact the linearity of the input current source (such as a photodiode). As such, it may be desirable to limit the magnitude of the voltage transients. One way to achieve this is to limit the slew rate of the control signals provided to integration switches S2, . . . ,Sn—assuming that the switches are such that the resistance between their signal terminals changes continuously with the control signal (as with FET switches). This can be accomplished with RC networks (not shown), for example, each of which is interposed between the Q output of a D flip-flop and the control input of the flip-flop's respective integration switch.

[0038] Another way in which the effect of voltage transients on the input current source can be reduced is by opening switch S_infor a brief period whenever any of said integration switches are switched from the open state to the closed state to isolate the input current source from the integration circuit. When switch S_inis temporarily opened, the input current will be integrated across the capacitance of the input current source, but this charge will be transferred to C1 when switch S_inis closed again.

[0039] While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.