Using a single control line to provide select and reset signals to image sensors in two rows of a digital imaging device

[0002] This application claims the benefit of U.S. Provisional Application No. 60/075,454, filed on Feb. 20, 1998, the full disclosure of which is incorporated by reference.

[0003] The invention relates to digital imaging devices, such as active pixel sensor and CCD arrays.

[0004] Digital imaging devices such as active pixel sensor (APS) and charge-coupled device (CCD) cameras include many image sensors arranged into arrays of columns and rows. Each image sensor collects electrical charge when exposed to light. Control signals provided to the image sensors periodically enable the sensors to transfer the collected charge, or voltage-mode signals derived from the charge, to an imaging circuit.

[0005] The inventor has recognized a desire to reduce a necessary number of control lines for a given application that drive the image sensors in a digital imaging array. One technique for reducing the number of control lines is to provide multiple control signals on lines that are shared by adjacent rows of sensors in the array. Many advantages result, including greater space resolution in the sensor array, reduced interlevel (e.g., metal to polysilicon) contacts in the APS circuit, and higher quantum efficiency for the sensors.

[0006] In one aspect, the invention features a digital imaging device that includes a plurality of image sensors arranged into an array of lines including rows and columns. At least one output line connects to the image sensors. A control line connects electrically to at least two different image sensors in two different lines. The control line delivers a select signal to at least one image sensor in one of the lines and delivers a reset signal to at least one image sensor the other line. The select signal causes the image sensor in the first line to place an output signal on the output line, and the reset signal clears information from the image sensor in the second line.

[0007] In another aspect, the invention features a digital imaging system that includes a plurality of image sensors arranged into an array of lines forming rows and columns. Each of the image sensors includes a photosensor that collects electric charge when exposed to light, a select circuit that generates an output signal indicating the amount of electric charge collected by the photosensor, and a reset circuit that removes collected charge from the photosensor. The system also includes a line decoder circuit. This circuit includes a plurality of control lines and a control circuit that delivers select signals and reset signals over the control lines. Each control line connects to image sensors in two lines of the array. Each control line delivers a select signal to the select circuits in one of the two lines and delivers a reset signal to the reset circuits in the other of the two lines.

[0008] In another aspect, the invention features a method for use in capturing an image with a plurality of image sensors arranged into an array of lines forming rows and columns. A select signal is delivered to at least one image sensor in a first one of the lines, and a reset signal is delivered to at least one image sensor in a second one of the lines. The select signal and the reset signal are delivered over a single control line. In response to the select signal, an output signal is delivered from the image sensor in the first line, and information is cleared from the image sensor in the second line.

[0009] Other embodiments and advantages are apparent from the following description and from the claims.

[0010] FIG. 1 is a schematic diagram of a conventional active pixel sensor (APS) circuit.

[0011] FIGS. 2 and 4 are schematic diagrams of two types of conventional active pixel sensors.

[0012] FIGS. 3 and 5 are timing diagrams for control signals delivered to the active pixel sensors of FIGS. 2 and 4.

[0013] FIG. 6 is a schematic diagram of an APS circuit in which a single control line is shared by two adjacent rows of sensors in the array.

[0014] FIGS. 7 and 9 are schematic diagrams of two types of active pixel sensors for use in APS circuits like that of FIG. 6.

[0015] FIGS. 8 and 10 are timing diagrams for control signals delivered to the active pixel sensors of FIGS. 7 and 9.

[0016] FIG. 11 is a schematic diagram of a logic circuit that drives a shared control line.

[0017] A conventional APS circuit 100 is shown in FIG. 1. In this circuit 100, a timing controller 102 and a row driver 104 together form a control circuit 105 that generates two types of control signals, known as select signals and reset signals, which control the readout of collected charge from each sensor 110A-I in the APS array 115. The control circuit 105 provides two control lines, a select line 106A-C and a reset line 108A-C, for each row 112A-C of sensors in the array 115. Each sensor 110A-I converts the collected charge into a signal and delivers this signal to one of several column lines 114A-C when the corresponding select line 106A-C is asserted. All collected charge is cleared from the sensor when the corresponding reset line 108A-C is asserted.

[0018] FIG. 2 shows a typical active pixel sensor 120. The sensor 120 includes a photosensitive element, e.g., photodiode 122 that collects charge when exposed to light. The charge is delivered at selected times to an output driver 124. The output driver 124 includes two transistors 126, 128 that deliver an output signal to the corresponding column line 130. One of these transistors is a source-follower transistor 126, the source of which connects to a power supply line (Vdd), and the gate of which connects to the cathode of the photodiode 122. The other transistor is a switching transistor 128 that connects the drain of the source-follower transistor 126 to one of the column lines 130. The gate of the switching transistor 128 connects to one of the select lines 132 extending from the control circuit 105.

[0019] The sensor 120 also includes a reset transistor 134 connected between the cathode of the photodiode 122 and the power supply line (Vdd). The gate of this transistor 134 connects to one of the reset lines 136 extending from the control circuit.

[0020] In operation, charge collected in the photodiode 122 diffuses into the gate of the source-follower transistor 126 and creates an output voltage on the column line 130 when the switching transistor 128 is activated by the select line. The reset transistor 134 begins conducting and thus clears collected charge from the photodiode 122 when the reset line 136 is asserted.

[0021] FIG. 3 shows the relative timing of the select and reset signals for two adjacent rows of sensors in the APS array. Each row of sensors has a corresponding select line, which delivers a select pulse 140A-B to each sensor in the row. Each row also has a corresponding reset line, which delivers a reset pulse 142A-B to each sensor in the row during the corresponding select pulse 140A-B. Charge that collects in the photodiode 122 during the portion of the select pulse 140A-B that follows the reset pulse 142A-B is treated as background noise. The charge that collects in the photodiode during the portion of the select pulse 140A-B that precedes the reset pulse 142A-B is attributable both to background noise and to the incoming image. The difference between the output signals generated during these two time periods indicates how much of the collected charge is attributable to the incoming image. The time interval between the rising or falling edge of the select signal 140A on one select line and the corresponding rising or falling edge of the select signal 140B on an adjacent select line is known as the “row clock period.”

[0022] FIG. 4 shows another typical APS sensor 145, which acts essentially as a single-stage charge-coupled device (CCD). In this sensor 145, a photogate 144 and a charge transfer gate 146 replace the photodiode of FIG. 2. Four control signals, including a select signal, a reset signal, a photogate (PG) signal, and a charge transfer (TX) signal, are provided for each row of sensors in the array. FIG. 5 shows the relative timing of the select, reset, and PG signals for two adjacent rows of sensors.

[0023] FIG. 6 shows an APS circuit 200 in which the number of control lines is reduced by almost a factor of two over conventional APS circuits. Instead of providing separate select and reset lines for each row of sensors, the APS circuit 200 includes control lines 202A, 202B, 202C, respectively associated with each row of sensors. One additional control line 202B is also needed.

[0024] The sensors are arranged in an array formed by lines including rows and columns 204A, 204B, 204C. Each control line 202B, 202C that is connected between two sensor rows 204B, 204C is shared by all of the sensors on those two adjoining rows. In particular, a shared control line 202B delivers a select signal to sensors in one row 204B and delivers a reset signal to sensors in another row 204A.

[0025] FIGS. 7 and 9 show alternative image sensors 210, 220 for use in the shared-line APS array 200. A photodiode 212 serves as the image sensing device in one of these sensors 210. A single-stage CCD, embodied as a photogate 222 and a charge transfer transistor 224, serves as the image sensing device in the other sensor 220. The reset circuit structures for these sensors 210, 220 are similar to those for the conventional sensors of FIGS. 2 and 4. However, the switching transistor 214 and the reset transistor 216 do not connect to a separate dedicated select line and a dedicated reset line, as shown in FIGS. 2 and 4. Rather, these transistors 214, 216 connect to shared control lines 218, 219. Each of these delivers both select signals and reset signals to sensors in two rows of the APS array. The single-stage CCD sensor 220 (FIG. 9) also receives a photogate signal (PG) and a charge transfer signal (TX) like those described above.

[0026] FIG. 8 shows the relative timing of the control signals on the shared control lines 218, 219 for the sensor 210 of FIG. 7. The upper control line 218 provides one or more select pulses 230 to the switching transistor 214. During the select pulse 230, the lower control line 219 delivers a reset pulse 232 to the reset transistor 216. The collected charge is cleared from the photodiode 212 during the reset pulse 232. The lower control line 219 later provides a select pulse 234 that activates the sensors in another row of the array. The centers of the reset pulse 232 and the select pulse 234 on each shared control line 219 are separated by a time interval that is equal to approximately one row clock period. In some implementations, the select pulse 230 on one control line 218 is deasserted during the corresponding reset pulse 232 on an adjacent control line 219, as shown by the dashed lines in FIG. 8.

[0027] FIG. 10 shows the relative timing of the photogate signal PG and the control signals provided on the shared control lines 218, 219 for the sensor 220 of FIG. 9. The lower control line 219 delivers a reset pulse 242 to the reset transistor, and then the upper control line 218 delivers one or more select pulses 242 to the switching transistor. During the select pulse 242, a photogate pulse 244 is delivered to the photogate 222, during which the photogate 222 transfers charge to the output driver. The lower control line 219 later delivers one or more select pulses 246 to the sensors in another row of the array.

[0028] FIG. 11 shows a logic circuit 250 that is used to generate control signals on a shared control line (LINE N). This circuit 250 is added to the conventional control circuit 105 of FIG. 1 to replace a pair of select and reset lines with a single shared control line. The logic circuit 250 receives standard select pulse and row select signals for a particular row N [SELECT(N), ROW_SELECT(N)] from a conventional row driver. The circuit 250 also receives a standard reset pulse for an adjacent row N−1 [RESET_(N−1)]. An AND gate 252 receives the SELECT(N) and ROW_SELECT(N) signals as input, and an OR gate 254 receives the RESET(N−1) signal and the output of the AND gate 252 as input. The output of the OR gate drives a control line (LINE N) that is shared by the sensors in row N and row N−1 of the array. The control line is asserted when both the ROW_SELECT(N) and the SELECT(N) signals are asserted and when the RESET(N−1) signal is asserted.

[0029] Other embodiments are within the scope of the following claims. For example, while the invention has been described in terms of an APS array, the invention is useful in other pixel based imaging systems. The invention also is not limited to the use of gated transistors, such as field effect transistors (FETs). Other switching devices, including other types of transistors, such as bipolar junction transistors, are used in some implementations. Also, while this system is described as being used for one control for two rows, it should be understood that the control could be shared between columns instead.