Electro-optic interconnect circuit board

[0002] This application is a continuation-in-part of U.S. Provisional Patent Application No. 60/234,138 filed on Sep. 21, 2000, now abandoned.

[0003] The field of the invention relates to optical devices and more particularly to the communication of information signals using optical devices.

[0004] Short electronic interconnects are often needed between semiconductor photonic devices such as lasers and photodiodes and electronic interface circuitry. This electronic circuitry could include photonic signal drivers and photonic signal receivers. This need for decreased distance between photonic devices and electrical interface circuitry increases as the signaling data rate increases.

[0005] Photonic components are often placed on simple carrier substrates to verify operation, to do burn-in, or simply to facilitate handling of that device. This photonic device and carrier substrate may then be placed on another substrate before additional packaging is completed. This packaging may add additional electrical interfaces, such as wire bonds and long non-controlled impedance wires, decreasing the electrical performance of the photonic device.

[0006] One example is an electro-optic TO can with an optical port. After placing the optical component in a can and making electrical wirebonds, further packaging must be done in the alignment to a fiber optic cable to the optical port. The additional packaging often involves placing structures around the TO can to support and align the fiber optic cable. The physical needs of the electrical connections and mechanical devices required for alignment often consume a great deal of space resulting in the introduction of significant distance between the optical device and the fiber. The physical need of the optical port also minimizes or eliminates the possibility of placing multiple optical devices on the same semiconductor substrate.

[0007] Some commonly used photonics devices (e.g., the vertical cavity surface emitting laser (VCSEL), photodiode structures, etc.) have both electrical contacts and optical ports on the same surface of the substrate. Placing optical ports and electrical contacts on a common surface particularly exacerbates packaging problems and optimization of the performance of these devices. These packaging problems are particularly exacerbated when more than one optical component is arrayed on a common substrate. Because of the importance of optical devices, a need exists for a simple yet reliable means of electrically and optically interconnecting such devices that does not rely upon trial and error.

[0008] A method and apparatus are provided for aligning a plurality of transmission paths of an array of optical devices with a plurality of optical fibers. The method includes the steps of disposing the optical array on a first side of the transparent substrate with the plurality of optical transmission paths passing directly through the substrate, disposing a signal processor on the first side of the transparent substrate adjacent the array of optical devices, disposing a set of alignment guides on a second side of the transparent substrate parallel to the plurality of transmission paths for aligning the plurality of optical fibers with the plurality of transmission paths and coupling a plurality of signals processed by the processor through the plurality of transmission paths between the optical array and plurality of optical fibers.

[0009] FIG. 1 shows an electro-optical converter cell in accordance with an illustrated embodiment of the invention, in a context of use;

[0010] FIG. 2 depicts the electro-optical cell of FIG. 1;

[0011] FIG. 3 depicts an optical array used in the cell of FIG. 1;

[0012] FIG. 4 depicts an alignment and boring fixture that may be used with the substrate of FIG. 1;

[0013] FIG. 5 depicts a connector and cell of FIG. 1;

[0014] FIG. 6 depicts an alternate embodiment of the system of FIG. 1;

[0015] FIG. 7 depicts details of the system in FIG. 6;

[0016] FIG. 8 depicts a further alternate embodiment of the system of FIG. 1;

[0017] FIG. 9 depicts a further alternate embodiment of the system of FIG. 1; and

[0018] FIG. 10 depicts an array of electro-optical cells used in the embodiment shown in FIG. 9.

[0019] FIG. 1 shows a signal processing assembly using a number of electro-optical converter assemblies (unit cells) 10 under an illustrated embodiment of the invention and in a context of use. The signal processing assembly includes a communications device (an application specific integrated circuit (ASIC)) 12 with a number of unit cells 10 distributed around a periphery of the communications ASIC 12 and which are electrically connected to the communications ASIC 12.

[0020] For example, the communications ASIC 12 may be an ultra-high speed router used as a hub in a communication system (e.g., Internet, PSTN, etc.). Further, the signal processing assembly of FIG. 1 provides an example of a device that may be mounted in a backplane of a rack in a communications cabinet.

[0021] Under the illustrated embodiment of FIG. 1, the router ASIC 12 may be a matrix switch with a number of connections and the ability of internally connecting any two external ports. Such devices 12 have great utility in routing signals (e.g., telephone signals, Internet protocol traffic, corporate Ethernet traffic, etc.).

[0022] The cells 10 may each form a number of electro-optical interfaces between the router 12 and external optical fibers through a waveguide connector 13 (FIG. 5). The waveguide connector 13, in turn, may engage and be aligned to the cell 10 through the interaction of an alignment guide 19 and receptacle 54.

[0023] FIG. 2 is a simplified view of one of the cells 10. As shown, the cell 10 may include an optical array 14, a signal processor 16 and a set of alignment guides 19 all disposed on a transparent substrate 20.

[0024] The optical array 14 may have a number of optical ports 22 (e.g., eleven ports shown in FIG. 2). Each port 22 may be a photonics transmitter (e.g., VCEL laser, DFB laser, etc.), a photonics receiver (e.g., a photodiode, PIN photodiode, etc.) or a combination transmitter/receiver.

[0025] The optical array 14 may be disposed on a first side of the substrate 20 in such a way as to transceive an optical signal along a number of optical paths that pass directly through a body of the substrate 20. The alignment guides 19 extend outwards from a second side of the substrate 20 and function to align a set of optical waveguides (e.g., optical fibers) 56 (FIG. 5) of the connector 13 to respective ports 22 of the optical array 14.

[0026] The signal processor 16 may be any of a number of signal processing devices. In the simplest configuration, the signal processor 16 may be an array of amplifiers. If the ports 22 are lasers, then the amplifiers may receive a driving signal from the router 12 on traces 17 and drive the lasers 22 through traces 15, accordingly. If the ports 22 are photodetectors, then signals received on traces 15 from the photodetectors are amplified within the signal processor 16 and are transferred to the router 12. Alternatively, if the array 14 is a mixture of lasers and photodetectors, then the signal processor 16 may simultaneously transfer signals in both directions.

[0027] Alternatively, the signal processor 16 may be a multiplexer and the ASIC 12 may be one or more Pentium III processors or digital signal processors (DSPs). Further, the number of electrical signal traces 17 supplying the multiplexer 16 may be much greater than the number of ports 22 necessary to service the data on those traces 17. The traces 17, in fact, may represent one or more data buses related to specific processors or functions of the ASIC 12.

[0028] The multiplexer 16 may contain an internal lookup table that relates specific buses to specific ports and to specific slots in those ports. Further, the allocation of slots to buses may be under the control of the ASIC 12.

[0029] As a further alternative and where the ASIC 12 are structured as one or more data processors, the signal processor 16, itself, may be a router. As each packet arrives on a bus 17, a header of the packet may be stripped off and decoded for a destination address. Upon recovering a destination address, the router 16 may recover routing information from a routing table identifying a particular port for transmitting to that destination. The router 16 may route the packet through the identified port 22 to the destination.

[0030] At a destination, a similar router 16 may receive and decode the packet. Upon decoding the packet, the router 16 may route the packet to an identified bus 17.

[0031] Because of the small electrical signals associated with the ports 22 (e.g., provided by photodiodes), the signal processor 16 may be placed as close as possible to the array 14 to maximize electrical signal integrity. FIG. 2, in fact, depicts the signal processor 16 placed on the same transparent substrate as the array 14. Since the substrate may be a relatively thin glass, the material of the substrate 20 may be shaped (e.g., provided with one or more 90 degree bends), but still remain rigid enough to maintain optical tolerances.

[0032] Glass also has a thermal expansion coefficient that is much closer to semiconductor devices 14, 16 (as compared to the metal substrates more commonly used in photonics packaging). This reduces temperature-induced misalignment between the packaged optical device shown in FIG. 2 and externally coupled optical fibers 56. Alignment features may also be placed in or on the substrate with micron or submicron accuracy, as described in more detail below. This greatly simplifies the alignment of the optical devices on the array 14 with optical fiber connectors 13 that may also have complementary alignment structures. Electrical traces may be placed on the opposite side of the substrate, to separate the electrical and optical interconnect requirements and simplifying packaging.

[0033] By multiplying the number of ports 22 in FIG. 2 by the number of cells 10 in FIG. 1, it may be observed that in the case where the ASIC is a router, the router 12 of FIG. 1 may form any of 16! (16 factorial) possible connections. By coupling the cells 10 directly to the router 12, the speed and switching capabilities of the combination shown in FIG. 1 may far exceed that possible with prior art devices.

[0034] Turning now to the cell 10, in specific, a brief description will be provided of the operational features and construction of the cell 10. Following a description of the cell 10, a description will be provided of the use of the cell 10 in conjunction with other devices (e.g., the router 12 of FIG. 1).

[0035] FIG. 3 depicts a view of the active side of the array 14. An axis of transmission of the ports 22 would be normal to the surface of the page of FIG. 3 (i.e., a laser 22 would transmit out of the page, a photodiode 22 would receive an optical signal transmitted into the page).

[0036] A series of connection pads 32 may be provided on the array 14 for purposes of making electrical connections with the active elements of the ports 22. Trace leads 34 may be used to interconnect the pads 32 with the ports 22.

[0037] Also present on the array 14 may be a registration target 36 surrounding each port 22. The registration targets 36 surrounding the ports 22 may be created during fabrication of the array 14 and may be precisely aligned to the axis of transmission of its respective port 22.

[0038] Similarly, the traces 15, 17 may be provided on the transparent substrate 20. The traces 15, 17 may be created by a conventional photolithographic process.

[0039] As a first step in assembly of the cell 10, the array 14 may be joined to the transparent substrate 20. Alignment is not especially important at this step in that the only criteria is that the solder pads of the array 14 contact the traces 15 disposed on the substrate 20. Other optical components (e.g., the optical processor 16) may be placed on the substrate, as shown in FIG. 2. Once the alignment with the traces 15, 17 has been made, the optical array 14 and signal processor 16 may be held in place by a mass rapid bonding process. Bonding could include adhesives, solder, stud bumps, or a similar material.

[0040] As a next step, a set of apertures 18 for receiving the alignment guides 19 may be formed in the transparent substrate 20. To form the apertures, a boring fixture 38 (FIG. 4) may be used. The boring fixture 38 may include a pattern recognition module 40 and lasers 42, 44. The pattern recognition module 40 may include software adapted to recognize and position itself over a line of targets.

[0041] Once recognition of the targets has occurred, the pattern recognition module 40 functions to identify a transverse line passing through the line of targets as well as a center point of the line of targets. The pattern recognition module 40 then positions its own transverse line and center point with the identified transverse line and center point. The lasers 42, 44 may be precisely aligned along the transverse line of the pattern recognition module 40. The lasers 42, 44 are also positioned a precise distance on either side of the center point of the pattern recognition module 40.

[0042] The pattern recognition module 40 may be programmed to view the array 14 through the transparent substrate 20 and identify the set of alignment targets 36 (e.g., the alignment targets 36 on opposing ends of the array 14). Once the pattern recognition module 40 has aligned itself with the registration targets 36 (and also the lasers 42, 44 on either side of the targets 36), the boring fixture 38 activates the lasers 42, 44 to ablate the holes 18 in precise alignment with the ports 22.

[0043] To complete assembly of the cell 10, a set of alignment pins 19 may be inserted into the holes 18, as shown in FIG. 5. Also shown in FIG. 5 is the waveguide connector 13 of FIG. 1 that engages the cell 10.

[0044] Included within the waveguide connector 13 may be a connector block 52 with a set of alignment apertures 54. As the set of apertures 54 engages the pins 19, a taper 58 on the pins 19 functions to align the block 52 with the substrate. As the block 52 engages the pins 19, the fibers 56 are brought into alignment with respective ports 22.

[0045] FIG. 6 shows an alternate embodiment of the invention. As shown, the router 12 may be disposed on a printed circuit board (PCB) or ASIC 60. The optical unit cells 10 may be disposed onto the PCB or ASIC package 60 around the periphery of the package 60. FIG. 7 is a greatly enlarged section of FIG. 6. The package may contain spaces for the electrical and optical IC's, 14 and 16 respectively, to fit into, and they may be connected to the package using any appropriate technology (e.g., adhesives, solder, stud bumps, etc.).

[0046] In another embodiment of FIG. 7, a number of unit cells 10 may be constructed on a single large substrate 62. These cells could be constructed together on the large substrate 62 (FIG. 8) to from a large array 64 of cells 10. These arrays of cells 10 may function as an Electro-Optic circuit board.

[0047] Further, as shown in FIGS. 9 and 10, the substrate 62 may be physically divided into rows, and each row of substrates provided with a 90 degree bend 66 along its longitudinal axis. The use of the bend 66 may allow the PCB 60 to be attached to a mother board, while simplifying the attachment of the optical connector 13.

[0048] Optionally, a number of cells 10 (FIG. 2) may be formed with a 90 degree bend 66 and attached to the communications device 12 as shown in FIG. 9. As above, the cells 10 may be mechanically and electrically connected to the device 12 using any appropriate technology (e.g., adhesives, solder, stud bumps, etc.).

[0049] A specific embodiment of a method and apparatus for coupling an optical array to optical waveguides has been described for the purpose of illustrating the manner in which the invention is made and used. It should be understood that the implementation of other variations and modifications of the invention and its various aspects will be apparent to one skilled in the art, and that the invention is not limited by the specific embodiments described. Therefore, it is contemplated to cover the present invention and any and all modifications, variations, or equivalents that fall within the true spirit and scope of the basic underlying principles disclosed and claimed herein.