Functional device unit and method of producing the same

[0002] 1. Field of the Invention

[0003] The present invention relates to a functional device unit, which includes a semiconductor device implemented thereon, and method of producing the unit.

[0004] 2. Description of the Related Art

[0005] Recently, as the MEMS (Micro Electro Mechanical Systems) technology progresses, various functional devices are promoted to combine with others. Ideally, it is preferable to integrate various functional devices, beginning with semiconductor devices, monolithically on an identical substrate. Considering electromagnetic and mechanical characteristics of each functional device, however, the monolithic integration is not applicable in many cases practically. In these cases, a method of hybrid implementation is employed to implement different functional devices in a batch and then combine them.

[0006] An example of such the hybrid implementation includes a structure for implementing semiconductor devices such as LSI, light emitting diode (LED), laser diode (LD) and photodiode (PD) in a recess (cavity) formed on a silicon base and the like. This implementation structure can be applied, for example, to a sensor head in an optical encoder.

[0007] FIG. 1 shows an example of such the implementation structure for semiconductor devices. A silicon substrate 1 has a recess (cavity) 2 formed thereon, which is employed to implement a semiconductor device 3 therein. The semiconductor device 3 has terminal pads that are connected to terminal pads 4 formed on a surface outside the cavity 2 via bonding wires 5.

[0008] The implementation structure shown in FIG. 1 has the following disadvantages. First, if the cavity has a deep step, it raises a difficulty for wire bonding and needs longer wires additionally. Therefore, disturbances such as vibrations easily influence on the structure, thereby reducing its reliability. In addition, a large stray capacitance of the wire effects electrically on the structure to cause performance degradations such as a signal delay.

[0009] The present invention has an object to provide a functional device unit capable of having an improved reliability and performance, and method of producing the unit.

[0010] A functional device unit, according to the present invention, includes an insulating substrate having a recess formed in a surface thereof; a wiring layer patterned on the surface of the substrate, the wiring layer continuously extending from the bottom of and via the side of the recess to the top surface of the substrate; and a semiconductor device implemented in the recess of the substrate in a flip-chip manner.

[0011] According to the present invention, a base for implementing semiconductor devices has a recess formed thereon. Awiring layer is formed on the bottom of the recess and continuously extends therefrom via the side of the recess to the top surface of the substrate. A semiconductor device is mounted on the implementation base in a flip-chip manner. Therefore, the functional device unit obtained is not influenced frommechanical disturbances and has high reliability, differing from those obtained by the conventional method of implementation using the wire bonding. Electrically, it can reduce a signal delay and achieve a high performance.

[0012] The functional device according to the present invention may serve, for example, as a sensor head of an optical encoder. In this case, a photodetector chip is implemented as the semiconductor device.

[0013] A method of producing a base for implementing a functional device, according to the present invention, has the steps of forming a recess in a surface of an insulating substrate; burying an insulating layer in the recess to planarize the substrate, the insulating layer consisting of a material different from the substrate; forming a photoresist mask over the substrate planarized with the insulating layer buried, the photoresist mask having a groove for wire-burying continuously extending from the top of the insulating layer to the outside of the recess; etching the insulating layer to remove parts exposing through the groove of the photoresistmask; depositing a conductive layer over the resist mask remaining on the substrate to form a wiring layer in the groove, the wiring layer continuously extending from the bottom of and via the side of the recess to the top surface of the substrate; and removing the photoresist mask and the insulating layer successively.

[0014] The method of producing according to the present invention employs the step of burying an insulating layer and the step of lifting-off to form the wiring layer on the substrate surface that has a step. That is, deposition of the insulating layer planarizes the recessed surface of the substrate. Then, lithography is employed to formaphotoresistmaskhavinga groove for wire burying on the planarized substrate, and a conductive layer is buried in the groove. Patterning the conductive layer is performed by the lift-off method, which removes the grounding insulating layer and photoresist mask. As a result, even though the recess in the implementation base has a deep step, the wiring layer can be reliably formed across the step.

[0015] A method of producing a functional device unit, according to the present invention, has the steps of forming a recess in a surface of an insulating substrate; burying an insulating layer in the recess to planarize the substrate, the insulating layer consisting of a material different from the substrate; forming a photoresist mask over the substrate planarized with the insulating layer buried, the photoresist mask having a groove for wire-burying continuously extending from the top of the insulating layer to the outside of the recess; etching the insulating layer to remove parts exposing trough the groove of the photoresist mask; depositing a conductive layer over the photoresist mask remaining on the substrate to form a wiring layer in the groove, the wiring layer continuously extending from the bottom of and via the side of the recess to the top surface of the substrate; removing the photoresist mask and the insulating layer successively; and implementing at least one semiconductor device in the recess of the substrate in a flip-chip manner.

[0016] Other features and advantages of the invention will be apparent from the following description of the preferred embodiments thereof.

[0017] The present invention will be more fully understood from the following detailed description with reference to the accompanying drawings in which:

[0018] FIG. 1 is a cross sectional view showing a structure for implementing semiconductor devices in the art;

[0019] FIG. 2 is a cross sectional view showing a structure for implementing semiconductor devices according to an embodiment of the present invention;

[0020] FIGS. 3A and 3B are a perspective view showing the step of processing a recess in an implementation base of the above embodiment and a cross sectional view thereof taken along an I-I′ line;

[0021] FIGS. 4A and 4B are a perspective view showing the step of depositing an insulating layer on the implementation base of the above embodiment and a cross sectional view thereof taken along an I-I′ line;

[0022] FIGS. 5A and 5B are a perspective view showing the step of planarizing the implementation base of the above embodiment and a cross sectional view thereof taken along an I-I′ line;

[0023] FIGS. 6A and 6B are a perspective view showing the step of lithography for the implementation base of the above embodiment and the step of etching the insulating layer and a cross sectional view thereof taken along an I-I′ line;

[0024] FIGS. 7A and 7B are a perspective view showing the step of forming a wiring layer in the implementation base of the above embodiment and a cross sectional view thereof taken along an I-I′ line;

[0025] FIGS. 8A and 8B are a perspective view showing the step of lifting-off for the implementation base of the above embodiment and a cross sectional view thereof taken along an I-I′ line;

[0026] FIGS. 9A and 9B are a perspective view showing an implementation base in an embodiment applied to a sensor head of an optical encoder and a cross sectional view thereof taken along an I-I′ line;

[0027] FIGS. 10A and 10B are a perspective view showing a structure of the above implementation base having slits formed on the recess bottom thereof and a cross sectional view thereof taken along an I-I′ line;

[0028] FIGS. 11A and 11B are a perspective view showing a structure of a sensor head including the implementation base and a photodetector IC mounted thereon and a cross sectional view thereof taken along an I-I′ line;

[0029] FIG. 12 is a perspective view showing a hybrid optical detector unit according to another embodiment;

[0030] FIG. 13 shows another implementation base formed of a silicon substrate;

[0031] FIG. 14 shows a layout of the optical grating formed of slits 16 and the photodiodes in the photodetector chip 14 in FIGS. 11A and 11B;

[0032] FIG. 15 is a cross sectional view of another sensor head, which corresponds to FIG. 11B; and

[0033] FIG. 16 shows a layout of the photodiode array of the photodetector chip in FIG. 15.

[0034] FIG. 2 shows a cross-sectional structure of a functional device unit according to an embodiment of the present invention. An implementation base 10 is formed of a silicon substrate 11 that has a high resistivity and is substantially insulating. A recess 12 is formed on a surface of the silicon substrate 11. A wiring layer 13 is formed in the recess 12, continuously extending from the bottom 12ato the top surface via the side 12bof the recess 12. A semiconductor device chip 14 is mounted on the implementation base 10 in a flip-chip manner. That is, the semiconductor chip 14 is face-down bonded such that terminal pads located on the surface can connect through bumps 15 with end portions of the wiring layers 13 located on the recess bottom 12a.

[0035] In the implementation base 10 of this embodiment, as described above, the wiring layer 13 is formed to continuously extend from the bottom 12aof the recess 12 to the top surface. Such the wiring layer 13 is difficult to form, if the recess 12 has a deep step, with a method of patterning a conductive layer using a usual lithography process. Then, in this embodiment, the implementation base 10 is produced in accordance with the following method. FIGS. 3A-B through 8A-B are a perspective view showing each step of producing the base and a cross sectional view thereof taken along an I-I′ line.

[0036] First, as shown in FIGS. 3A-B, anisotropic etching is performed to form a recess 12 on the silicon substrate 11. The recess 12 is a cavity with a step that is equal to or deeper than a thickness of a semiconductor chip to be implemented. Specifically, wet etching using an aqueous solution of KOH, TMAH or EDP is employed to form the recess 12. Alternatively, high concentration plasma etching such as ICP-RIE may also be utilized. Process conditions are selectively determined so that a side 12bof the recess 12 is tapered, and the bottom 12aand side 12bof the recess 12 have such a surface roughness that does not influence on a later film formation of a conductive layer.

[0037] Next, as shown in FIGS. 4A-B, an insulating layer 21 is deposited on the substrate 11. The insulating layer 21 is composed of a different material from the substrate 11. For the insulating layer 21, an organic insulating layer (such as resin layer, photoresist layer and the like) formed by spin coating, or an inorganic insulating layer (such as SiO2, SiN and the like) formed by CVD or sputtering can be used. It is preferable that the insulating layer 21 has such a character that can be uniformly filled up in the recess 12, and can be easily removed by O2 plasma etching. From this viewpoint, the SOG (Spin On Glass) layer, that is a coated insulating layer, is the optimum as the insulating layer 21.

[0038] Subsequently, a method of CMP (Chemical Mechanical Polishing) is employed to polish the insulating layer 21 so that the insulating layer 21 buried in the recess 12 forms a state of planarized surface as shown in FIGS. 5A-B. The CMP condition is optimally determined to prevent the insulating layer 21 from curling up at edges of the recess 12 and to match the position of the surface of the insulating layer 21 just with that of the top surface of the substrate 11 outside the recess 12.

[0039] Thereafter, a lithography is performed to pattern a photoresist mask 22 on the planarized substrate as shown in FIGS. 6A-B and then the photoresist mask 22 is employed to etch the insulating layer 21. It is preferable that the photoresist mask 22 has a sufficient resistance against O2 plasma. As shown in the FIGS. 6A and 6B, the resist mask 22 is patterned to have grooves 23 for wire burying, corresponding to a wiring pattern to be formed later. Each of the grooves 23 has a pattern that extends over the step of the recess 12. The insulating layer 21 exposed through the groove 23 is etched almost vertically.

[0040] For etching of the insulating layer 21, such an etching condition is employed that has a large selective ratio to the silicon substrate 11. Specifically, reactive ion etching (RIE) with O₂plasma may be used, for example. This etching can remove parts of the insulating layer 21 only exposed through the groove 23, barely etching the substrate 11. If the recess 12 has a depth of several 100 μm, for example, low pressure RIE with inductively coupled plasma (ICP-RIE) is effective.

[0041] Next, remaining the photoresist mask 22, as shown in FIGS. 7A-B, an Al layer 24 is deposited on it as a conductive layer. The Al layer 24 formed through the groove 23 of the resist mask 22 defines a wiring layer 13 that extends over the step of the recess 12. That is, the wiring layer 13 extends continuously from the bottom 12aof the recess 12 via the side 12bto the upper surface. For deposition of the Al layer 24, sputtering or CVD, that has good step coverage, may be employed. If the Al layer 24 is deposited excessively thick on the sides of the recess 12, however, it causes a trouble on etching to remove the insulating layer 21 later. Accordingly, it is preferable to select a deposition condition such that an Al layer 24 with the minimum thickness necessary for a wiring layer is formed on the side 12bof the recess 12.

[0042] Thereafter, as shown in FIGS. 8A-B, the resist mask 22 is removed to lift-off the unnecessary Al layer 24 thereon at the same time. Further, the insulating layer 21 remaining in the recess 12 is etched and removed to finish the implementation base 10. If the insulating layer 21 is formed of an organic material polymer) film, the use of an organic solvent can easily remove it without etching the remaining parts.

[0043] According to the embodiment described above, the method can produce the implementation base 10 including the wiring layer 13 that is formed thereon and extends from the bottom 12aof the recess 12 to the upper surface via the side 12b.Flip-chip implementation of the semiconductor device 14 in the implementation base 10 as shown in FIG. 2 can provide a functional device unit that is excellent in mechanical reliability and electrical performance.

[0044] A sensor head (i.e., pick-up) of an optical encoder is an example of functional devices, to which the present invention is applicable. In this case, the semiconductor device chip 14 is a photodetector chip. A specific configuration applied to a sensor head of an optical encoder will be described with reference to FIGS. 9A-B through 11A-B. FIGS. 9A-B show a perspective view of the implementation base 10 including the wiring layer 13 formed in accordance with the aforementioned process steps and a cross sectional view thereof taken along an I-I′ line.

[0045] Then, as shown in FIGS. 10A-B, lithography and ICP-RIE process are employed to form a plurality of slits 16 starting from the back surface of the implementation base 10 through the silicon substrate 11 that remains on the bottom of the recess 12. FIGS. 10A-B show the base in FIGS. 9A-B upside down. The slits 16 are serve as optical gratings (index gratings), which are positioned in front of photoreceiving surfaces of a photodetector chip 14 that is mounted on the implementation base 10, to modulate a light transmitted through or reflected from a scale and guide it to the photodetector chip 14.

[0046] Then, as shown in FIGS. 11A-B, the photodetector chip 14 is flip-chip bonded, facing its photoreceptive surfaces to the slits 16. It is preferable that a signal processing circuit for processing the received signals output from the photodetetor is integrally formed in the chip 14. Preferably, the photodetector chip 14 mounted is sealed in a plastic 17 as shown in FIG. 11B.

[0047] Thus obtained sensor head of the optical encoder can be thin and highly reliable.

[0048] The present invention is not limited to the above embodiment. Rather, it is also applicable to implementations of LSI chip, LED chip, LD chip and the like in similar structures. Although the above embodiment exemplifies the implementation of one semiconductor device chip, the present invention is similarly applicable to a hybrid device that includes a plurality of devices implemented therein.

[0049] For example, FIG. 12 shows another embodiment, which is applied to a hybrid optical detector unit. An implementation base 10 has the same structure and can be produced through the same process steps as those in the above embodiments. On the implementation base 10, a semiconductor light emitting device chip of surface emission type (for example, LED chip) 31, a semiconductor photodetector device chip (for example, photodetector IC chip) 32, and a signal processing IC chip 33 for processing a detected signal output from the photodetector device chip 32 are implemented in a flip-chip manner. Apertures for light transmission and detection are previously opened at parts on the bottom of the recess 12 where the LED chip 31 and the photodetector device chip 32 are to be mounted. A cover 34 is applied, as shown with a chain line, over the recess 21 that contains the devices implemented therein.

[0050] Thus obtained photo-detector unit is compact and hybrid.

[0051] In the above-described embodiment, it is necessary for the implementation base 10 that Si substrate 11 has a sufficiently high resistivity. If the leakage current that flows between the wiring layers 13 via the substrate 11 is not negligible small, as shown in FIG. 13, it is effective to form an insulating film 18 on the surface of the silicon substrate 11. The insulating film 18 is, for example, a silicon dioxide film formed by thermal oxidation. In detail, after forming the recess 12 in the silicon substrate 11 as shown in FIGS. 3A and B, and prior to depositing the insulating layer 21 as shown in FIGS. 4A and 4B, thermal oxidation is performed to form the silicon dioxide film on the whole surface of the silicon substrate 11. However, it is not necessary that the silicon substrate 11 is entirely coated by the insulating film 18. The insulating film 18 is formed at least on the bottom 12aand side 12bof the recess 12, and the top surface of the substrate 11.

[0052] On the silicon substrate 11 on which the insulating film 18 is formed, the wiring layers 13 are formed by the same processes as above described. The insulating film 18 can be used as an etching mask for forming the slits 16 by etching the silicon substrate 11.

[0053] Although a silicon substrate is employed as a material for the implementation base in the embodiment, other appropriate insulating substrates may also be employed. As the wiring layer, appropriate conductive materials other than Al can also be employed.

[0054] In the sensor head shown in FIGS. 11A and 11B, the index optical gratings formed of the slits 16 are disposed in front of the photodetector chip 14. In this case, in order to output 4-phases (i.e., A-, AB-, B- and BB-phases) displacement signals, as shown in FIG. 14, it is necessary to arrange index gratings 16A, 16AB, 16B and 16BB that are formed of slits 16, and to dispose 4 photodiodes PD1 to PD4 in the detector chip 14 corresponding to the respective index gratings.

[0055] By contrast, in such a case that the sensor head is formed such a type as to have no optical index grating in front of the photodetector chip, the sensor head may be formed as shown in FIGS. 15 and 16. FIG. 15 is a cross sectional view corresponding to FIG. 11A. FIG. 16 shows a layout of the photodetector array in the photodetector chip 14. As shown in these drawings, plural rectangular photodiodes PD are arranged, for example, at a pitch of 3 λ/4 (λ: scale grating pitch) so as to outputting A-,BB-,AB- and B-phase displacement signals. At the bottom of the silicon substrate 11, as shown in FIG. 15, an aperture 19 is formed so as to open to the photo receiving surface of the photodetector chip 14.

[0056] As obvious from the forgoing, for the purpose of forming a wiring layer from the bottom of a recess to the upper surface, a method is employed to form a groove for burying a wire and bury a conductive layer in the groove. Therefore, according to the present invention, even if the recess in the implementation base has a deep step, the wiring layer can be formed reliably. In addition, flip-chip mounting of semiconductor devices in such the implementation base can achieve a functional device unit that is excellent in mechanical reliability and electrical performance.

[0057] Having described the embodiments consistent with the invention, other embodiments and variations consistent with the invention will be apparent to those skilled in the art. Therefore, the invention should not be viewed as limited to the disclosed embodiments but rather should be viewed as limited only by the spirit and scope of the appended claims.