Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system

[0002] This application is a continuation of U.S. Ser. No. 09/006/322, filed Jan. 13, 1998, entitled METHOD AND APPARATUS FOR TRANSFERRING DATA IN SOURCE-SYNCHRONOUS PROTOCOL AND TRANSFERRING SIGNALS IN A COMMON CLOCK PROTOCOL IN A MULTIPLE AGENT PROCESSING SYSTEM, issued as U.S. Pat. No. 6,336,159 on Jan. 1, 2002, which is in turn a continuation-in-part of U.S. patent application Ser. No. 08/881,941 filed Jun. 25, 1997, entitled METHOD AND APPARATUS FOR SWITCHING BETWEEN SOURCE-SYNCHRONOUS AND COMMON CLOCK DATA TRANSFER MODES IN A MULTIPLE PROCESSING SYSTEM, issued as U.S. Pat. No. 5,919,254 on Jul. 6, 1999.

[0003] The present invention relates to the field of data transmission in computer systems.

[0004] Modern computer systems typically include multiple agents each coupled to a system bus. Typically, the agents are integrated circuit packages with multiple interfaces coupling each agent to the bus. The agents may include, for example, processors, memory devices, mass storage devices, etc. In order for the computer system to operate properly, agents should be able to communicate effectively with each other via the bus.

[0005] Existing computer systems typically transfer data between components or agents in accordance with a predefined clocking scheme. A system bus clock typically clocks data out of a sending device and into a receiving device. Consequently, it takes at least one complete clock cycles of a system bus clock to transfer data from one device to another device.

[0006] However, data may also be transferred in a source synchronous fashion in order to increase the speed of data transmission. In source synchronous transmission, a strobe is sent with a data transmission. This strobe latches the data into the receiving device in a time period that is typically shorter than the period of the system bus clock.

[0007] The source synchronous latched protocol operates a bus at a greater frequency. For example, two chunks of data may be driven onto the bus in the time it would take to drive one chunk in common clock transmission.

[0008] As a result, it would be advantages to provide a system that transmits data using a source synchronous protocol while transmitting control signals using a common clock protocol in order to increase the bandwidth of transmitting data without a corresponding increase in the number of signals transmitted.

[0009] The present invention provides a method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to the second agent, via a second transfer protocol.

[0010] FIG. 1 is a block diagram of a multiple agent computer system according to the present invention.

[0011] FIG. 2 is a diagram of transaction phases according to an embodiment of the present invention.

[0012] FIG. 3 is a timing diagram illustrating a common clock latched protocol.

[0013] FIG. 4 is a timing diagram illustrating a source synchronous latched protocol according to an embodiment of the present invention.

[0014] FIG. 5 is a block diagram of an agent according to one embodiment of the present invention.

[0015] FIG. 6 is a timing diagram illustrating a read 64-byte transaction with implicit write back using source synchronous transfer according to an embodiment of the present invention.

[0016] A method and apparatus for transferring control signals via a common clock protocol and transferring data via source synchronous protocol in a computer system is described. The transmission of the control signals is clocked by a system bus clock, while the transition of the data is clocked by strobes transmitted by the data source.

[0017] FIG. 1 is a block diagram of a multi-processor computer system which may be used with embodiments of the present invention. Computer system 100 comprises processor-memory bus 101 for communication between different agents coupled to bus 101, such as processors, bus bridges, memory devices, peripheral devices, etc. Processor-memory bus 101 includes arbitration, address, data and control busses (not shown). In one embodiment, each of processors 102, 103, 104, and 105 include a small, extremely fast internal cache memory (not shown), commonly referred to as a level one (L1) cache memory for temporarily storing data and instructions on the same integrated circuit as its associated processor. In addition, a larger, level two (L2) cache memory 106 is coupled to processor 105 for temporarily storing data and instructions for use by processor 105. In other embodiments, an L2 cache such as memory 106 can be coupled to any one of processors 102-105.

[0018] Processor-memory bus 101 provides access to the memory and input/output (I/O) subsystems. Memory controller 122 is coupled to processor-memory bus 101 for controlling access to a random access memory (RAM) or other dynamic storage device 121 (commonly referred to as main memory) for storing information and instructions for processors 102-105. Display device 132, keyboard device 133, cursor control device 134, hard copy device 135, and mass storage device 136 are coupled to system I/O bus 131 and to processor-memory bus 101 through bus bridge 124. Bridge 124 is coupled to processor-memory bus 101 and system I/O bus 131 to provide a communication path or gateway for devices on either processor-memory bus 101 or I/O bus 131 to access or transfer data between devices on the other bus. Bridge 124 is an interface between system I/O bus 131 and processor-memory bus 101. I/O bus 131 communicates information between peripheral devices 132-136.

[0019] Processors 102-105, bus bridge 124, mass storage device 125, and memory controller 122 each include a bus controller 138. Bus controller 138 controls communication over processor-memory bus 101 when the agent containing it has control of processor-memory bus 101.

[0020] In one embodiment of the present invention, bus activity on processor-memory bus 101 is hierarchically organized into operations, transactions, and phases. An operation is a bus procedure that appears atomic to software, such as reading a naturally aligned memory location. Executing an operation usually requires one transaction but may require multiple transactions, as in the case of deferred replies in which requests and replies are different transactions, or in non-lined memory operations which software expects to be atomic. In this embodiment, a transaction is the set of bus activities related to a single request, from request bus arbitration to the completion of the transaction (for example, a normal or implicit writeback response) during the response phase.

[0021] In one embodiment, a transaction contains up to six distinct phases. However, certain phases are optional based on the transaction and response type. Alternatively, additional phases could also be added. A phase uses a particular signal group to communicate a particular type of information. In one implementation these phases are:

[0022] ARBITRATION PHASE

[0023] REQUEST PHASE

[0024] ERROR PHASE

[0025] SNOOP PHASE

[0026] RESPONSE PHASE

[0027] DATA TRANSFER PHASE

[0028] In one embodiment, the data transfer phase is optional and is used if a transaction is transferring data. The data phase is request initiated if the data is available at the time of initiating a request (for example, for a write transaction). The data phase is response initiated if the data is available at the time of generating the transaction response (for example, for a read transaction). A transaction may contain both a request initiated data transfer and a response initiated data transfer, for example, a write which is converted to an implicit writeback).

[0029] In one embodiment of the present invention, the signals transmitted in relation to the arbitration phase, request phase, error phase, snoop phase, and the response phase are transmitted via the common clock protocol (i.e., clocked by the system bus), as will be described in more detail below. Data transmitted during the data transfer phase, however, is transmitted via a source synchronous protocol in order to transfer a greater amount of data per clock cycle, as will also be described in more detail below.

[0030] Different phases from different transactions can overlap, allowing bus usage to be pipelined and bus performance to be improved. FIG. 2 shows an example of overlap phases for two transactions. Referring to FIG. 2, transactions begin with an arbitration phase, in which a requesting agent becomes the bus owner. The arbitration phase needs to occur only if the agent that is driving the next transaction does not already own the bus. In one implementation, bus ownership is granted to the requesting agent in the arbitration phase two or more clock cycles after ownership is requested.

[0031] The second phase is the request phase in which the bus owner drives a request and address information on the bus. In one implementation the request phase is one or more clock cycles after bus ownership is granted (provided there is an arbitration phase), and is two clock cycles long. In the first clock an address signal is given along with the transaction type and sufficient information to begin snooping a memory access. In the second clock, byte enables used to identify which bytes of data should be transferred if the data transfer is less than the data bus width, the transaction identifier used to uniquely identify the transaction in the event a deferred response is to be given to the request, and the requested data transfer lengths are driven, along with other transaction information.

[0032] The third phase of a transaction is an error phase. The error phase indicates any immediate error, such as parity errors, triggered by the request. If an error is discovered, an error signal is asserted during the error phase by the agent which detected the error in the transaction. According to one embodiment, when an error is indicated, the transaction is immediately dropped (that is, the transaction progresses no further in the pipeline) and may be redriven by the agent which issued the transaction. Whether the agent reissues the transaction depends on the agent itself. In one implementation, the error phase is three clock cycles after the request phase.

[0033] In one embodiment, every transaction that is not canceled because of an error in the error phase has a snoop phase. The snoop phase indicates whether the cache line accessed in a transaction is not valid, valid or modified (dirty) in any agents' cache. In one implementation, the snoop phase is four or more clock cycles from the request phase.

[0034] The snoop phase of the bus defines a snoop window during which snoop events can occur on the bus. A snoop event refers to agents transmitting and/or receiving snoop results via the bus. An agent which has snoop results which need to be driven during the snoop phase drives these snoop results as a snoop event during the snoop window. All snooping agents coupled to the bus, including the agent driving the results, receive these snoop results as a snoop event during the snoop window. In one implementation the snoop window is a single bus clock.

[0035] The response phase indicates whether the transaction failed or succeeded, whether the response is immediate or deferred, whether the transaction will be retried, or whether the transaction includes data phases. If a transaction contains a response initiated data phase, then it enters the data transfer phase coincident with the response phase.

[0036] If the transaction does not have a data phase, then that transaction is complete at the response stage. If the requesting agent has write data to transfer or has requested read data, the transaction has a data phase which may extend beyond the response phase in the former case and will be coincident with or extend beyond the response phase in the latter case. The data phase occurs only if a transaction requires a data transfer. The data phase can be response initiated (for example, by the memory controller or another processor) or request initiated.

[0037] The bus accommodates deferred transactions by splitting a bus transaction into two independent transactions. The first transaction involves a request by a requesting agent and a response by the responding agent. The response includes the sending of the request data (or completion signals) if the responding agent is ready to respond. In this case, the bus transaction ends. However, if the responding agent is not ready to complete the bus transaction, then the responding agent may send a deferred response over the bus during the response phase. Sending of a deferred response allows other transactions to be issued and not held up by the completion of this transaction. When the responding agent is ready to complete the deferred bus transaction, the responding agent arbitrates for ownership of the bus and sends a deferred reply transaction which includes the requested data (or completion signals) on the bus.

[0038] Because, in this embodiment, the bus is of a pipeline nature, multiple transactions can be at different phases of the bus at different times. For example, one transaction can be at the snoop phase, while a second transaction is in the error phase, and a third transaction is in the request phase. Thus, error signals and request signals can both be issued concurrently on the bus even though they correspond to different transactions.

[0039] In one embodiment of the present invention, up to sixteen transactions can be outstanding on the bus at any particular time and up to sixteen transactions can be waiting for a deferred response at any particular time.

[0040] Additionally, one embodiment of the present invention also supports an implicit writeback, which is part of a read or write transaction. An implicit writeback occurs when a requesting agent places a request on the bus for a cache line which is stored in a modified state in a cache coupled to the bus. For example, an agent may perform a write transaction over the bus of 8 bytes of data (or some other amount of data less than or equal to a cache line), however, the cache line which includes those 8 bytes is stored in a modified state in another agent's cache. In this situation, the cache which contains the cache line in a modified state (or the agent which is coupled to the cache) issues a “hit modified” signal on the bus during the snoop phase for the transaction. The requesting agent places the 8 bytes of write data onto the bus, which are retrieved by the targeted agent. Then, coincident with the response phase of the transaction, the cache which contains the cache line in a modified state writes the cache line, which is 32 or 64 bytes in one implementation, to the bus. Any of the data in the cache line which was not written by the requesting agent is then merged with the write data from the original data transfer.

[0041] An implicit writeback may also occur with a read transaction. For example, a requesting agent may perform a read transaction which targets a memory controller on the bus, but which also hits a modified cache line in a snooping agents' cache memory. In this example, the snooping agent becomes the source agent and provides the requested data, as an implicit writeback, to the memory controller which in turns stores the writeback data into main memory. Also, in this example, the requesting agent takes the implicit writeback data from the bus (referred to as “snarfing” the data). In alternate embodiments, however, the memory controller may perform the snarfing, in which case the cache line will be taken off the bus by the requesting agent and may or may not be taken off the bus by the memory controller.

[0042] FIG. 3 is a timing diagram showing what occurs on the bus during a common clock transaction for the transmission of control signals, in accordance with one embodiment of the present invention. In timing diagrams herein, a square symbol indicates that a signal is driven, a circle symbol indicates that a signal is sampled (latched, or captured), and a triangle symbol indicates that the signal is received, or observed.

[0043] Signal names herein use uppercase letters, such as ADS#. Signals in a set of related signals are distinguished by numeric suffixes, such as A 4 for address bit 4. A set of signals covering a range of numeric suffixes if denoted as, for example, D[63-0] for data bits 0 through 63. A “#” suffix indicates that the signal is active low. No “#” suffix indicates that the signal is active high. The logic levels at which certain signals are active are merely choices made for particular embodiments and are not essential to the invention. The term “asserted,” implies that a signal is driven to its active logic level. The term “deasserted” implies that a signal is driven to its inactive logic level.

[0044] Bus clock signal BCLK 600 is active on its rising edge. At the start of clock cycle T1, signal A# 602 is asserted on the bus. At the start of T2, BCLK 600 latches signal A# 602. At the start of T3, B# 604 is asserted in response to the latching of A# 602. A# 602 changes state to its original, inactive state in T2. It can be seen from FIG. 3 that B# 604 is asserted in response to A# 602 two BCLK 600 cycles after A# 602 is asserted.

[0045] FIG. 4 is a timing diagram illustrating source synchronous data transmission for the transfer of data, according to one embodiment. As a result, the present invention allows the transfer of a greater amount of data per bus clock cycle compared to transferring data via a common clock protocol. As shown in the example of four chunks of data, D1, D2, D3, and D4 are sent and received. BCLK 600 operates with its normal frequency just as in the common clock transaction shown in FIG. 3. According to the source synchronous protocol shown in FIG. 4, data is sent and latched with strobes STBp[3:0]# 310 and STBn[3:0]# 312 to allow transfer rates twice the common clock transfer rate with reasonable signal flight times. The source synchronous latched protocol operates the bus at twice the frequency of BCLK 600. Two chunks of data are driven onto the bus in the time it would take to drive one chunk in common clock transmission. Therefore, bandwidth may be doubled without a corresponding increase in the number of signals transmitted.

[0046] As explained in Table IV, signals DRDYS# 428 and DRDY# 426 both active indicate that the sender is sending data in a source synchronous 128-bit mode. D# 302 comprises the data signals as seen by the driver. D# 308 comprises the data signals as seen by the receiver. STBp[3:0]# 304 and STBn[3:0]# 306 are strobe signals as seen by the driver of the strobe signals. STBp[3:0]# 310 and STBn[3:0]# 312 are the strobe signals as seen by the receiver of the data and strobe signals. On both the rising edge and the 50% point of the bus clock, the driver sends new data. On both the 25% point and the 75% point of the bus clock, the driver sends centered differential strobes STBp[3:0]# 304 and STBn[3:0]# 306. The receiver captures the data with the strobes deterministically.

[0047] In one embodiment, the driver predrives STBp[3:0]# 304 before driving D[63:0]# 302. The driver sends a rising and falling edge on STBp[3:0]# 304 and STBn[3:0]# 306 centered with data. The driver deasserts the strobes after the last data is sent. The receiver captures valid data with both strobe signals, asynchronous to BCLK 600. Signals synchronous to BCLK 600 (DRDYS# 428 and DRDY# 426) indicate to the receiver that valid data has been sent. FIG. 4 illustrate that if both agents are capable of 128-bit data transmission, data can be transmitted in half the time with respect to BCLK 600 as with the common clock protocol as shown in FIG. 3.

[0048] FIG. 5 is a block diagram showing an agent in more detail according to one embodiment of the present invention. Agent 400 includes a data width indicator 401, internal control logic 402, bus controller 138, data buffers 404 and 406, and multiplexors 403, 405, and 408.

[0049] Data width indicator 401 is an indicator of the data transfer widths supported by agent 400. In one embodiment, data width indicator 401 is a two-bit value which encodes the data transfer which is supported by agent 400. Data width indicator 401, according to one embodiment, is a preconfigured value. Indicator 401 can be preconfigured in any of the wide range of convention manners, such as having particular interfaces of agent 400 connected to particular predetermined voltage levels which are sampled at system reset periods. In other embodiments data width indicator 401 may be reconfigurable. For example, data width indicator 401 may be stored in a memory device or may be part of a configuration register that can be written to by software. Bus controller 138 provides an interface between agent 400 and bus 101. Bus controller 138 transfers various control and address signals between bus 101 and also controls the transfer of data to and from bus 101. As shown, bus 101 has a 64-bit wide data bus. In other embodiments, other data bus widths may be used.

[0050] A summary of the signals used with the present invention is shown in Table I below. The interaction of these signals is discussed more fully below.

[0051] Table I is a summary of signals used with the present invention, but is not an exhaustive list of signals transmitted by agent 400 or bus 101, but includes those signals most pertinent to the present invention.

[0052] Agent 400 also includes two sets of data buffers 404 and 406. Agent 400 includes two sets of input buffers 406 and two sets of output buffers 404. However, alternate embodiments could include more or fewer data buffers or data buffers that could be used for both input and output rather than having two different sets of buffers.

[0053] Data buffers 404 temporarily store data that is being transferred from agent 400 to another agent via bus 101. According to one embodiment of the present invention, each of data buffers 404 comprise four separate buffers, 404a,404b,404cand 404d,each capable of storing 64 bits of data. Each of data buffers 404 is input into a multiplexor 403. Multiplexor 403 is controlled by bus controller 138, thereby allowing bus controller 138 to control which 64-bit portion of data is provided to data lines D[63:32]# 418 and D[31:0]# 419 at any particular time. The output of multiplexor 403 is then input into a second multiplexor 405 which is also controlled by bus controller 138. Multiplexor 405 takes the 64 bits of data from multiplexor 403 and places either the upper 32 bits or the lower 32 bits onto the data lines D[31:0]# 419. In one embodiment, the group of 32 bits placed on data lined D[31:0]# 419 is dependent upon control signals received from bus controller 138, which are in turn dependent upon the data transfer width for the transaction, as discussed in more detail below. Additionally, the upper 32 bits from multiplexor 403 are also placed onto data lines D[63:32]# 418, thereby making the upper 32 bits available on the data bus for 64-bit wide data transfers, according to one embodiment.

[0054] Data buffers 406 temporarily store data that is being transferred from another agent to agent 400 via bus 101. According to one embodiment of the present invention each of data buffers 406 comprise four separate buffers each capable of storing 64 bits of data. Buffers 406 and multiplexor 408 are essentially the same as buffers 404 and multiplexors 403 and 405, except that they work in the opposite direction (that is, they operate to store data from the bus rather than transfer data to the bus). Data is received from D[31:0]# lines 419 and possibly D[63:32]# lines 418 and placed into one of data buffers 406 via multiplexor 408. Multiplexor 408 provides either 64 bits of data to a buffer 406 or 32 bits of data as the upper or lower 32 bits to a buffer 406, based on control signals from bus controller 138, which are dependent upon the data transfer widths for the transaction as discussed in more detail below.

[0055] Moreover, considering that the data has been transmitted asynchronous to the bus clock, the data will have been received by the agent 400 within a window that crosses a clock cycle boundary. As such, the received data is latched in deskew latches (not shown) within buffers 406 until accessed by the agent 400. Furthermore, the bus controller 138 typically uses the common clock signal to resynchronize the received data with the clock of the agent 400 by determining when the data is to be accessed from the agent 400. A more detailed explanation of one embodiment for performing the resynchronization can be found in the patent application “Source Synchronous Interface Between Master and Slave Using a Deskew Latch”, filed on May 6, 1997, assigned Ser. No. 08/852,438.

[0056] In one embodiment of the present invention, the agents may dynamically change between transferring data via the source synchronous protocol and the common clock protocol. That is, if all agents involved in the bus transaction support source synchronous transfer protocol, then data will be transferred accordingly. Otherwise, data is transferred via the common clock protocol.

[0057] For example, in one embodiment of the present invention when agent 400 is issuing a request on the bus, agent 400 provides an indication of the data transfer widths supported by agent 400. In one embodiment this indication is encoded in REQ[4:0]# 414, using REQ[4:3]# asserted in the second clock cycle of the request phase. An encoding of particular data transfer widths supported in this implementation is shown in Table II below, in which “0” indicates an inactive signal and “1” indicates an active signal.

[0058] The proper indication to be provided by agent 400 is based on the data width indicator 401. In one implementation, data width indicator 401 stores one of the four encoding shown in Table II, and can be placed directly on the bus by bus controller 138. If agent 400 is the target of the request issued by another agent coupled to the bus, then agent 400 also provides, as a target agent, an indication of the data transfer widths supported by agent 400. In one embodiment, this indication is provided using a combination of one or more of DRDY# 426, DRDYS# 428, TRDY# 420, and TRDYS# 422. A summary of the indications provided by these signals, based on what the requesting agent has indicated it supports, as shown in Table III below.

[0059] DRDY# 426 and DRDYS# 428 signals also indicate whether a transfer is in accordance with common clock protocol or source synchronous protocol. This is summarized in Table IV below.

[0060] In embodiments of the present invention in which different agents support up to 32, 64 or 128 bit transfers and which use signals as discussed above in Table III, agents participating in the transaction maintain a record in bus controller 138 of whether the data transfer width indicated as being supported by the requesting agent where 32- or 64-bit, or 64- or 128-bit. For response initiated transactions, a record of DRDY# 426 and DRDYS# 428 is kept. For request initiated transactions or implicit writeback transaction, a record of TRDY# 420 and TRDYS# 422 signals is kept. This record is kept to allow assertion of TRDY# 420 and TRDYS# 422 to indicate either a 64-bit or 128-bit transfer, depending on the original request. A snooping agent monitors TRDY# 420 and TRDYS# 422 signals. If agent 400 snoops a request on the bus which hits a modified cache line in the agent's cache, agent 400, which will be placing writeback data on the bus, indicates the data transfer data width supported by agent 400. In one embodiment, this indication is provided using one or more of the DRDY# 426 and DRDYS# 428 signals. The TRDY# 420 signal and TRDYS# 422 signal are asserted by the targeted agent, as discussed above. A summary of the indications provided by these signals, based on the data transfer widths both the requesting agent and the targeted agent have indicated they support, is shown in Table V below.

[0061] FIG. 6 is a timing diagram showing the events of a 64-byte read transaction with implicit writeback according to source synchronous protocol. In this embodiment, the data bus is 64 bits wide, so the transaction requires the transmission of eight separate chunks of 64 bits each.

[0062] In the example of FIG. 6, the requesting agent asserts ADS# 410 in T1 to initiate a 64-byte read transaction. In T2, the requesting agent asserts certain bits of request signals {REQ} 414 to indicate a 64-byte length and that it is a 64-bit/128-bit agent. During the snoop phase in T5, HITM# 416 is asserted by the snooping agent. In T7 the responding agent asserts TRDYS# 422 and TRDY# 420 to indicate that it is ready to accept writeback data and that it is capable of performing 128-bit data transactions in a source synchronous mode. Because the responding, or target agent is responsible for driving the appropriate TRDY#/TRDYS# signals based on the original request received, the snooping agent is relieved of this burden. In T8, the snooping agent samples TRDYS# 422 and TRDY# 420 asserted with deasserted DBSY# 424. In T9, the snooping agent begins the data phase by asserting DBSY# 424 and SBSY# 484. The snooping agent predrives STBp[3:0]# 480 at the 75% point of T9.

[0063] The snooping agent begins valid data transfer by asserting DRDYS# 428 and DRDY# 426 and driving valid data on D[63:0]# 608 on the rising edge and at the 50% point of BCLK 600 between T10 and T13. Two 64-bit chunks of data are driven onto the bus in one clock period of BCLK 600. The snooping agent drives a rising and falling edge on both STBp[3:0]# 480 and STBn[3:0]# 482 at the 25% and 75% point of BCLK 600 between T10 and T13 (the center of each data transfer). The snooping agent drives a rising edge on STBp[3:0]# 480 and at the 25% point of T14 to turn the bus over to the next agent.

[0064] About one clock cycle after the snooping agent drives the strobes, the centered strobes arrive at the requesting and responding agents to capture the data. With each arriving strobe pair a new chunk of data is captured into the requested and responding agents' buffers. In T11, the requesting and responding agents sample DRDYS# 428 and DRDY# 426 and know that data has been sent. Sometime later, the requesting agent and the responding agent latch the data into the BCLK 600 domain. Thus, FIG. 6 illustrates bus agents sending 128 bits of data in one clock period of a 64-bit bus using source synchronous protocol.

[0065] In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. For example, the present invention has been described with reference to particular system configurations, signal encodings, and data transmission widths. Various modifications and changes may be made to such specific details as described herein, without departing from the broader spirit and scope of the invention as set forth in the following claims.