Dual mode high voltage power supply for providing increased speed in programming during testing of low voltage non-volatile memories

[0002] The present invention relates generally to non-volatile memory integrated circuit devices, and more specifically to increasing the speed of programming such devices.

[0003] Non-volatile memory devices are used in the semiconductor integrated circuit industry in logic systems, such as microprocessors, and are used for creating storage elements such as memory boards or solid state hard disks. A conventional non-volatile or flash memory device includes a plurality of memory cells typically organized in the plurality of memory sectors. Within each memory sector, the memory cells are arranged in a array comprising a plurality of rows and a plurality of columns. A plurality of word lines are coupled to the respective rows of the memory cells, and a plurality of bit lines are coupled to the respective columns of the memory cells. Each memory cell is capable of storing one bit. During the operation of a conventional non-volatile memory, a memory cell is programmed by supplying a current from a high voltage power supply to the drain of the memory cell through the respective bit lines to which the memory cells are connected when the non-volatile memory is in a conventional embedded program mode.

[0004] With the advent of low and very low voltage flash non-volatile memories, operated at or below 2.7 V, the die area occupied by the on-chip voltage multiplier charge pump becomes prohibitively large. The reason for this increase in the size of the charge pump is explained below.

[0005] The open circuit voltage V_MOof a n-stage charge pump is approximately given by formula (1)

[0006] V_MO=n(V_DD−V_TH)  (1)

[0007] where

[0008] n=numbers of stages

[0009] V_DD=power supply voltage

[0010] V_TH=average threshold voltage for NMOS transistors in the charge pump chain.

[0011] With reference to FIG. 4, a state-of-the-art charge pump 20 is shown. The internal charge pump 20 receives a low voltage power supply V_DDat an input terminal 22 and produces a programming voltage V_Mat an output terminal 24. A plurality of diode-connected NMOS transistors 215 are connected in series between the input terminal 22 and the output terminal 24. Between each of the diode transistors 215 is a node 230. A clock signal CLK is supplied to a clock input 28 and is inverted by an inverter 223 to provide an inverted clock signal {overscore (CLK)} 221. The inverted clock signal 221 is inverted again by a second inverter 225 to provide a clock signal 212. Capacitors 219 are connected between each of the nodes 230 and one of the clock signals 212, 221. Alternating nodes (N1, N3, N5) are connected to the clock signal line 212 through one of the capacitors 219, while the other nodes (N2, N4, N6) are connected through a capacitor 219 to the inverted clock signal line 221.

[0012] In FIG. 4, the internal nodes 230 are labeled N_k, k=1, 2 . . . 6. The average voltage at node N_kis

[0013] {tilde over (V)}_k=k(V_DD−{tilde over (V)}_THk)  (2)

[0014] The average threshold voltage {tilde over (V)}_THkof the NMOS transistor at node N_kis affected by the substrate bias provided by the average node voltage {tilde over (V)}_k. Formula (3) provides an approximation of the substrate bias effect on increasing {tilde over (V)}_THk:

[0015] {tilde over (V)}_THk=V_THo+γ({square root over ({tilde over (V)})}_k+φ_B−{square root over (φ_B)})  (3)

[0016] Where {tilde over (V)}_THois the threshold voltage at zero substrate bias, γ is the substrate bias coefficient and φ_Bis the built in substrate (bulk) voltage. Typical values are:

[0017] V_THo≡0 for NMOS native transistors (No enhancement implant)

[0018] γ≡0.1÷0.9{square root over (V)}

[0019] φ_B≡0.6÷0.7V

[0020] A trial and error iterative computation for V_MOand {tilde over (V)}_THin formula (1) yields a typical value of {tilde over (V)}_TH=1.5V for n=8÷10 stages. With reference to FIG. 5, the open circuit voltage V_MO515 of the charge pump is plotted with respect to the power supply voltage V_DD519. Under load, V_Mhas the approximate behavior: $\begin{array}{cc}{\tilde{V}}_M={\tilde{V}}_{\mathrm{MO}}-n\frac{T}{C}·{\tilde{I}}_{\mathrm{LOAD}}& \left(4\right)\end{array}$

[0021] where T=clock period, C=capacitor value. Assuming that {tilde over (V)}_Mnominalshould be {tilde over (V)}_Mnominal=10V as imposed by the hot electron injection mechanism, the current capability of the charge pump is: $\begin{array}{cc}{I}_{{\mathrm{LOAD}}_{\max }}=\frac{{\tilde{V}}_{\mathrm{Mo}}-{\tilde{V}}_{M_{\mathrm{nominal}}}}{n\frac{T}{C}}& \left(5\right)\end{array}$

[0022] provided that {tilde over (V)}_Mo>{tilde over (V)}_Mnominl. From FIG. 5, it can be seen from the graph 525 that the current capability 515 decreases dramatically for lower values of V_DD519.

[0023] Moreover, if one assumes that the programming cell current (Flash hot electron injection mechanism) is I_{PRG CELL}≡200 μA., then the number of bits (q), i.e. memory cells, which can be simultaneously programmed is: $\begin{array}{cc}q=\frac{I_{{\mathrm{LOAD}}_{\max }}}{I_{\mathrm{PRG}\mathrm{CELL}}}=\frac{{\tilde{V}}_{\mathrm{Mo}}-{\tilde{V}}_{M_{\mathrm{nominal}}}}{n·\frac{T}{C}·I_{\mathrm{PRG}\mathrm{CELL}}}& \left(6\right)\\ q=\frac{n\left(V_{\mathrm{DD}}-{\tilde{V}}_{\mathrm{TH}}\right)-V_{M_{\mathrm{nominal}}}}{n·\frac{T}{C}·I_{\mathrm{PRG}\mathrm{CELL}}}& \left(7\right)\\ q=·\frac{C}{T}·\frac{n\left(V_{\mathrm{DD}}-{\tilde{V}}_{\mathrm{TH}}\right)-V_{M_{\mathrm{nominal}}}}{I_{\mathrm{PRG}\mathrm{CELL}}}& \left(8\right)\end{array}$

[0024] Assuming that C=100 pF and T=100 ns, and using Equation (8) with the other numerical values assumed above, the following results are obtained:

[0025] n=10

[0026] {tilde over (V)}_TH=1.5V

[0027] V_Mnominal=10V

[0028] I_{PREG CELL}=200 μA

[0029] C=100 pF

[0030] T=100 ns

[0031] q=[5(V_DD−2.5)]bits(with V_DDin volts)  (9)

[0032] Table 1 shows, in a second column, the number of bits that can be programmed at one time when the capacitance is 100 pF, based on various values of the power supply voltage V_DD, shown in the first column. The third column of Table 1 shows the corresponding capacitance value when the programming rate is fixed at eight bits at a time for each of the power supply voltage V_DDvalues of the first column.

[0033] The following results can be observed from Table 1. At V_DD=3V, one can either have C=100 pF and write only 2 bits at a time or, one can have C=320 pF and write 8 bits at a time. For comparison, at V_DD=4.5V, one can either have C=100 pF and write 10 bits at a time or have C=80 pF and write 8 bits at a time. Therefore, to be able to write 8 bits at a time, and to reduce the internal voltage from V_DD=4.5V down to V_DD=3V, the area of the charge pump capacitors has to be increased by 400% $\left(\frac{320\mathrm{pF}}{80\mathrm{pF}}\right),$

[0034] which is prohibitively large.

[0035] Attempts have been made in the prior art to increase the speed of programming flash non-volatile memories. U.S. Pat. No. 5,663,918 to Javanifard et al. discloses an integrated circuit having internal power supplies including circuitry for selecting either the external supply voltages or the internal power supplies to supply voltages to the remaining circuitry of the integrated circuit. The integrated circuit comprises voltage detector circuits for detecting the external voltage levels and a control circuit for selecting either the external supply voltages or the internal power supplies in response to the detected external voltages. The patent describes the mutually exclusive use of the external power supply and the operating supply voltage driven from the internal charge pump. Additionally, the regulation method is based upon the control of the frequency of the charge pump by means of a voltage control oscillator.

[0036] U.S. Pat. No. 6,014,332 to Roohparvar discloses a flash memory which includes circuitry to determine how many memory cells can be programmed in a single write operation by measuring the power available for programming.

[0037] It is the object of the present invention to provide a dual mode power supply for speeding up the programming of flash nonvolatile memories without having to increase the charge pump size when the flash memories are operated with low voltage power supplies.

[0038] It is a further object of the present invention to provide a dual mode high voltage power supply that has a first mode that programs using only the internal charge pump driven from the low voltage power supply VDD and a second mode that programs using the internal charge pump in conjunction with an external high voltage power supply in order to program a larger amount of memory cells simultaneously.

[0039] The above objects have been achieved by a dual mode high voltage power supply circuit having an external high voltage switch which determines whether the memory blocks of a nonvolatile memory circuit are programmed by an internal high voltage produced by an internal charge pump or are programmed by an external power supply high voltage in conjunction with the internal charge pump high voltage. When the dual mode power supply circuit is operating only on its internal charge pump high voltage, in order to keep the die area small, only one or two bits would be programmed at the same time. This is a first mode of operation. However, when the external power supply high voltage is available, eight or more bits can be written to at the same time, thus the throughput is four or more times larger. This is a second mode of operation. The switching from slow to fast programming mode can be dictated by a command or can be automatically executed by the flash memory itself based upon sensing the external voltage.

[0040] The dual mode power supply circuit includes the use of hysteresis comparator as a means of regulating the programming voltage by turning on or off the constant frequency clocks feeding the internal charge pump and additionally in the fast programming mode by turning on or off the external voltage switch. (The second power voltage is external but the switch controlling its distribution is internal.) This feedback loop built by the means of the hysteresis comparator allows the programming voltage from the internal charge pump to be matched by the external power supply as this programming voltage value is very critical for the overall performance of the non-volatile memory cells (both data retention and cell endurance).

[0041] FIG. 1 is a block diagram of the dual mode high voltage power supply circuit of the present invention.

[0042] FIG. 2 is a timing diagram of the programming signals for programming the memory blocks.

[0043] FIG. 3 is an electrical schematic diagram of the external voltage switch used in the dual mode high voltage power supply circuit of the present invention.

[0044] FIG. 4 is an electrical schematic diagram of the charge pump circuit used in the present invention and known in the prior art.

[0045] FIG. 5 is a graph showing the relationship between the low voltage power supply V_DDand the open circuit voltage of the charge pump of FIG. 4.

[0046] With reference to FIG. 1, the dual mode high voltage power supply circuit 15 of the present invention is shown. An internal charge pump 20 receives the regular power supply low voltage V_DDat an input terminal 22. The charge pump 20 receives a timing signal CHP-CLK at a clock terminal 28. A ground terminal 26 is connected to signal ground. The internal charge pump produces a programming voltage V_Mat an output terminal 24. A tank capacitor 44 is connected between the programming voltage output 24 and signal ground. The programming voltage V_Mis supplied to a common node 29 and then is used to program the plurality of memory blocks 46. Each memory block 46 is connected to a memory block switch 44 having an input terminal 45 to receive the programming voltage V_Mand a programming control terminal 42 to receive a programming control signal.

[0047] The timing for the power supply circuit 15 is generated from an on-chip oscillator 70 which produces a clock signal 72. The clock signal 72 is supplied to a clock terminal 58 of a flip-flop circuit 50 which produces an output 52. The output 52 of the flip-flop 50 and the clock signal 72 are input into an AND gate 80, and the output of the AND gate 80 is the CHP-CLK clock timing signal for the charge pump 20.

[0048] The dual mode high voltage power supply circuit 15 also includes a divider and hysteresis voltage comparator circuit 60. The hysteresis voltage comparator circuit 60 receives a reference voltage V_refat a reference terminal 62 and also receives the programming voltage V_Mat an input terminal 66. The output of the hysteresis voltage comparator circuit 60 is an analog enable signal EN_Owhich is produced at an enable output 64. The analog enable signal EN_Ois provided as the data input to the flip-flop 50.

[0049] An external voltage switch 30 determines whether the programming is conducted in the normal slower programming mode, in which only the low voltage power supply V_DDis used and only one or two bits are programmed at the same time, or whether the programming is conducted in the faster programming mode in which the high voltage power supply V_PPis used in conjunction with the low voltage power supply V_DD, and eight or more bits are programmed at once. The external voltage switch 30 receives the high voltage V_PPat an input terminal 38 and also receives a first enable signal EN at an enable terminal 33. The first enable signal EN is derived from the output of the flip-flop circuit 50. At a second enable terminal 36, the external voltage switch receives the fast program enable signal FAST-PEN, which is used to activate or deactivate the switch 30. A ground terminal 37 is connected to signal ground. The switch 30 also has a terminal 35 for receiving the low voltage power supply V_DD. The external voltage switch 30 produces the programming voltage on an output terminal 39 which joins with the output of the charge pump 24 at the common node 29.

[0050] The internal charge pump 20 can be implemented using the prior art state-of-the-art charge pump that was described with reference to FIG. 4 or can be implemented by any equivalent means that is known in the art. Similarly, the hysteresis voltage comparator circuit 60 can be implemented using any known hysteresis voltage comparator circuit, so long as the resulting program voltage is regulated to the internal voltage value. The desired result of the hysteresis voltage comparator circuit 60 is a constant internal load line when the regulator is on, so that the programming voltage can be matched by the external power supply. The AND gate 80 serves to gate the clock feeding the internal charge pump 20 in order to provide a complete clock cycle. Without the AND gate 80, the systolic two-phase charge pump described with regard to FIG. 4 would not work properly. The flip-flop circuit 50 rounds up the output analog enable signal EN_oof the hysteresis voltage comparator 60 to produce the enable signal EN which changes only on positive edges of the clock. In this way, the internal charge pump 20 will receive the clock CLK and the inverted clock CLK signals always in pairs of positive pulses through the signal CHP-CLK.

[0051] With reference to FIG. 2, the signal FAST-PEN, fast program enable 110, is used to enable the external voltage switch 30 and also to change the behavior of the program control block 40. With reference to FIG. 2, the program select signals (PS0) 100 through (PS7) 107 enable a memory block switch 44 to connect the high voltage programming signal V_Mwith one of the memory blocks 46 (memory blocks 0-7). Each memory block 46 corresponds to a bit in any byte stored in the flash memory. As shown in FIG. 2, when the fast program enable signal 100 is not activated (low), the dual mode high voltage power supply operates in the slower programming mode in which it only uses the internal charge pump driven by the low voltage V_DDfor programming. In this case, at each address, only two bits are programmed at any one time. For the first byte of data 130 it can be seen that the program select signals (PS7) 107 and (PS6) 106 are activated for programming at the same time and then next pair of program select signals (PS5) 105 and (PS4) 104 are activated after the first pair of signals (PS5) 105 and (PS4) 104 finish programming. This continues until all of the memory blocks have been programmed at a first address (addr 0) 130. At the next address, (addr 1) 140, the circuit is still operating in the slow programming mode, such that two bits are programmed at one time.

[0052] At the next address, (addr 2) 150, the fast program enable signal 110 is activated (high). As shown in FIG. 2, in the fast programming mode, all of the program select signals (PS0-PS7) 100-107 are activated at the same time. This allows all eight memory blocks to be programmed at once. This fast programming mode continues, while the fast program enable signal 110 is activated at the next addresses, (addr 3) 160 and (addr 4) 170. At each of these addresses, the dual mode high voltage power supply is in the fast programming mode which allows 8 bits or more at a time to be programmed.

[0053] During the fast programming mode, the internal charge pump circuit is operating even when the external voltage power supply is on. This is to maintain at least the same level of noise induced by the internal charge pump during testing in the fast programming mode as there is in the normal operation slow programming mode. If this were not the case, the testing would be too favorable for the device noise performance. The use of the same regulator to control the internal high voltage and additionally the external high voltage in all cases further ensures that testing is representative of the full load normal operation.

[0054] With reference to FIG. 3, the details of the external high voltage power switch 30 are shown. The external high voltage power switch 30 includes an input terminal 38 which receives the external power supply high voltage V_PPand an output terminal 39 on which is produced the programming voltage V_M. A switch resistor 308 is connected to the input terminal 38 and is in series with a diode-connected NMOS transistor 302 which is connected between the switch resistor 308 and the low voltage supply terminal V_DD35. A pair of PMOS transistors 304, 306 are connected in a cross-coupled manner between the diode 302 and the switch resistor 308. A high voltage enable line HVEN 330 is produced at the drain terminal of the first 304 of the pair of PMOS transistors. A NAND gate 320 receives a first enable signal EN1 at a first input terminal 33 and a second enable signal EN2 at a second input terminal 36. A NAND gate 320 produces a gate output on a terminal 325. The NAND gate output is connected to the gate of an NMOS transistor 318 which has a drain connected to the high voltage enable line 330 and a source terminal connected to ground 37. The NAND gate output 325 is also input to an inverter 316, the output of the inverter 316 being supplied to the gate of a second NMOS transistor 314. The NMOS transistor 314 has a source terminal connected to ground and a drain terminal connected to the drain terminal of the second PMOS transistor 306. The high voltage enable line 330 supplies the gate terminal of NMOS transistor 312. NMOS transistor 312 is a pass transistor and is connected at a drain terminal through a pass resistor 310 to the input terminal 38. The source terminal of pass transistor 312 is connected to the output terminal 39.

[0055] The cross coupling of PMOS transistors 304, 306 provides a positive loop which restores the full input voltage level on the high voltage enable line 330. Because the supply low voltage V_DDat terminal 35 is much smaller than the external supply high voltage V_PPsupplied at terminal 38, the internal supply voltage drive presented by the NAND gate 320 and the inverter 316 on the gates of transistors 318 and 314 may be insufficient to fight the external supply high voltage drive present on the gates of transistors 304, 306. For this reason, the switch resistor 308 will drop the voltage on the node connected to the sources of the transistors 304, 306 because of the total current flowing through transistors 318 and 304 and between 306 and 314 during the switching time.

[0056] The voltage on node N_TOP381 is being limited by the diode connected transistor 302 to a value just below the supply low voltage V_DD. This results in the switching time being shortened in comparison with a full collapse of the node N_TOPvoltage. The switch resistor 308 should be sufficiently large to allow the node N_TOP381 voltage to drop to the low voltage supply V_DDlevel so that transistors 318 or 314 can switch/toggle the current through the PMOS transistors 304, 306. After the switching, the current through the switch resistor 308 is zero, so the voltage on HVEN 330 goes to either the full external high voltage V_PP(as on the input terminal 38) or all the way to ground potential. In this way, the pass transistor M_PASS312 is fully turned on or off. The pass resistor R_PASS310 must match the order of magnitude of the output impedance of the internal charge pump.

[0057] Referring to FIG. 1, the hysteresis voltage comparator 60 works based upon the ripple on the programming voltage V_Mto turn on or off the charge pump 20. The charge pump 20 functions more like a current generator than a voltage generator. For this reason, if the external supply voltage V_PPswitch 30 has too low of a series impedance, the regulation feedback loop would not work properly because of the excessive ripple created the external supply voltage by V_PPon the tank capacitor C_TANK44. The charge pump output impedance is given by formula (10) which is derived from formula (4) above: $\begin{array}{cc}{R}_{{\mathrm{CHP}}_{\mathrm{out}}}=\frac{-\Delta V_M}{\Delta I_{\mathrm{LOAD}}}=n\frac{T}{C}& \left(10\right)\end{array}$

[0058] Using the numerical values from formula (9), this results in: $R_{{\mathrm{CHP}}_{\mathrm{out}}}=\left(10\right)100\frac{\mathrm{ns}}{100\mathrm{pF}}=10k\Omega$

[0059] The purpose of the external supply voltage V_PPis to boost the current capability of the internal charge pump. Assuming that the internal charge pump can supply 2 bits at a time, then in order to program eight bits, the external supply voltage V_PPhas to supply the remaining six bits, hence $\begin{array}{cc}{R}_{\mathrm{PASS}}=\left(\frac{\#\mathrm{of}\mathrm{internal}\mathrm{programmable}\mathrm{bits}}{\#\mathrm{of}\mathrm{all}\mathrm{bits}-\#\mathrm{of}\mathrm{internal}\mathrm{programmable}\mathrm{bits}}\right)R_{\mathrm{PASS}}=\frac{2}{8-2}·10k\Omega =3.3k\Omega & \left(11\right)\end{array}$

[0060] To match the external supply voltage V_PPload line with the internal charge pump load line, the external supply voltage V_PPneeds to be approximately equal to the programming voltage V_MO. These computations assume that the pass transistor M_PASS312 has a series resistance included in the resistance of the pass resistor R_PASS310.

[0061] The dual mode high voltage power supply architecture of the present invention enables fast parallel programming from an external power supply high voltage plus the internal charge pump voltage during testing for low voltage flash memories which have a slow serial access. The dual mode power supply circuit also allows one to program in a slower, low current, serial programming mode, which allows the internal charge pump to be of considerably smaller area on the silicon die.