Method for minimizing clock skew for an integrated circuit

[0002] The present invention relates to synchronizing clock pulses among layout blocks of an integrated circuit. More specifically, but without limitation thereto, the present invention relates to inserting a minimum set of delay cells between a clock driver and each circuit element to synchronize clock pulses in an integrated circuit.

[0003] An integrated circuit chip design typically includes a hierarchy of layout blocks, or hard macros (“hardmacs”). These circuit elements generally require a common clock pulse to synchronize their operation with one another. Because the wire length between a clock pulse generator and each circuit varies, the propagation delays in the wiring also vary. The clock pulses arrive at each circuit element at a different time due to the propagation delays in the wiring. This variation in propagation time of the clock pulses to each of the circuit elements is called clock skew. In high speed circuits, clock skew of 100 picoseconds may cause a malfunction in the chip.

[0004] Current methods for correcting clock skew add compensating lengths of wire to balance the propagation delays. A disadvantage of these methods is that the increased wire length increases capacitive coupling to other circuits and adds loading capacitance that may distort the clock pulse waveform.

[0005] The present invention advantageously addresses the problems above as well as other problems by providing a method for synchronizing clock pulses for an integrated circuit by a balanced clock tree with delay cells.

[0006] In one embodiment, the present invention may be characterized as a method for synchronizing clock pulses for an integrated circuit that includes the steps of (a) finding a relative delay with respect to a clock signal for a plurality of circuit elements and (b) inserting a delay cell between the clock signal and each of the plurality of circuit elements for each of the plurality of circuit elements that has a relative delay greater than a minimum delay to minimize clock skew.

[0007] The above and other aspects, features and advantages of the present invention will be more apparent from the following more specific description thereof, presented in conjunction with the following drawings herein:

[0008] FIG. 1 is a diagram of a typical clock fanout for an integrated circuit design;

[0009] FIG. 2 is a diagram of a clock balancing tree of the prior art for the clock fanout of FIG. 1;

[0010] FIG. 3 is a diagram of a clock balancing tree for the clock fanout of FIG. 1 according to an embodiment of the present invention;

[0011] FIG. 4 is a diagram of delay symbols for the clock balancing tree of FIG. 3;

[0012] FIG. 5 is a diagram of a physical layout for the stack of delay cells of FIG. 4; and

[0013] FIG. 6 is a flowchart of a method of minimizing clock skew for the clock balancing tree of FIG. 3.

[0014] Corresponding reference characters indicate corresponding elements throughout the several views of the drawings.

[0015] The following description is presented to disclose the currently known best mode for making and using the present invention. The scope of the invention is defined by the claims.

[0016] FIG. 1 is a diagram of a typical clock fanout 100 for an integrated circuit design. Shown in FIG. 1 are a clock driver 102, random logic flip-flops 104, and hard macros 106, 108, and 110. The clock driver 102 outputs a clock pulse to each of the random logic flip-flops 104, and the hard macros 106, 108, and 110. The wire lengths and corresponding propagation delays between the clock driver 102 and each of the random logic flip-flops 104, the hard macros 106, 108, and 110 are generally different, resulting in a relative clock phase shift or clock skew that may cause the integrated circuit to malfunction. A method of the prior art for balancing propagation delays to minimize clock skew is illustrated in FIG. 2.

[0017] FIG. 2 is a diagram of a clock balancing tree 200 of the prior art for the clock fanout of FIG. 1. Shown in FIG. 2 are a clock driver 102, random logic flip-flops 104, hard macros 106, 108, and 110, level 1 buffers 202, level 2 buffers 204, and long wires 206 and 208. The level 1 buffers 202 and the level 2 buffers 204 reduce the total delay, improve the clock skew, and avoid degradation of the clock pulse waveform due to large fanout load.

[0018] The clock pulse output from the clock driver 102 is connected to the level 2 buffers 204 and by the long wire 206 to the hard macro 110. The long wire 206 has a length with a corresponding propagation delay selected to balance the delay between the clock driver 102 and each of the other circuit elements, i.e., the random logic flip-flops 104, and the hard macros 106 and 108.

[0019] The output of each of the level 2 buffers is connected to two of the level 1 buffers 202 and by the long wire 208 to the hard macro 108. The long wire 208 has a length with a corresponding propagation delay selected to balance the delay between the clock driver 102 and each of the other circuit elements, i.e., the random logic flip-flops 104 and the hard macro 106. Balancing the propagation delays to approximately the same value for each of the circuit elements removes the relative phase shift of the clock pulses output from the clock driver 102, thus minimizing clock skew.

[0020] A disadvantage of the method of FIG. 2 is that the long wires 206 and 208 may generate capacitive coupling and loading that may adversely affect the operation of the circuit elements to which they are connected as well as other circuit elements in close proximity to the long wires 206 and 208.

[0021] FIG. 3 is a diagram of a clock balancing tree 300 for the clock fanout of FIG. 1 that uses a minimum set of delays instead of long wires for balancing propagation delays. Shown in FIG. 3 are a clock driver 102, random logic flip-flops 104, hard macros 106, 108, and 110, level 1 buffers 202, level 2 buffers 204, and delay cells 302 and 304.

[0022] The delay cell 302 is inserted between the clock driver 102 and the hard macro 110 to generate a delay selected to balance the delay between the clock driver 102 and each of the other circuit elements, i.e., the random logic flip-flops 104, and the hard macros 106 and 108 to minimize clock skew.

[0023] Likewise, the delay cell 304 is inserted between the clock driver 102 and the hard macro 108 to generate a delay selected to balance the delay between the clock driver 102 and each of the other circuit elements, i.e., the random logic flip-flops 104 and the hard macro 106 to minimize clock skew. A delay cell may include multiple delay cells connected in series to form a stack as shown in FIG. 4.

[0024] FIG. 4 is a diagram of delay symbols 400 for the clock balancing tree of FIG. 3. Shown in FIG. 4 is a stack of three delay cells 402, 404, and 406 that generate a combined delay selected to minimize clock skew.

[0025] FIG. 5 is a diagram of a physical layout 500 for the stack of delay cells of FIG. 4. Shown in FIG. 5 are delay cells 402, 404, and 406. Each of the delay cells 402, 404, and 406 is preferably a member of a minimum set of delay cells that may be connected in various combinations to generate any delay within a delay range at a selected granularity. For example, for a delay range of 100 picoseconds to 1150 picoseconds, a minimum set of five delay cells may be used to generate any delay within the delay range in steps, or granularity, of 25 picoseconds using a stack of from one to four delay cells as shown in Table 1 below. In this example, the minimum delay is 100 picoseconds. If the delay required to minimize clock skew is less than one-half the minimum delay, i.e., 50 picoseconds, then no delay cells would be inserted. Smaller minimum delays may be used to suit specific applications. The five delays cells in this example are 100, 125, 150, 175, and 400 picoseconds, respectively. Table 1 may be extended to a wider delay range, however some delays are not realizable with four or fewer of the minimum set of delays used to illustrate this example.

[0026] FIG. 6 is a flowchart 600 of a method of minimizing clock skew for the clock balancing tree of FIG. 3. Step 602 is the entry point for the flowchart 600. Step 604 finds a relative delay with respect to a clock signal for each circuit element for a plurality of circuit elements. Step 606 initializes a circuit element index i. Step 608 checks whether the relative delay of circuit element i is greater than a minimum delay. If yes, then step 610 inserts a delay cell stack between the clock signal and circuit element i to minimize clock skew. If no, control transfers to step 612. Step 612 increments the circuit element index i. Step 614 checks whether i exceeds the number of circuit elements. If no, control transfers to step 608. If yes, control transfers to step 616. Step 616 is the exit point for the flowchart 600.

[0027] Using standard delay cells instead of long wires by the method described above simplifies the layout of integrated circuit designs and greatly reduces unwanted coupling signals between interconnects.

[0028] While the invention herein disclosed has been described by means of specific embodiments and applications thereof, other modifications, variations, and arrangements of the present invention may be made in accordance with the above teachings other than as specifically described to practice the invention within the spirit and scope defined by the following claims.