Simultaneous processing for error detection and P-parity and Q-parity ECC encoding

[0002] This invention relates to processing of data information in error control encoding.

[0003] In parity-based error control procedures that are presently used, data representing a “bare” message, without error control bytes attached thereto, are read from memory three times: once to calculate an error detection control (EDC) segment, once to calculate a P-parity checkbyte, and once to calculate a Q-parity checkbyte for error correction control (ECC). Each read operation requires a certain time increment, and this triple reading of each data byte adds substantially to the total time required to generate error detection bytes and error correction bytes on a given data block.

[0004] What is needed is an approach that reduces to one the number of times a given array of data elements must be read from memory, without substantially increasing the time required for subsequent processing of the data for ECC encoding purposes. Preferably, the approach should be flexible enough to allow each data element received to be used for more than one computation and should not require that the error control procedures be performed in a particular order. Preferably, the approach should extend to data element arrays of arbitrary size.

[0005] These needs are met by the invention, which provides a modified procedure for using an array of data elements, each read once from memory, received separately at an EDC processor, at an ECC P-parity processor and at an ECC Q-parity processor, and processed in parallel in the three processors to compute an EDC error detection term and, simultaneously, to compute two ECC P-parity syndromes s0 and s1 and two ECC Q-parity syndromes. A first algorithm is used at the EDC processor to compute the EDC term by receiving the sequence {s(k)} of data elements (k=0, 1, . . . , M·N−1, with M=24 and N=43 in an example) in serial order and computing the EDC terms as the data elements are received. A second algorithm is used in parallel at the ECC-P processor to compute components of two ECC P-parity syndromes (and, optionally, two corresponding ECC P-parity checkbytes) as the data elements are received in serial order. A third algorithm is used in parallel at the ECC-Q processor to compute components of two ECC Q-parity syndromes (and, optionally, two ECC Q-parity checkbytes) as the data elements are received in serial order. Because the three processors operate independently but in parallel, the time required for combined EDC, ECC-P and ECC-Q processing is about one-third of what would otherwise be required, and each data element value s(k) need only be read once from memory.

[0006] FIG. 1 is a schematic view illustrating use of a data block for EDC, ECC-P and ECC-Q purposes.

[0007] FIGS. 2, 3A, 3B and 3C illustrate a 26×43 array of data elements, in a standard arrangement and rearranged so that the P-parity syndrome components and Q-parity syndrome components form columns and rows.

[0008] FIG. 4 illustrates a shift register configuration suitable for determining one or more EDC error detection checkbytes.

[0009] FIGS. 5, 6A, 6B, 7 and 8, and FIGS. 9, 10, 11 and 12, illustrate apparatus suitable for processing a single data stream to compute ECC P-parity and Q-parity syndromes, for a first embodiment and for a second embodiment, respectively.

[0010] FIGS. 13 and 14 schematically illustrate use of syndrome components s0[n2], s1[n2], s0′[n1] and s1′[n1], to form the appropriate checkbyte components c0[n2], c1[n2], c0′[n1] and c1′[n1].

[0011] FIGS. 15A and 15B are a flow chart illustrating a procedure suitable for simultaneously forming the EDC checkbytes and the ECC-P-parity and ECC-Q-parity syndromes and checkbytes.

[0012] FIG. 1 schematically illustrates processing of a data block, read once from memory, for EDC purposes, for ECC-P-parity purposes and for ECC-Q purposes. Data (16-bit in this instance) are read from a memory unit 11 and are received and processed by an EDC processor unit 13. The data read from memory are also received by ECC-P-parity and Q-parity processor units 15 and 17, which compute components for two ECC-P-parity syndromes and two ECC-Q-parity syndromes for the data stream. Computation of the ECC-Q syndromes requires use of the ECC-P syndrome component values so that the ECC-P syndromes are conventionally computed first and placed in a local register for subsequent use for ECC-Q purposes.

[0013] The P-parity test for ECC augments each column of the 24×43 array, with two double bytes, representing P-parity syndrome components, s0 and s1, so that each augmented column for P-parity is now 26×1, as illustrated in FIG. 2. Each of the two new rows, designated as s0 and s1, is a 16-bit, 1×43 array. The column entries for the two new rows are computed using linear processes involving only the data entries S(x) in the corresponding column. Thus, once all elements in a particular column, such as column 2, containing the data elements s(0002), s(0045), s(0088), . . . , s(0991), are read in, the syndrome components contributed by that column can be computed. The ECC P-parity check involves powers αⁿ(n=0, 1, . . . , 7) of an eight-bit primitive α that satisfies a selected primitive polynomial relation

[0014] p(α)=0.  (1)

[0015] For example, the primitive polynomial equation may be selected to be

[0016] p(α)=α⁸+α⁴+α³+α²+1=0,  (2)

[0017] and the “0” element, the “1” element and several powers of α become

[0018] 0={0,0,0,0,0,0,0,0},

[0019] α⁰={0,0,0,0,0,0,0,1}=α²⁵⁵(=“1”),

[0020] α={0,0,0,0,0,0,1,0},

[0021] α²={0,0,0,0,0,1,0,0},

[0022] α³={0,0,0,0,1,0,0,0},

[0023] α⁴={0,0,0,1,0,0,0,0},

[0024] α⁵={0,0,1,0,0,0,0,0},

[0025] α⁶={0,1,0,0,0,0,0,0},

[0026] α⁷={1,0,0,0,0,0,0,0},

[0027] α⁸={0,0,0,1,1,1,0,1}=α⁴+α³+α²+1,  (3)

[0028] α⁹={0,0,1,1,1,0,1,0}=α·α⁸=α⁵+α⁴+α³+α,  (3)

[0029] α²³⁰={1,1,1,1,0,1,0,0},

[0030] α²³¹={1,1,1,1,0,1,0,1},

[0031] α²³²={1,1,1,1,0,1,1,1},

[0032] where the particular powers αⁿ(n=230, 231, 232) will be needed in the following development. The remaining powers αⁿ(n=10≦n≦255) are generated using the particular primitive polynomial equation (2). Change of the choice of primitive polynomial will cause a corresponding change in definition of most of the powers of α.

[0033] The particular P-parity checkbytes c0 and c1 are formed as follows, using an array such as the one shown in FIG. 2. Two syndrome components s0 and s1 for P-parity are defined by $\begin{array}{cc}\mathrm{s0}\left[\mathrm{n1}\right]=\sum _{\mathrm{n2}=0}^{M-1}1·s\left(\mathrm{n1}+N·\mathrm{n2}\right)\left(\mathrm{n1}=0,1,\dots ,N-1\right),& \left(4\right)\\ \mathrm{s1}\left[\mathrm{n1}\right]=\sum _{\mathrm{n2}=0}^{M-1}{\alpha }^{M-1-\mathrm{n2}}·s\left(\mathrm{n1}+N·\mathrm{n2}\right),& \left(5\right)\end{array}$

[0034] where, for example, the choices N=43 and M=24 correspond to the array for P-parity error correction shown in FIG. 2. Two checkbytes, c0 and c1, are added for every code word to detect up to two errors per code word and to allow correction of up to one error per code word. The components of the two P-parity checkbytes are computed as follows.

[0035] c0[n1]=α²³⁰·s0[n1]+α²³²·s1[n1] (n1=0, 1, . . . , N−1)  (6)

[0036] c1[n1]=α²³¹·s0[n1]+α²³²·s1[n1].  (7)

[0037] With reference to FIGS. 2 or 3, the syndromes s0′ and s1′ for Q-parity have the components $\begin{array}{cc}{\mathrm{s0}}^{\prime }\left[\mathrm{n2}\right]=\sum _{\mathrm{n1}=0}^{N-1}1·{s\left(\left(N+1\right)·\mathrm{n1}+N·\mathrm{n2}\right)}_{\mathrm{R2}}\left(\mathrm{n2}=0,1,\dots ,M+1\right)& \left(8\right)\\ {\mathrm{s1}}^{\prime }\left[\mathrm{n2}\right]=\sum _{\mathrm{n1}=0}^{N-1}{\alpha }^{N-1-\mathrm{n1}}·{s\left(\left(N+1\right)·\mathrm{n1}+N·\mathrm{n2}\right)}_{\mathrm{R2}},& \left(9\right)\end{array}$

[0038] where the subscript “R2” on the data elements s((N+1)·n1+N·n2) indicates that the argument, (N+1)·n1+N·n2, is to be computed modulo R2, with

[0039] R2=N·M2=N·(M+2).  (10)

[0040] For the P-array shown in FIG. 2, N=43, M+2=26 and (M+2)·N=1118. As indicated in FIG. 2, computation of the Q-parity syndromes requires use of the augmented data elements lying along a diagonal, rather than in a column.

[0041] In the argument 1·n1+N·n2, the integers 1 and N are relatively prime to each other and have no common integer divisors except 1. The integer equation n1+N·n2=0 (mod R), with R=M·N, has no non-integer solution pair (n1,n2) in the ranges 0≦n1≦N−1 and 0≦n2≦M−1. The integer equation

[0042] 1·n1+N·n2=h1 (mod R) (0≦h1≦R)  (11)

[0043] has a solution pair (n1(h1),n2(h1)) in the range 0≦n1≦N−1 and 0≦n2≦M−1.

[0044] In the argument (N+1)·n1+N·n2, the two integers N and N+1 are relatively prime to each other and have no common integer divisors except 1. Thus, the integer equation (N+1)·n1+N·n2=0 (mod R2) has no non-zero solution pair (n1,n2) in the ranges 0≦n1≦N−1 and 0≦n2≦M+1. The integer equation

[0045] (N+1)·n1+N·n2=h2 (mod R2) (0≦h2≦R2−1)  (12)

[0046] has a unique solution pair (n1(h2),n2(h2)) in the range 0≦n1≦N−1 and 0≦n2<M+1. These results will be useful in constructing the P-parity and Q-parity components according to one embodiment of the invention.

[0047] As each checkbyte component, c0[n1] and c1[n1], is computed in the ECC-P processor 15, using Eqs. (4) and (5), this checkbyte component is added to row 25 (for c0) or to row 26 (for c1) for the corresponding column in FIG. 2. The two rows number 25 and 26 now have the respective row supplemental entries s(1032+n1)=c0[n1] and s(1075+n1)=c1[n1] (n1=0, 1, . . . , 42).

[0048] The Q-parity syndrome components are computed using diagonal sums of the data entries, as indicated in FIG. 2, in which the syndrome components s(1032+m1) and s(1075+m1) (m1=0, 1, . . . , 42) are now included as part of an augmented P-array. If the P-array shown in FIG. 2 is rearranged to the format of the 43×26 Q-array shown in FIGS. 3A, 3B, and 3C: (1) the P-parity syndrome components s0[n1] and s1[n1] are formed as weighted sums of the column entries s(k)=s(n1+43·n2) (n2=0, 1, . . . , M−1), with s(k)=0 (k=1032, . . . , 1117) initially; and (2) the Q-parity syndrome components s0′[n2] and s1′[n2] are formed as weighted sums of the row entries s(k)=s(44·n1+43·n2)_R2in FIGS. 3A, 3B, and 3C. The Q-array will be used for illustrative purposes in discussions to follow.

[0049] An EDC encoder computes and provides an error detection factor that is appended to a digital data stream to allow up to a selected number of errors to be identified in the data stream, as received, using a selected EDC polynomial G(x) for the coding. One suitable choice for the divisor polynomial G(x) is

[0050] G(x)=x³¹+x¹⁶+x¹⁵+x⁴+x³+x+1,  (13)

[0051] and this choice is used here for illustrative purposes.

[0052] FIG. 4 displays a linear feedback shift register (LFSR), suitably arranged to provide the divisor polynomial G(x). Let Q_n(i) represent the binary value contained in the flipflop number n in FIG. 3 (n=0, 1, . . . , 31) at a cycle time i (i=0, 1, 2, . . . ), and let B(i) be the ith binary value in a sequence of such values that are part of the digital data stream (arriving from the left). Each flip flop n contains a selected initial binary value at cycle time i=0. Three relations define the values contained in each flipflop at any later cycle time (i≧1):

[0053] Q₀(i)=B(i−1)⊕Q₃₁(i−1),  (14)

[0054] Q_m(i)=B(i−1)⊕Q₃₁(i−1)⊕Q_m−1(i−1) (m=1,3,4,15,16,31),  (15)

[0055] Q_n(i)=Q_n−1(i−1) (n≠1,3,4,15,16,31).  (16)

[0056] An EDC error detection factor, which is appended to the data stream, is the ordered sequence of bit values remaining in the LFSR shown in FIG. 4 after the entire data stream has passed through the LFSR. This sequence may be characterized as a remainder of the data stream of values S(x) modulo a selected divisor polynomial G(x).

[0057] The data stream S(x) of values will consist of 1032 two-byte codewords, which may be arranged as a 24×43 array of bytes, as illustrated in FIG. 2. Four bytes, representing an EDC factor for error detection, are appended to and depend upon the values of the data stream.

[0058] The EDC error detection factor discussed in the preceding is computed bit-by-bit. The EDC factor can also be computed one byte or, preferably, one word (two bytes) at a time, with appropriate changes in the normal (bit-by-bit) procedure. Where the EDC factor is computed one word at a time, the EDC error detection bits d[k], numbered k=0, 1, 2, . . . , 31 from LSB to MSB, are defined as follows.

[0059] d[0]=q[31]⊕q[30]⊕q[29]⊕q[28]⊕q[27]⊕q[26]⊕q[25]

[0060] ⊕q[24]⊕q[23]⊕q[22]⊕q[21]⊕q[20]⊕q[19]⊕q[18]

[0061] ⊕q[17]⊕q[16]⊕B[15]⊕B[14]⊕B [13]⊕B[12]⊕B[11]

[0062] ⊕B[10]⊕B[9]⊕B[8]⊕B[7]⊕B[6]⊕B[5]⊕B[4]⊕B[3]

[0063] ⊕B[2]⊕B[1]⊕B[0],

[0064] d[1]=q[16]⊕B[15],

[0065] d[2]=q[17]⊕B[14],

[0066] d[3]=q[31]⊕q[30]⊕q[29]⊕q[28]⊕q[27]⊕q[26]⊕q[25]

[0067] ⊕q[24]⊕q[23]⊕q[22]⊕q[21]⊕q[20]⊕q[19]⊕q[17]

[0068] ⊕q[16]⊕B[15]⊕B[14]⊕B[12]⊕B[11]⊕B[10]⊕B[9]

[0069] ⊕[8]⊕B[7]⊕B[6]⊕B[5]⊕B[4]⊕B[3]⊕B[2]⊕B[1]

[0070] ⊕B[0],

[0071] d[4]=q[19]⊕q[16]⊕B[15]⊕B[12],

[0072] d[5]=q[20]⊕q[17]⊕B[14]⊕B[11],

[0073] d[6]=q[21]⊕q[18]⊕B[13]⊕B[10],

[0074] d[7]=q[22]⊕q[19]⊕B[12]⊕B[9],

[0075] d[8]=q[23]⊕q[20]⊕B[11]⊕B[8],

[0076] d[9]=q[24]⊕q[21]⊕B[10]⊕B[7],

[0077] d[10]=q[25]⊕q[22]⊕B[9]⊕B[6],

[0078] d[11]=q[26]⊕q[23]⊕B[8]⊕B[5],

[0079] d[12]=q[27]⊕q[24]⊕B[7]⊕B[4],

[0080] d[13]=q[28]⊕q[25]⊕B[6]⊕B[3],

[0081] d[14]=q[29]⊕q[26]⊕B[5]⊕B[2],

[0082] d[15]=q[31]⊕q[29]⊕q[28]⊕q[26]⊕q[25]⊕q[24]⊕q[23]

[0083] ⊕q[22]⊕q[21]⊕q[20]⊕q[19]⊕q[18]⊕q[17]⊕q[16]

[0084] ⊕B[15]⊕B[14]⊕B[13]⊕B[12]⊕B[11]⊕B[10]⊕B[9]

[0085] ⊕B[8]⊕B[7]⊕B[6]⊕B[5]⊕B[3]⊕B[2]⊕B[0],

[0086] d[16]=q[31]⊕q[28]⊕q[16]⊕q[0]⊕B[15]⊕B[3]⊕B[0],

[0087] d[17]=q[29]⊕q[17]⊕q[1]⊕B[14]⊕B[2],

[0088] d[18]=q[30]⊕q[18]⊕q[2]⊕B[13]⊕B[1],

[0089] d[19]=q[31]⊕q[19]⊕q[3]⊕B[12]⊕B[0],

[0090] d[20]=q[20]⊕q[4]⊕B[11],

[0091] d[21]=q[21]⊕q[5]⊕B[10],

[0092] d[22]=q[22]⊕q[6]⊕B[9],

[0093] d[23]=q[23]⊕q[7]⊕B[8],

[0094] d[24]=q[24]⊕q[8]⊕B[7],

[0095] d[25]=q[25]⊕q[9]⊕B[6],

[0096] d[26]=q[26]⊕q[10]⊕B[5],

[0097] d[27]=q[27]⊕q[11]⊕B[4],

[0098] d[28]=q[28]⊕q[12]⊕B[3],

[0099] d[29]=q[29]⊕q[13]⊕B[2],

[0100] d[30]=q[30]⊕q[14]⊕B[1],

[0101] d[31]=q[30]⊕q[29]⊕q[28]⊕q[27]⊕q[26]⊕q[25]⊕q[24]

[0102] ⊕q[23]⊕q[22]⊕q[21]⊕q[20]⊕q[19]⊕q[18]⊕q[17]

[0103] ⊕q[16]⊕q[15]⊕B[15]⊕B[14]⊕B[13]⊕B[12]⊕B[11]

[0104] ⊕B[10]⊕B[9]⊕B[8]⊕B[7]⊕B[6]⊕B[5]⊕B[4]

[0105] ⊕B[3]⊕B[2]⊕B[1].

[0106] Four EDC bytes, edc[m] (m=0, 1, 2, 3) can be generated as indicated in FIG. 4, where edc[m] has the following eight-bit sequence:

[0107] edc[m]={d[8·m+0],d[8·m+1],d[8·m+2],d[8·m+3],d[8·m+4],d[8·m+5],d[8·m+6],d[8·m+7]}.  (17)

[0108] The ordered sequence of 32-bit values remaining in the LFSR, after the data bits B[k] are all passed through the apparatus and through an EDC bit order inverter, is the 32-bit EDC factor, where 16 consecutive bits (a word) are processed consecutively for EDC purposes.

[0109] Aram Perez, in “Byte-wise CRC Calculations”, I.E.E.E. Micro, June 1983, pp. 40-46, presents analysis of a 16-bit linear feedback shift register and an associated 16th degree CRC polynomial, G(x)=x¹⁶+x¹⁵+x²+1, that can be used to provide byte-wise, rather than bit-wise, CRC calculations. For a 16-bit LFSR array, configured according to the CRC polynomial above, the upper eight component registers (R₉-R₁₆) have contents such as x1⊕x2⊕x3⊕x4⊕x5⊕x6⊕x7⊕x8, x1⊕x2⊕x3⊕x4⊕x5⊕x6⊕x7, and xm⊕x(m+1) (m=2, 3, 4, 5, 6), where xk=C_k⊕M_kis the Exclusive-Or combination of an initial register bit value C_kand an input bit value M_k. The lower eight component registers (R_1-R8) contain terms such as x1⊕x2⊕C₁₆, x1⊕C₁₅, C_m(m=10, 11, 12, 13, 14) and x1⊕x2⊕x3⊕x4⊕x5⊕x6⊕x7⊕x8. Using the developed formalism, the author infers that a CRC calculation can be performed on eight bits (one byte) at a time by pre-loading appropriate values into the registers and into the data input queue (M_k).

[0110] Byte-wise, rather than bit-wise, CRC calculations may be implemented in the registers R₉-R₁₆registers in the following manner. The bit combinations for the upper eight component registers are prepared in parallel and are positioned at the input terminals of the registers R₉through R₁₆. In the next time cycle for processing one bit, these input values are loaded into the registers R₉through R₁₆. This achieves the equivalent of a byte-wise CRC calculation in a time corresponding to processing of one bit. This technique can be extended to word-wise CRC calculations, handling 16 bits or one word at a time, by making use of a 32nd degree CRC polynomial, such as the polynomial G1(x)⊕G2(x), where G1(x) and G2(x) are 16th degree divisor polynomials. Use of byte-wise or word-wise CRC calculations rather than the standard bit-wise CRC calculations provides extra time savings.

[0111] The procedure discussed herein has been extended to M×N arrays of data elements {s(n1+N·n2)|0≦n1≦N−1; 0≦n2≦M−1} from the particular choices M=24 and N=43. This invention allows the system to read in each element in the data array once, receive the data element at the EDC processor and at the ECC processor, and process the data element in parallel to compute the EDC error detection term and components of the ECC checkbytes c0 and c1.

[0112] The particular 32nd degree divisor polynomial used in the EDC processor and set forth in the relation (12) can be replaced by any other suitable 32-bit divisor polynomial. In particular, the 16th degree CRC-16 polynomial in the primitive relation (1) can be replaced by another suitable polynomial, such as G3(x)=x¹⁶+x¹²+x⁵+1, G4(x)=x¹⁶+x¹²+x²+1, G5(x)=x¹⁶+x¹⁴+x+1, G6(x)=x¹⁶+x¹¹+x⁴+1, or G7(x)=x¹⁶+1. The 32nd degree divisor can also be used to implement apparatus that performs word-wise (or, if preferred, byte-wise) CRC calculations for the EDC factor used for error detection.

[0113] The system shown in FIG. 1 may be characterized as a first sequence of operations carried out on the contents of a first computer register, a second sequence of operations carried out on the contents of a second computer register, and a third sequence of operations carried out on the contents of a third computer register, where the first register is optionally part of an EDC processor and the second and third registers each hold an eight-bit array and are optionally part of an ECC processor. In this characterization, three registers (each 16-bit), and three memory arrays of size max(M,N) are needed to implement the invention, and each data element is read in only once for processing for EDC purposes and for ECC-P-parity purposes.

[0114] Because of constraints in processing the data elements s(n1,n2)=s(n1+N·n2), the data elements are preferably read in consecutively once in the format s(00), s(01), s(02), . . . s(R−1) and processed immediately. FIGS. 5, 6, 7 and 8 illustrate suitable apparatus for processing the data elements s(k) (k=0000, 0001, . . . , R−1) to determine the ECC P-parity, P-parity, Q-parity and Q-parity checkbytes, respectively, according to a first embodiment.

[0115] FIG. 5 illustrates apparatus suitable for calculating the P-parity coefficients s0[n1] according to the first embodiment. A stream of data element values s(k) (k=0, 1, . . . , R−1) is received (normally in serial order) at a multiplexer 51. The MUX 51 selectively feeds each presently received data element value s(k) to one of the sum modules SUM1-p (p=0, 1, . . . , N−1) with p=k(mod N). Each sum module SUM1-p forms a sum of the received data element value s(k) and the contents of that sum module before the data element value was received. Each sum module SUM1-p is initialized by an initializer 53 to have content “0” before the computations begin. The MUX 51 receives the data element value s(k), is provided with the index “k” for this value, and feeds the data element value s(k) to the sum module SUM1-p (p=0, 1, . . . , N−1), which forms a sum of this received value with the content of this sum module and replaces the content by this new sum.

[0116] When the MUX 51 senses that R=M·N data element values s(k) have been received and that each has been fed to, and summed with the contents of, one of the sum modules SUM1-p, the MUX 51 causes a readout signal to be sent to each of the sum modules SUM1-p. Receipt of this readout signal causes each sum module SUM1-p to deposit its present content into a register or buffer unit BU1-p (p=0, 1, . . . , N−1) in a first register 57. The content of the buffer unit BU1-p represents the P-parity coefficient s0[n1=p].

[0117] FIG. 6A illustrates apparatus suitable for calculating the P-parity coefficients s1[n1] according to the first embodiment. A stream of data element values s(k) (k=0, 1, . . . , R−1) is received (normally in serial order) at a multiplexer 61. The MUX 61 selectively feeds the data value s(k) and the index value k to one of the sum modules, SUM2-p or 63, with p=k(mod N−1). Each sum module SUM2-p forms a sum of the received value s(k) plus α times the contents S1 of that sum module before the data element value s(k) was received, using a bank of α-multiplier modules 64; the sum is now s(k)+α·S1. Each sum module SUM2-p is initialized by an initializer 65 to have content “0” before the computations begin.

[0118] When the MUX 61 senses that R=M·N data element values s(k) have been received and that each data value s(k) has been fed to, and summed with the contents of, one of the α-weighted sum modules SUM2-p, the MUX 61 causes a readout signal to be sent to each of the sum modules SUM2-p. Receipt of this readout signal causes each sum module SUM2-p to deposit its present content into a register or buffer unit BU2-p (p=0, 1, . . . , N−1) in a second buffer 67. The content of the register unit BU2-p represents the P-parity coefficient s1[n1=p].

[0119] FIG. 6B illustrates alternative apparatus suitable for calculating the P-parity coefficients s1[n1] according to the first embodiment. A stream of data element values s(k) (k=0, 1, . . . , R−1) is received (normally in serial order) at an α-weighted multiplexer 61′. The α-MUX 61′ multiplies each data element value by an α-power, namely α^(M−1-[k/N]int), and selectively feeds the resulting product α^(M−1-[k/N]int)·s(k) to one of the sum modules, SUM2-p or 63′, with p=k(mod N−1). Here, [w] is the “floor function” or integer part of the real number w. Each sum module SUM2-p forms a sum of the received product α^(M−1-[k/N]int)·s(k) and the contents of that sum module before the data element value was received. Each sum module SUM2-p is initialized by an initializer 65′ to have content “0” before the computations begin. The α-MUX 61′ receives the data element value s(k), is provided with the index “k” for this value, and feeds the product α^(M−1-[k/N]int)·s(k) to the sum module SUM2-p (p=k(mod N−1)=0, 1, . . . , N−1), which forms a sum of this received value with the content of this sum module and replaces the content by this new sum.

[0120] When the α-MUX 61′ senses that R=M·N data element values s(k) have been received and that each product α^(M−1-[k/N]int)·s(k) has been fed to, and summed with the contents of, one of the sum modules SUM2-p, the α-MUX 61′ causes a readout signal to be sent to each of the sum modules SUM2-p. Receipt of this readout signal causes each sum module SUM2-p to deposit its present content into a register or buffer unit BU2-p (p=0, 1, . . . , N−1) in a second buffer 67′. The content of the register unit BU2-p represents the P-parity coefficient s1[n1=p].

[0121] FIG. 7 illustrates apparatus suitable for calculating the Q-parity coefficients s0′[n2] according to the first embodiment. A stream of data element values s(k) (k=0, 1, . . . , R−1), augmented by the values s(k) (k=R, . . . , R2−1) computed in the P-parity calculations, is received (normally in serial order) at a multiplexer 71. The MUX 71 selectively feeds each presently received data element value s(k) to one of the sum modules SUM3-q (q=0, 1, . . . , M+1). Each sum module SUM3-q forms a sum of the received data element value s(k) and the contents of that sum module before the data element value was received. Each sum module SUM3-q is initialized by an initializer 73 to have content “0” before the computations begin. The MUX 71 receives the data element value s(k), is provided with the index “k” for this value, computes the row index q and column index p, and feeds the data element value s(k) to the correct sum module SUM3-q, which forms a sum of this received value with the content of this sum module and replaces the content by this new sum.

[0122] If the row index (q=0, 1, 2, . . . , 24, 25) and the column index (p=0, 1, 2, . . . , 42) are designated as

[0123] (row, column)=(q, p),  (18)

[0124] one can verify that the assembly of numbers in FIG. 3 are reproduced by the following prescription

[0125] p=k(mod 43) (=0, 1, . . . , 42)  (19A)

[0126] m={k/43]_int,  (20A)

[0127] q=(m·44−k) (mod 26) (=0, 1, . . . , 25).  (21A)

[0128] For a more generally prescribed M2×N block (M2×N=26×43 in FIGS. 3A, 3B, and 3C), the analogous prescription becomes

[0129] p=k(mod N),  (19B)

[0130] m=[k/N]_int,  (20B)

[0131] q=(m·N1−k) (mod M2).  (21B)

[0132] A second prescription for the (row,column) indices (q,p) uses a number theoretic result: for M and N relatively prime integers, each integer k in the range 0, 1, . . . , M2·N−1 is uniquely expressible as a modulo sum

[0133] k=((N+1)·p+N·q) (mod (·M2·N))  (22)

[0134] where p and q are non-negative integers satisfying the constraints 0≦p≦N−1 and 0≦q≦M+1. The (row,column) indices (q(k),p(k)) thus become the solutions of Eq. (22).

[0135] A third prescription for the (row,column) indices (q,p) uses a pair of functions, one complicated:

[0136] p=k(mod N),  (23)

[0137] q=f(k),  (24)

[0138] m=[k/N]_int,

[0139] $\begin{array}{cc}\begin{array}{c}f\left(k\right)=\mathrm{N1}·m-k\\ \left(N·m\le k\le \mathrm{N1}·m;m=0,1,2,\dots ,M+1\right)\\ ={\left(\mathrm{N1}·m-k\right)}_{\mathrm{mod}\mathrm{M2}}\\ \left(\mathrm{N1}·m+1\le k\le \mathrm{N1}·m+\mathrm{M2};m=0,1,\dots ,M+1\right)\\ ={\left(\mathrm{N1}·m-k\right)}_{\mathrm{mod}\mathrm{M2}}\\ (\mathrm{N1}·m+\mathrm{M2}+1\le k\le \mathrm{N1}·m+N-1-m;\\ m=0,1,\dots ,N-M-4)\\ ={\left(\mathrm{N1}·m-k\right)}_{\mathrm{mod}\mathrm{M2}}\\ (m·\mathrm{N1}+1\le k\le N·m+N-1;\\ m=N-M-3,\dots ,M+1).\end{array}& \left(25\right)\end{array}$

[0140] Any of these three prescriptions for (row,column) indices can be used together with the apparatus shown in FIGS. 7 and 8 to determine the Q-parity coefficients s0′[n1] and s1′[n1]. The alpha-exponent for the primitive α used to determine the coefficient s1′[n1], for a given data index k, is

[0141] α^N−p−1,

[0142] for any of the three (row.column) indices prescriptions.

[0143] When the MUX 71 senses that all R2=(M+2)−N data element values s(k) have been received and that each has been fed to, and summed with the contents of, one of the sum modules SUM3-q, the MUX 71 causes a readout signal to be sent to each of the sum modules SUM3-q. Receipt of this readout signal causes each sum module SUM3-q to deposit its present content into a register or buffer unit BU3-q (q=0, 1, . . . , M+1) in a third register 77. The content of the buffer unit BU3-q represents the Q-parity coefficient s0′[n2=q].

[0144] FIG. 8 illustrates apparatus suitable for calculating the Q-parity coefficients s1′[n1] according to the first embodiment. Each sum module SUM4-q (q=0, 1, 2, . . . , M+1) in the assembly 83 is initialized by an initializer 85 to have content “0” before the computations begin. A stream of data element values s(k) (k=0, 1, . . . , R−1), augmented by the values s(k) (k=R, . . . , R2−1) computed in the P-parity calculations, and the corresponding index numbers “k” are received (normally in serial order) at a multiplexer 80. The multiplexer 80 directs the data element s(k) to an α-weighted multiplier MULT4-g(k), where

[0145] g(k)=N−1-{k(mod N)}=(N−1-k) (mod N).  (26)

[0146] is the column index p in an assembly 81 of such multipliers. The prescription set forth in Eq. (26) is equivalent to rotation of each the column n2=m in FIGS. 3A and 3B backward (from top to bottom) by m places (m=0, 1, . . . , M+1) before the Q-parity syndrome components s1′[n2] are calculated, because of application of the modulo N to the α-exponent.

[0147] The multiplier MULT4-g(k) receives the data element s(k) and multiplies this data element by α^g(k), as indicated in FIG. 8. The α-weighted data element s(k)·α^g(k)is then received by a rotate module 82 that directs this α-weighted data element to a sum element SUM4-h in an assembly 83 of sum elements. The sum element SUM4-h receives this α-weighted data element and adds this element to the sum of α-weighted data elements already received by this sum element. The initial value placed in the sum element SUM4-h by the initializer 85 is 0. The rotate module 82 directs the α-weighted data element s(k)·α^g(k)to the sum element SUM4-q where q is the row index as determined in the preceding discussion.

[0148] When the rotate module 82 senses that R2=(M+2)·N data element values s(k) have been received and that each product s(k)·α^g(k)has been fed to, and summed with the contents of, one of the sum modules SUM4-q, the rotate module 82 causes a readout of each of the sum modules SUM4-q into a register or buffer unit in a register assembly 87. The content of the register assembly 87 represents the Q-parity coefficient s1′[n2=q] (q=0, 1, . . . , M+1).

[0149] FIGS. 9, 10, 11 and 12 illustrate suitable apparatus for processing the data elements s(k) (k=0000, 0001, . . . , R−1) to determine the ECC P-parity, P-parity, Q-parity and Q-parity checkbytes, respectively, according to a second embodiment.

[0150] In FIG. 9, the data element values arrive in consecutive order at a first input terminal of a sum module 91, and a sum is formed of the new data element value and a value received, at a second input terminal of the sum module 91, from an N-unit feed-back shift register unit 95 that has feed-back capability. A shift register initializer 95 optionally initializes the contents of the shift register units in 93 so that each of the first N data elements to arrive at the sum module 91 is summed with a feedback value (initial) of 0. Each of the value sums formed by the sum module 91 is received by shift register unit SR1-0 and is then moved rightwards to the next buffer unit (SR1-0→SR1-1→SR1-2→ . . . →SR1-(N−1)) upon receipt of the next clock pulse (CLK), which also drives the sum module 91, the feed-back shift register unit 95 and an N-unit first buffer 97 (optional). After N consecutive data elements have been read in, the first of these data element values, s(k=0), (or, more generally, a feedback sum FBS1(k)) is received from the feed-back shift register unit SR1-(N−1) by the sum module 91 and is summed with the data element value, s(k) (k=N, N+1, . . . ) that is presently received at the first input terminal of the sum module 91. This sum is then received by the feedback shift register 93 at the next clock pulse, as before. This summation, shift and feedback process continues until all R data elements values s(k) (k=0, 1, . . . , R−1) have been received at the sum module 91.

[0151] At least one of the sum module 91 and the first feedback shift register 93 is programmed to track the number K of data elements received and processed thus far. If 0≦K<R, the first feed-back shift register unit 95 continues to shift the data element value sum FBS1(k) from the shift register unit SR1-(N−1) to the second input terminal of the sum module 91, where this data element value (sum) is added to the incoming data element value; and the new sum is again shifted into the shift register unit SR1-0 of the first feedback shift register 93. The sums FBS1(k) that accumulate in the shift register units SR1-m (m=0, 1, . . . , N−1) are the partial sums of the column entries corresponding to n1=N−1-m in FIG. 2.

[0152] When the count index K reaches K=R−1 for the first feedback shift register 93, the data element value sums in the first shift register units SR1-m (m=0, 1, . . . , N−1) now represent the components s0[n1] of the P-parity first syndrome s0, arranged in reverse order (n1=N−1-m). At this point, the first feedback shift register 95 no longer shifts the data element value sums to the sum module 91. Instead, the shift register 93 optionally (1) temporarily holds the contents of the N first shift register units SR1-m, without further feed-back or shift-forward, or (2) shifts these data element value sums s0[n1] into an N-unit first buffer 97, in consecutive order or (optionally) in reverse order.

[0153] In FIG. 10, the data element values s(k) are received by an α-weighted sum module 101. A shift register initializer 107 optionally initializes the contents of the shift register units in a second feedback shift register 103 so that each of the first N data elements to arrive at the α-weighted sum module 101 is summed with a feedback value (initial) of 0. The data element values arrive in consecutive order at a first input terminal of the α-weighted sum module 101. The α-weighted sum module 101 forms sums of the data element value s(k), received at the first input terminal, and a term α·FBS2(k), where FBS2(k) is the value (initially zero) presently received at the second input terminal of the α-weighted sum module 101. With the data element index k=n1+N·n2, the α-weighted sum module 101 thus forms a sum of terms

[0154] s(k)+α·FBS2(k)=s(n1+N·n2)+α¹·s(n1+N·(n2−1))+α²·s(n1+N·(n2−2))+ . . . +α⁴³⁻¹·s(n1+N·(n2−(N−1))),  (27)

[0155] weighted by powers of the 8-bit array α, where the sum on the right is discontinued when the first argument n1+N·(n2−p) becomes negative. Each of the value sums, s(k)+α·FBS2(k), formed by the α-weighted sum module 101 is received by shift register unit SR2-0 and is then moved rightwards to the next buffer unit (SR2-0→SR2-1→SR2-2→ . . . →SR2-(N−1) ) upon receipt of the next clock pulse (CLK), which also drives the α-weighted sum module 101, the second feed-back shift register unit 103 and an N-unit second buffer 107 (optional). After N consecutive data elements have been read in, the first of these data element values, s(k=0), is received from the feed-back shift register unit SR2-(N−1) by the a-weighted sum module 101, is multiplied by α, and is summed with the data element value, s(k=N), that is presently received at the first input terminal of the α-weighted sum module 101. This weighted sum is then received by the feedback shift register 103 at the next clock pulse, as before. This weighted sum, shift and feedback process continues until all R data elements values s(k) (k=0, 1, . . . , R−1) have been received at the α-weighted sum module 101.

[0156] At least one of the α-weighted sum module 101 and the second feedback shift register 103 is programmed to track the number K of data elements received and processed thus far. If 0≦K<R, the second feed-back shift register unit 103 continues to shift the data element value (sum) from the shift register unit SR1-(N−1) to the second input terminal of the α-weighted sum module 101, where this data element value (sum) is multiplied by α and the resulting product is added to the incoming data element value; and the new weighted sum is again shifted into the shift register unit SR2-0 of the second feedback shift register 103. The sums that accumulate in the shift register units SR2-m (m=0, 1, . . . , N−1) are the partial sums of the α-weighted column entries corresponding to n1=N−1-m in FIG. 2.

[0157] When the count index k reaches k=R−1 for the second feedback shift register 103, the data element value sums in the second shift register units SR-m (m=0, 1, . . . , N−1) now represent the components s1[n1] of the second syndrome, arranged in reverse order (n1=N−1-m). At this point, the second feedback shift register 103 no longer shifts the data element value sums to the weighted sum module 101. Instead, the shift register unit 103 optionally (1) temporarily holds the contents of the N second shift register units SR2-m, without further feed-back or shift-forward, or (2) shifts these data element value sums s1[n1] into an N-unit second buffer 107 (optional), in consecutive order or (optionally) in reverse order. The contents of the first buffer 97 and of the second buffer 107 are transferred, as 2N additions to the stream of data element values s(k) (k=0, 1, . . . , R−1), to a sum module 111 (FIG. 11) and an α-weighted sum/permutation module 121 (FIG. 12), respectively. The contents of the first buffer 97 and second buffer 107 are also transferred to a syndrome processing module 80 that will compute the checkbyte components c0[n1] and c1[n1].

[0158] In the preceding discussion of FIGS. 9 and 10, the respective general numbers M, M+2, N−1, N, 2·N, M·N−1 and (M+2)·N−1 may be replaced by particular choices, such as the respective numbers 24, 26, 42, 43, 86, 1031 and 1117.

[0159] FIGS. 11 and 12 illustrate a second embodiment of apparatus for processing the data elements s(k) (k=0000, 0001, . . . , R−1, R, . . . , R2−1), including the supplemental or augmented data element values s(k) corresponding to k=R, R+1, . . . , R2−1, for ECC Q-parity. The operation of the system in FIG. 11, which provides the components s0′[n2] of the first syndrome s0′ for Q-parity, is similar, in part, to operation of the apparatus shown in FIG. 9, with the following difference: the N-unit first feedback shift register 93 in FIG. 9 is replaced by an (M+2)-unit third feedback shift register 113 that feeds the contents FBS3(k) of this last shift register unit SR3-(M+1) to the second input terminal of a sum-module 111.

[0160] Similarly, the operation of the system in FIG. 12, which provides the components s1′[n2] of the first syndrome s1′ for Q-parity, is similar, in part, to operation of the apparatus shown in FIG. 10, with the following difference: the N-unit first feedback shift register 103 in FIG. 10 is replaced by an (M+2)-unit third feedback shift register 123 that feeds the contents FBS4(k) of this last shift register unit SR4-(M+1) to the second input terminal of a sum module 121. The sum modules, 111 and 121, and the third and fourth feedback shift registers, 113 and 123, are arranged to operate according to the following requirements.

[0161] The data elements s(k) (k=0, 1, . . . , R−1) are received and processed at the first input terminal of the sum module 111. The sum module 113 also receives feedback from the register unit SR3-(M+1) at a second input terminal, in the same manner as the second input terminal of the sum module 111 receives feedback from the register unit SR3-(M+1) in FIG. 5. When the count index k reaches K=R−1, the data element values s(k) with k=R, R+1, . . . , R2−1 (stored in the buffers 117 and 127) are added to the stream of data elements received at the first input terminal of the sum module 111. When the count index K reaches K=R2−1, the data element value sums in the third shift register units SR3-m (m=0, 1, . . . , M+1) now represent the components of the first Q-parity syndrome s0′[n2], arranged in reverse order. At this point, the third feedback shift register 115 no longer shifts the data element sums to the sum module 111. Instead, the third feedback shift register unit 115 optionally (1) temporarily holds the contents of its M+2 units, without further feed-back or shift-forward, or (2) shifts these data element value sums s0′[n2] into an (M+2)-unit third buffer 117 (optional), in consecutive order or (optionally) in reverse order.

[0162] Computation of the components of the second Q-parity syndrome s1′[n2] are more complex, because of the combined presence of the factors α^N−1-n1and s((N+1)·n1+N·n2)_R2in the expressions for s1′[n2] in the relation (9). The data element stream s(k) (k=0, 1, . . . , R−1) is received at a first input terminal of an α-weighted sum module 121, which receives a feedback value, FBS4(k), at a second input terminal. The α-weighted sum module 121 determines an integer solution pair (n1(k),n2(k)) for the relation

[0163] k=((N+1)·n1+N·n2)_R2=((N+1)·n1+N·n2) (mod R2),  (28)

[0164] with 0≦n1(k)≦N−1 and 0≦n2(k)≦M+1, forms an α-weighted sum α^M−1-n1·s(k)+FBS4(k), and passes this weighted sum to an (M+2)-unit fourth feedback shift register 123. The fourth feedback shift register 123 is optionally initialized by a fourth initializer 125, which initially places a zero value in each of the M+2 shift register units SR4-m (m=0, 1, . . . , M+1). Thus, the first M+2 feedback values FBS4(k) (k=0, 1, . . . , M+1) are 0.

[0165] A data element s(k) and its associated index k are provided at the α-weighted sum-module 121, and the relation (28) is to be solved for an integer solution pair (n1(k),n2(k)). As noted in connection with the discussion of the argument in the relation (9), the relation (28) has a unique solution pair (n1,n2) with 0≦n1≦N and 0≦n2≦M+1. The solution pair (n1(k),n2(k)) for the relation (28) can be solved explicitly, using well known number theoretic methods, or the solution pair (n1(k),n2(k)) can be provided by table look-up. Once the solution pair (n1(k),n2(k)) is known for the index k and for the data element s(k), the weight α^M−1-n1can be provided and multiplied by the element s(k), from the relations (19A)-(25), to form the weighted data element

[0166] α^M−1-n1·s((N+1)·n1+N·n2)_R2,

[0167] which is then passed to the fourth feedback shift register 123 for appropriate feedback.

[0168] After the augmented data element stream with all R2 data element values has been received, and a-weighted sums have been formed by the α-weighted sum module 121 and passed to the fourth feedback shift register 123, the feedback path is disabled, the M+2 sum register units SR4-m (m=0, 1, . . . , M+1) hold the components of the second Q-parity syndrome s1′[n2], arranged in reverse order. The fourth feedback shift register 123 optionally (1) temporarily holds the contents of its M+2 units, without further feed-back or shift-forward, or (2) shifts these data element sums s1′[n2] into an (M+2)-unit fourth buffer 127 (optional).

[0169] The P-parity calculations of the syndrome components s0[n1] and s1[n1] (n1=0, 1, . . . , N−1) are computed as in the discussion of FIGS. 4 and 5, using the relations (4) and (5) and only the original coefficients s(k) (k=0, 1, . . . , R−1), with R=M·N=1032 in the example. The P-parity components are computed using the preceding formalism (e.g., as in FIGS. 9 and 10) and do not require any changes in the approach of the first embodiment.

[0170] The Q-parity syndrome components s0′[n2] and s1′[n2] (n2=0, 1, . . . , M+1) are computed in this second embodiment as in the relations (8) and (9), including the original coefficients s(k) (k=0, 1, . . . , R−1) and the P-parity checkbyte components c0[n1] and c1[n1], which are again re-designated as new coefficients s(R+n1) and s(R+N+n1), respectively, for convenient reference.

[0171] The four feedback shift registers, 93, 103, 113 and 123, or, alternatively, the four buffers, 97, 107, 117 and 127, now hold the respective components s0[n1], s1[n1], s0′[n2] and s1′[n2], in reverse order or (optionally) in forward order. The components s0[n1] and s1[n1] are read out and received by the syndrome processing module 130, shown in FIG. 13, to compute the P-parity code words c0[n1] and c1[n1], as indicated in the relations (6) and (7).

[0172] Sub-systems from the first and second embodiments can be mixed, if desired. For example, the sub-systems containing the MUX 51, α-weighted MUX 61, and sum modules SUM1-p and SUM2-p of the first embodiment can be exchanged with the sub-systems containing the sum module 91, α-weighted sum module 101 and shift registers 93 and 103; and/or the sub-systems containing the MUX 71, α-weighted MUX 81, and sum modules SUM3-p and SUM4-p of the first embodiment can be exchanged with the sub-systems containing the sum module 111, α-weighted sum module 121 and shift registers 113 and 123.

[0173] For computation of the P-parity code words, the components s0[n1] and s1[n1] are received at first and second input terminals of the syndrome processing module 80, weighted sums α²³⁰·s0[n1]+α²³²·s1[n1] and α²³¹·s0[n1]+α²³²·s1[n1] are computed at first and second α-weighted sum modules, 131 and 133, respectively, and these α-weighted sums are held in memory units, 135 and 137, or are presented for immediate use at output terminals of the syndrome processing module 130.

[0174] The components s0′[n2] and s1′[n2] are read out and received by an syndrome processing module 140, analogous to 130 in FIG. 13, and the corresponding components 141, 143, 145 and 147, in FIG. 14 to form the Q-parity code words c0′[n2] and c1′[n2], which are computed according to the relations

[0175] c0′[n2]=α²³⁰·s0′[n2]+α²³²·s1′[n2] (n2=0, 1, . . . , M+1),  (29)

[0176] c1′[n2]=α²³¹·s0′[n2]+α²³²·s1′[n2].  (30)

[0177] Alternatively, the same syndrome processing module 130 (FIG. 13) can be used to compute the P-parity code words, c0[n1] and c1[n1], and the Q-parity code words, c0′[n2] and c1′[n2].

[0178] FIGS. 15A and 15B are a flow chart of a procedure, generalized to selected positive integers M and N, for simultaneously generating the EDC code word(s), the ECC-P code words and the ECC-Q code words for error control. The integers N and N+1 are relatively prime to each other. In step 151 (optional), each of the variables n1 and n2 is initialized to 0, and the contents of first, second, third and fourth feedback registers (with respective sizes N, N, M+1 and M+1) are initialized. Selected powers α^p(p=0, 1, . . . , max(N−1,M+1) and others) are provided or computed.

[0179] In step 152, a stream of data element values s(k) (k=0, 1, . . . , R−1) is received seriatim (in forward order or backward order) at a first input terminal of each of an EDC processor, an ECC-P processor and an ECC-Q processor. In step 153, one or more EDC error detection checkbytes is computed and stored for the stream of data element values.

[0180] In step 154, the ECC-P processor computes ECC-P parity syndrome components s0[n1], preferably using a sum module and (first) N-unit feedback shift register with feedback to the sum module, as discussed in connection with FIG. 5.

[0181] In step 155, the ECC-P processor computes ECC-P parity syndrome components s1[n1], preferably using an α-weighted sum module and (second) N-unit feedback shift register with feedback to the weighted sum module, as discussed in connection with FIG. 10.

[0182] In step 156, the stream of data element values s(k) (k=0, 1, . . . , R−1) at the ECC-Q processor is augmented using augmenting data element values s(M·N+k)=s0[k] and s((M+1)·N+k)=s1[k] for k=0, 1, . . . , N−1. In step 157, ECC-P parity checkbytes c0[n1] and c1[n1] (n1=0, 1, . . . , N−1) are computed by analogy with the relations (6) and (7).

[0183] In step 158, the ECC-Q processor computes ECC-Q parity syndrome components s0′[n2], preferably using a sum module and (third) (M+2)-unit feedback shift register with feedback to the sum module, as discussed in connection with FIG. 11.

[0184] In step 159, the ECC-Q processor computes ECC-Q parity syndrome components s1′[n2], preferably using an α-weighted sum module and (fourth) (M+2)-unit feedback shift register with feedback to the α-weighted sum module, as discussed in connection with FIG. 12.

[0185] In step 160, ECC-Q parity checkbytes c0′[n2] and c1′[n2] (n2=0, 1, . . . , M+1) are computed by analogy with the relations (13) and (14).

[0186] The groups of steps {152}, {153, 154, 155} and {156, 157, 158, 159} are, or may be, performed substantially simultaneously according to the invention.

[0187] Proceeding in this manner, the EDC, ECC-P and ECC-Q checkbytes can be generated in parallel by three data element value processors that work in parallel and simultaneously receive and process the stream of data element values s(k) (k=0, 1, . . . , R−1). Computation of the ECC-Q code words may need to be delayed in time, relative to computation of the ECC-P code words, because the ECC-P code word components s0[n1] and s1[n1] are computed and used to augment the stream of data element values for the ECC-Q processor. However, these augmenting data element values are needed only at the end of the data element value stream for the ECC-Q processor (step 156 in FIG. 15 so that the associated time delay is likely to be minimal or non-existent. In effect, the system provides triple duty simultaneous processing to compute the EDC, ECC-P and ECC-Q checkbytes.