US 6,594,792 B1Grant
Modular turbo decoder for expanded code word length
Issue Date:2003-07-15
•6 Claims
•5 Drawing Sheets
Abstract
A turbo decoder system utilizing a MAP decoding algorithm has a predetermined number of turbo decoder modules for decoding segments of a turbo code component code word in parallel, thereby expanding the block-length and data-rate capability of the turbo decoder system. Input data samples are provided to an interleaver/de-interleaver module wherein they are divided into segments of predetermined size, each segment being provided to a respective turbo decoder module. The outputs of each turbo decoder module are a posteriori probabilities which are re-ordered in the interleaver/de-interleaver module, segmented, and provided back to the turbo decoders as a priori information-bit probabilities. For the case of a turbo code comprising two component codes, the a posteriori information-bit probabilities are re-ordered according to the interleaver definition at the end of odd-numbered half iterations, while at the end of even-numbered half iterations, they are re-ordered according to the de-interleaver definition. Decoding continues until the desired number of iterations have been performed. Data decisions are made on the final a posteriori bit probability estimates.
Metadata
Assignee
- General Electric Company
Inventors
- Stephen Michael Hladik
- Abdallah Mahmoud Itani
- Nick Andrew Van Stralen
- Robert Gideon Wodnicki
- John Anderson Fergus Ross
Application Information
Application Number:US 09/561,333
Filing Date:2000-04-28
Priority Date:1999-04-30
Art Unit:7
Classifications
IPC:
H03M 1329H03M 1345
Field of Search:
714755714780714786714794
Patent Drawings (5 sheets)
Description
Cross Reference to Related Applications
[0002] This application claims the benefit of U.S. Provisional Application No. 60/132,027, filed Apr. 30, 1999.
Background of the Invention
[0003] The present invention relates generally to error-correction coding and, more particularly, to a decoder for parallel convolutional codes, i.e., turbo codes.
[0004] A new class of forward error control codes, referred to as turbo codes, offers significant coding gain for power limited communication channels. Turbo codes are generated using two or more recursive systematic encoders operating on different orderings of the same information bits. A subset of the code bits generated by each encoder is transmitted in order to maintain bandwidth efficiency. Turbo decoding involves an iterative algorithm in which probability estimates of the information bits that are calculated for one of the received component code words are fed back to a probability estimator comprising the decoder component code words for the other component code words. Each iteration of decoder processing generally increases the reliability of these probability estimates. This process continues, cyclically decoding the component code words until the probability estimates can be used to make reliable decisions.
[0005] The maximum a posteriori (MAP) type algorithm introduced by Bahl, Cocke, Jelinek, and Raviv in “Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate”, IEEE Transactions on Information Theory, March 1974, pp. 284-287, is particularly useful as a component decoder in decoding parallel concatenated convolutional codes, i.e., turbo codes. The MAP algorithm is used in the turbo decoder to generate a posteriori probability estimates of the information bits that have been encoded into the code word. These probability estimates are used as a priori bit probabilities for the second MAP decoder. Three fundamental terms in the MAP algorithm are the forward and backward state probability functions (the alpha and beta functions, respectively) and the a posteriori transition probabilities (the sigma functions).
[0006] A known characteristic of turbo codes is that their error correction capability increases with code word length. However, there is some practical limit on the length of a code word that can be decoded with a MAP-algorithm decoder implementation. Accordingly, it is desirable to provide a modular turbo decoder structure capable of decoding longer code word lengths. It is furthermore desirable to provide such a turbo decoder while increasing coding gain and data rate.
Brief Summary of the Invention
[0007] A turbo decoder system utilizing a MAP decoding algorithm comprises a predetermined number M of turbo decoder modules for decoding segments of a turbo code component code word in parallel, thereby expanding the block-length and data-rate capability of the turbo decoder system. In an exemplary system, each turbo decoder module has a predetermined maximum code-word size corresponding to N information bits, and a predetermined maximum decoding rate. Input data samples from a received code word, corresponding to M·N information bits, are provided to an interleaver/de-interleaver module wherein they are divided into segments of predetermined size, each segment being provided to a respective turbo decoder module. The output of each turbo decoder module comprises a posteriori probabilities which are re-ordered in the interleaver/de-interleaver module, segmented, and provided back to the turbo decoders as a priori information bit probabilities. For the case of a turbo code comprising two component codes, the a posteriori information-bit probabilities are re-ordered according to the interleaver definition at the end of odd-numbered half iterations, while at the end of even-numbered half iterations, they are re-ordered according to the de-interleaver definition. Decoding continues until the desired number of iterations have been performed. Then, data decisions are made on the final a posteriori bit probability estimates.
Brief Description of the Drawings
[0008] FIG. 1 is a block diagram illustrating a typical turbo decoder utilizing a MAP decoding algorithm;
[0009] FIG. 2 is a block diagram illustrating a top level view of data flow in a MAP component decoder such as that of FIG. 1;
[0010] FIG. 3 is a block diagram illustrating an exemplary embodiment of a turbo decoder system of the present invention;
[0011] FIG. 4 is a block diagram illustrating an exemplary interleaver/de-interleaver module definition useful in a system according to the present invention; and
[0012] FIG. 5 is a block diagram illustrating an alternative exemplary embodiment of a turbo decoder system of the present invention, in which the interleaver and de-interleaver have been implemented in the MAP turbo decoder module.
Detailed Description of the Invention
[0013] A turbo decoder is described herein with particular reference to a MAP decoding algorithm as a turbo decoding algorithm. However, other suitable turbo decoding algorithms may be employed using the principles of the present invention, such as, for example, a SOVA decoding algorithm.
[0014] A MAP decoder provides estimates of the a posteriori probabilities of the states and transitions of a Markov source through a discrete memory-less channel. The transition probabilities of a discrete memory-less channel depend on the transitions X1τ of the Markov source and the observations Y1τ such that for a sequence,
[0015] where R(·|·) defines the channel transition probabilities.
[0016] The MAP decoder uses the received sequence Y1τ to estimate the a posteriori state and transition probabilities of the Markov source.
[0017] where Stis the state of the source at time t.
[0018] The alpha, beta and gamma functions are defined as follows:
[0019] αt(m)=Pr{St=m;Y1t} 4
[0020] βt(m)=Pr{Yl+1τ|St=m} 5
[0021] and
[0022] γt(m′,m)=Pr{St=m;Yt|St−1=m′} 6
[0023] so that
[0024] λt(m)=αt(m)·βt(m) 7
[0025] and
[0026] σt(m′,n)=αt−1(m′)·γt(m′,m)·βt(m) 8
[0027] The alpha function can be computed from the following recursion:
[0028] The beta function can be calculated using the following recursion:
[0029] Finally, the gamma function can be calculated as follows:
[0030] where pt(m|m′) are the transition probabilities of the Markov source, and qt(X|m′,m) is the distribution of the source's output symbols conditioned on the source's state transitions.
[0031] By way of illustration, the most common case of a turbo code comprising two component codes is described herein, but it is to be understood that the invention described herein applies generally to other turbo codes. For the exemplary case, turbo codes are constructed as two recursive systematic codes concatenated in parallel. A MAP decoder for a turbo code generates a probability estimate of the information bits in a component code word, based on one of the two recursive systematic codes comprising the turbo code, and provides these probability estimates to a second MAP decoder which decodes the other component code word of the turbo code word. The second decoder uses these probabilities as a priori information and generates new probability estimates of the information bits encoded in the code word. The updated estimates are provided to the first MAP component decoder, which, in turn, generates updated estimates. This feedback process continues a finite number of times, and a decision on the information bits is made based on the final probability estimates. Each operation of a component MAP decoder is referred to as a half iteration.
[0032] The two parallel component codes in a turbo code are referred to herein as the top code and the bottom code. Normally, the data is encoded by the top code and is interleaved using either a fixed-block interleaver or a random interleaver before being encoded by the bottom code.
[0033] FIG. 1 illustrates a turbo decoder 10 employing component MAP decoders 12 and 14. The inputs to the turbo decoder of FIG. 1 are elements of the composite turbo code word. The systematic data is a sequence of symbols that correspond to the information bits; the top-code parity data are symbols that correspond to the parity bits generated by the top component encoder; and the bottom code parity data are symbols that correspond to the parity bits generated by the bottom component encoder of the turbo encoder. As shown, the top code parity data is provided along with the systematic data to a top code memory 16 and then to MAP decoder 12. The systematic data is also provided, via an interleaver 18, along with the bottom code parity data to a bottom code memory 20 and then to the second MAP decoder 14. FIG. 1 also shows the feedback loop involving MAP decoders 12 and 14, interleaver 18, de-interleaver 22, a probability estimate memory 24, and an address generator 19 for implementing a MAP decoding algorithm as described hereinabove.
[0034] The systematic (i.e., information) bit probability estimates are computed using the a posteriori transition or σt(m′,m) probabilities. The sum of all a posteriori state transition probabilities resulting from the same information bit value is the a posteriori probability bit estimate. The output of a MAP component decoder is an a posteriori probability estimate of the information bits, denoted as APPt(0) and APPt(1), as set forth in the following expression:
[0035] where the summation is over all σt(m′,m) values where the information bit corresponding to the state transition (m′,m) is k.
[0036] The calculated a posteriori systematic bit probabilities are stored in memory as likelihood ratios, that is, APPt(1)/APPt(0).
[0037] Although the description herein is given with respect to non-logarithmic functions, it is to be understood that a logarithmic implementation is preferred for many applications. To this end, the mathematical expressions herein may be converted to logarithmic expressions in known fashion.
[0038] FIG. 2 is a top level view illustrating an exemplary turbo decoder data flow structure. The functional blocks within the turbo decoder in the data path are the gamma calculator block 40, the alpha calculator block 42, the beta calculator block 44, and the sigma calculator blocks 50. Received symbols IPDATA and the a posteriori bit probability estimates from the sigma blocks are provided as inputs to the gamma block. Four gamma values are outputted from the gamma block, one gamma value being provided to each of the alpha and beta blocks (GAMA and GAMB, respectively); and the other gamma values (GAMSR and GAMSL) being provided via multiplexers 52 to the sigma blocks along with the present alpha and beta values (ASR, BSL) and the alpha and beta values stored in memory (A-MEM and B-MEM).
[0039] As illustrated, four sigma blocks 50 calculate the sigma values for the state transitions in the code's trellis. These blocks also compute an update of the a posteriori probability associated with each of the information (systematic) bits in the code word. The probability of the transmitted bit being zero (APOR, APOL) is computed simultaneously with the probability of the bit being one (APIR, APIL). Since symbol-by-symbol MAP decoding involves both forward (from the beginning to the end of the received component code word) and backward (from the end to the beginning of the received component code word) recursive calculations, as described in U.S. patent application Ser. No. 09/137,260, filed Aug. 20, 1998, the turbo decoder processes the received symbols comprising the received component code words of the received turbo code word sequentially from the first received to the last received for the forward recursion and from the last received symbol to first for the backward recursion substantially simultaneously. These operations are performed in parallel in order to minimize the delay which would otherwise result from serial sigma block calculations.
[0040] FIG. 3 illustrates data flow through a turbo decoding system 80 employing multiple (e.g., four) turbo decoder modules, or chips, 82 for decoding a code word which exceeds the maximum length each respective chip is capable of decoding. System 80 is illustrated as comprising an interleaver/de-interleaver module 84 which receives data comprising turbo code words from an analog-to-digital (A/D) converter (not shown). Each turbo code word comprises information bits and parity bits. Interleaver/de-interleaver module 84 divides the received turbo code words into multiple segments, each respective segment being provided to a respective decoder chip 82. For the first half iteration of the turbo decoder MAP decoding algorithm, the inputted segments respectively correspond to those required to decode the top component code word. The turbo decoding of the code word segments for the first half iteration is performed simultaneously by the multiple turbo decoder chips. That is, the respective segments of the same turbo code word are decoded in parallel by the multiple chips. Upon completion of the first half iteration of decoding, a posteriori bit probability signals (APP's) are provided to the interleaver/de-interleaver module wherein they are re-ordered according to the interleaver definition therein. The interleaver (and de-interleaver) length corresponds to the total length of the received composite turbo code word, i.e., before segmenting.
[0041] Advantageously, the interleaving/de-interleaving function adds only minimal delay. That is, the a posteriori bit probability values are provided from the multiple turbo decoder chips simultaneously, these probability values being routed and inputted via the interleaver definition block to the respective turbo decoder chip for the next half iteration. This signal path provides only minimal delay (e.g., a few cycles of master clock delay) between receiving the a posteriori bit probability values and loading them as a priori probability values for the next iteration.
[0042] At or before the start of the second half iteration, data samples corresponding to bottom component code word are provided as inputs to the respective turbo decoder chips. Again the component code word is divided into multiple segments, with a respective turbo decoder operating on a different section of the code word. At the end of the second half iteration, the a posteriori bit probability outputs of the individual decoders are again passed through the interleaver/de-interleaver function block wherein they are again re-ordered, albeit this time with the de-interleaver definition. After de-interleaving, these values are associated with the corresponding elements of each segment of the top component code (in like manner as the first half iteration) and provided to the respective decoders for the third half iteration. In an exemplary embodiment, the same turbo decoder chips are used to decode the same segments as in the first iteration such that the data samples needed for the third half iteration have already been provided to the decoders and may be retained in memory.
[0043] Upon completion of any half iteration, the a posteriori bit probability estimates are provided as inputs to the interleaver/de-interleaver function block wherein they are re-ordered, segmented, and provided back into the decoders as a priori bit probabilities. At the end of odd-numbered half iterations, the a posteriori bit probabilities are re-ordered according to the interleaver definition, while at the end of even-numbered half iterations, they are re-ordered according to the de-interleaver definition. Decoding continues until the desired number of half iterations have been performed. Decoding decisions are typically made based on the final a posteriori probability estimates.
[0044] Each respective decoder chip is preferably used for decoding the corresponding segments of each code word, or frame, each time an odd or even numbered half iteration is performed. In this way, memory internal to the decoder can be used to store the required samples for the segments, and the data samples do not have to be entered into the decoders multiple times. It should also be noted that the a priori bit probabilities do not have to be entered into the decoders before the first iteration because at the start of the first half iteration, if the bit=0 hypothesis and the bit=1 hypothesis are assumed to be equally likely, and hence can be generated internally to the decoder.
[0045] The only data samples required to be inputted to each respective decoder chip are those for the segment of the code word being decoded by a specific decoder. As an example, an exemplary turbo decoder is capable of decoding a code word having 1024 information bits. A turbo decoder system such as that of FIG. 3 can be used to decode turbo code word generated by a block of 4096 information bits by using four of such 1024-bit chips, each respective turbo decoder chip having 1024 data samples (plus parity, merge and tail bits) entered for the top and bottom component of each chip. In addition, there is a decoding data rate advantage provided by this embodiment of the invention. That is, the decoding time for the frame would be similar or identical to the time elapsed if a single chip were to decode a 1024 block length code because the overhead associated with the interleave/de-interleave function is minimal. For the example herein, i.e., for a block length of 4096 bits, the four chips decode at four times the data rate as a single chip. Thus, there is a quadrupling of the data rate by using the four chips.
[0046] As an alternative embodiment, turbo decoder modules 82 may employ a common input bus for both the data samples and the a priori bit probability values. This is illustrated in FIG. 3 in phantom as bus 88 replacing the two illustrated input buses. The data samples needed to decode the segments for both the top and bottom component codes are provided to the decoder prior to the start of the first half iteration. The common input bus can be used exclusively for inputting data samples at this time because the a priori bit probability estimates for the first iteration can be easily generated internally to the individual chips. After the first iteration, the common input bus is used exclusively for input a priori bit probabilities obtained from the a posteriori bit probabilities that are fed back as a result of the previous decoding iteration. This is possible because the data samples needed for all iterations (odd and even numbered) can be stored internally in double buffers. (Such double buffers may be loaded with non-interleaved and interleaved data at the start of each new code word, resulting in reduced input/output processing delays.) The common input bus 88 must be at least as wide (i.e., with respect to the number of bits of precision) as the larger of the A/D data or the input a priori bit probabilities. In an exemplary turbo decoder having 6-bit input data samples and 9-bit a priori bit probabilities, a shared bus would have at least 9 bits.
[0047] FIG. 4 illustrates an interleaver's function useful for the turbo decoder structure described herein. Note that all the integrated circuits operate simultaneously, giving N times the throughput when N decoder chips are used.
[0048] Another alternative embodiment, illustrated in FIG. 5, is constructed such that the interleaving function performed between half-iterations is distributed among multiple decoder 92. With multi-chip interleaving capability built into each respective turbo decoder, the interleaving/de-interleaving block (FIG. 3) can be eliminated. In such case, all of the a posteriori bit probability estimates would be provided to all decoders. By way of example, FIG. 5 shows three input a priori bit probability buses 94 for each turbo decoder. Only three input buses are required to support concatenation of four chips since the output a posteriori probabilities can be stored in internal memory in addition to being provided as outputs of the chips. The data samples from the A/D converter (not shown) are provided to all four chips 92. However, only the data samples corresponding to the segment that each respective turbo decoder chip is designated to decode are stored in internal memory of the respective chip.
[0049] While the preferred embodiments of the present invention have been shown and described herein, it will be obvious that such embodiments are provided by way of example only. Numerous variations, changes and substitutions will occur to those of skill in the art without departing from the invention herein. Accordingly, it is intended that the invention be limited only by the spirit and scope of the appended claims.
Claims
What is claimed is:
1. A turbo decoder system, comprising:
a plurality M of turbo decoder modules, each for decoding a maximum code-word size corresponding to N information bits according to a turbo decoding algorithm;
interleaver/de-interleaver circuitry for receiving input data samples corresponding to (M·N) information bits and for receiving a priori bit probabilities, the interleaver/de-interleaver circuitry having predetermined interleaver and de-interleaver definitions, the interleaver/de-interleaver circuitry segmenting the input data samples into M segments, each segment being provided to a respective turbo decoder module which provides as output a posteriori bit probabilities based on the corresponding segment of input data samples, the interleaver/de-interleaver circuitry re-ordering the a posteriori bit probabilities according to the interleaver definition upon the end of odd-numbered half iterations and according to the de-interleaver definition upon the end of even-numbered half iterations.
2. The turbo decoder system of claim 1 wherein each respective turbo decoder module comprises a common input bus for the input data samples and the a priori bit probability values.
3. The turbo decoder system of claim 1 wherein the turbo decoding algorithm comprises a MAP decoding algorithm.
4. A turbo decoder system, comprising:
a plurality M of turbo decoder modules, each for decoding a maximum code-word size corresponding N information bits according to a turbo decoding algorithm, each turbo decoder module comprising a double buffer structure for storing non-interleaved and interleaved data samples at the start of each input data sample corresponding to a turbo code word;
interleaver/de-interleaver circuitry for receiving input data samples corresponding to (M·N) information bits and for receiving a priori bit probabilities, the interleaver/de-interleaver circuitry having predetermined interleaver and de-interleaver definitions, the interleaver/de-interleaver circuitry segmenting the input data samples into M segments, each segment being provided to a respective turbo decoder module which provides as output a posteriori bit probabilities based on the corresponding segment of input data samples, the interleaver/de-interleaver circuitry re-ordering the a posteriori bit probabilities according to the interleaver definition upon the end of odd-numbered half iterations and according to the de-interleaver definition upon the end of even-numbered half iterations.
5. The turbo decoder system of claim 4 wherein each respective turbo decoder module comprises a common input bus for the input data samples and the a priori bit probability values.
6. The turbo decoder system of claim 4 wherein the turbo decoding algorithm comprises a MAP decoding algorithm.
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