Digital double sampling in time integrating pixel sensors

[0002] The subject matter of the present application is related to copending U.S. application Ser. No. 16/012,944, filed herewith and having the same filing date, titled “TIME INTEGRATING PIXEL SENSOR”, which is assigned to Motorola and expressly incorporated herein by reference.

[0003] This invention relates generally to techniques and apparatus for image sensing, and more particularly to a method and apparatus for obtaining a digital measurement of a photo-current.

[0004] A typical optical detector, such a charge-coupled device (CCD), consists of an array of pixels each with its own pn junction photodiodes. Each photodiode has a capacitance associated with it, and when light falls on the detector the resulting photo-current charges the capacitance. The accumulated charge is thus the time integral of the light intensity falling on each pixel. The CCD periodically and sequentially switches the charge to a video line, resulting in a series of pulses, which can be converted into a voltage signal representing the light pattern incident on the array. If the integration time is too long, the device will saturate. If the integration time is too short, the voltage signal will be lost in the noise of the device. When a detector is reset the capacitor is discharged the voltage across the capacitor does not go to zero because of residual electrical noise in the circuit. The noise is referred to as reset noise. For example, a root-mean-square (rms) level of about 100 electrons might remain in the output sense capacitor after each pixel's charge packet is read. The reset noise increases in proportion to temperature, so the problem is more of a concern in devices that need to operate at higher temperatures.

[0005] One approach to reducing reset noise is the use of analog differential measurements through a double sampling technique. This approach first mirrors the initial charge offset in the output sense capacitor onto another capacitor and then reads the accumulated signal charge at the predetermined integration time. A differential measurement is performed on these two analog values either on a per-column basis or a on a per-pixel basis. Column-based calculations require twice the bandwidth while pixel-based differential measurements are sensitive to higher temperatures since the initial reading is fed as an output to a differential amplifier. Technology scaling produces additional concerns, as differential measurements become more sensitive to temperature variations and lower biasing levels make reset operations harder to perform.

[0006] In light of the foregoing discussion, it can be seen that there is a need in the art to have pixel sensors and image sensor arrays that are more robust in the presence of reset noise.

[0007] The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself however, both as to organization and method of operation, together with objects and advantages thereof, may be best understood by reference to the following detailed description of the invention, which describes certain exemplary embodiments of the invention, taken in conjunction with the accompanying drawings in which:

[0008] FIG. 1 is a block diagram of a photodiode sensor, in accordance with an aspect of the present invention.

[0009] FIG. 2 is a graph of showing photo-voltage as function of integration time for a photodiode sensor, in accordance with an aspect of the present invention.

[0010] FIG. 3 is a block diagram of a system utilizing a photodiode sensor array, in accordance with an aspect of the present invention.

[0011] FIG. 4 is a flow chart showing a method of sensing optical power in accordance with the present invention.

[0012] FIGS. 5A-5C are block diagrams of three alternative embodiments of devices in accordance with the present invention.

[0013] FIG. 6 is a circuit diagram in accordance with an embodiment of the present invention.

[0014] FIG. 7 is a graph illustrative of an embodiment of the present invention.

[0015] While this invention is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail specific embodiments, with the understanding that the present disclosure is to be considered as an example of the principles of the invention and not intended to limit the invention to the specific embodiments shown and described. In the description below, like reference numerals are used to describe the same, similar or corresponding parts in the several views of the drawings.

[0016] Referring now to FIG. 1, a time-integrating pixel architecture 100 of a preferred embodiment of the invention is shown. The pixel architecture 100 comprises a photo-detector 102 and a floating diffusion capacitor 104 with capacitance C_fd. In operation, the photo-current charges the floating diffusion capacitor and produces a photo-voltage 106. The charge is allowed to move directly from the photo-detector to the diffusion capacitor without the use of a transfer gate. The photo-voltage 106, sensed by the floating diffusion capacitor, and a reference voltage 126 are supplied as inputs to comparator 110. If the system is reset at time t=0, the voltage V across the capacitor at time t is the time integral of the photo-current i, which is given by $V=\frac{1}{C_{\mathrm{fd}}}{\int }_0^{t}i\left(\tau \right)·d\tau +V_{\mathrm{reset}}=\frac{\mathrm{it}}{C_{\mathrm{fd}}}+V_{\mathrm{reset}},$

[0017] where C_fdis the capacitance of the floating diffusion capacitor, t is the integration time of the capacitor and V_resetis the voltage due to reset noise. The photo-current is given by $i=\frac{\mathrm{PqQE}\lambda }{\mathrm{hc}}$

[0018] where P is the illumination intensity, q is the charge on an electron, λ is the wavelength of the light, c is the speed of light, h is Planks constant and QE is the quantum efficiency of the photo-detector. Hence the voltage across the capacitor is related to the integration time $V=\frac{\mathrm{PqQE}\lambda t}{C_{\mathrm{fd}}\mathrm{hc}}+V_{\mathrm{reset}}=\frac{P}{K}t+V_{\mathrm{reset}},$

[0019] where $K=\frac{C_{\mathrm{fd}}\mathrm{hc}}{\mathrm{qQE}\lambda }$

[0020] is a constant. For an illumination intensity P_i, the time to reach a reference voltage V₁is $t_1=K\frac{\left(V_1-V_{\mathrm{reset}}\right)}{P_i}.$

[0021] That is, after an integration time t₁, the photo-voltage 106 sensed by the floating diffusion capacitor and the reference voltage 126 are equal. In the pixel architecture shown in FIG. 1, a global counter 111 is reset at time t=0. The global counter value is supplied to the pixel architecture via pixel data memory decoder 112 and data bus 114. The switch 116 provides a logic control signal 118 to selector 120, which causes one of the two reference voltages 122 and 124 to passed to the output 126 of the selector 120. Initially, the lower of the two voltages 122 and 124 is selected. When the photo-voltage 106 exceeds the reference voltage 126 for a particular pixel, the output 128 from the comparator 110 changes value. At that time the global counter value is latched and stored in the first pixel data buffer 130. Optionally, the counter value may be negated by passing it through inverter 132. Latching the counter values avoids the need to interrogate the comparator output. In the preferred embodiment, the counter value is stored as a 10-bit value in the pixel data buffer 130. However, different size buffers may be used. Generally, larger buffers are more expensive but provide greater accuracy. One latch is used for each bit in the buffer. In the figure the latching mechanism is assumed to be an integral part of the pixel data buffer. After the counter value has been stored in the first pixel data buffer 130, the logic control signal 118 is switched so that the higher of the two voltages 122 and 124 is passed to the output 126 of the selector 120. This provides a higher reference voltage level. When the higher reference voltage level is exceeded, the value of the global counter is latched into the second pixel data buffer 134. The first and second pixel data buffers then contain the global counter values corresponding to the times taken for the sense capacitor to reach the two reference voltages.

[0022] For an illumination intensity P_i, the time to reach the higher reference voltage V₂is $t_2=K\frac{\left(V_2-V_{\mathrm{reset}}\right)}{P_i}.$

[0023] The difference between the two integration times is $t_2-t_1=K\frac{\left(V_2-V_1\right)}{P_i}$

[0024] which is not dependent upon the reset voltage V_reset. The illumination intensity P_Imay be calculated as $P_i=K\frac{\left(V_2-V_1\right)}{t_2-t_1}.$

[0025] The illumination intensity P_Ican therefore be calculated from knowledge of the two reference voltages, the two integration times and the constant K.

[0026] The apparatus shown in FIG. 1 provides direct digital values (the two counter values) related to the illumination intensity. This is in contrast to prior systems in which an analog voltage is sensed and then converted to digital value using an analog-to-digital converter. The simplicity of the system of the present invention compared to prior systems allows for sensors that are both smaller and cheaper. In addition, the calculated illumination intensity is not sensitive to the reset voltage.

[0027] In FIG. 1, only a single pixel sensor is shown. However, it is envisioned that an array of pixel sensors will be integrated in a single device, such as a CMOS device, may be utilized in conjunction with the present invention. Pixel data memory decoder 112 is coupled to a data bus 114 and is used to decode the data from individual pixel sensors and send it via data bus 136 to a processor (not shown). Logic elements in switch 116 are used to route data from the pixel data buffers 130 and 134 to the bus 114.

[0028] FIG. 2 is a graph showing photo-voltage as a function of integration time for a photodiode sensor of the present invention. The line labeled P_kshows the relationship between integration time and photo-voltage for light with optical power P_k. At time t₁, the photo-voltage reaches the first reference voltage V₁, as denoted by A in the figure. At this time the output from the comparator (110 in FIG. 1) switches value. This causes the global counter to be latched into the first pixel data buffer (130 in FIG. 1). At a later time t₂the photo-voltage will reach the second reference V₂, as denoted by B in the figure. At this time, the global counter is latched into the second pixel data buffer (134 in FIG. 1). At a still later time, t_maxthe photo-voltage will reach the saturation level V_sat.

[0029] If the voltage reference is increased, a longer integration time will be required. If the voltage reference is decreased, a shorter integration time will be required. Even when no light is incident upon the photo-detector, small currents and voltages will be present in the sensor because of electrical noise. Voltage levels below the voltage noise floor will be undetectable, so the first voltage reference level is preferably set above the voltage noise floor. There is an upper limit to the amount of charge that can be stored by the capacitor. The voltage corresponding to this maximum charge is called the saturation voltage. The second voltage reference level is set at or below the saturation voltage.

[0030] The integration times may be determined from the difference between the counter values. If the counter value at time t₁is denoted N₁and the counter value at time t₂is denoted N₂, the optical power is given by $P_i=C\frac{V_2-V_1}{N_2-N_1},$

[0031] where C=K×f_counteris a constant and f_counteris the counter frequency. This computation is performed by the processor. Pixel data memory decoder 112 in FIG. 1 is also used to couple the global counter 111 to the individual pixel sensors via bus 114.

[0032] Referring to FIG. 3, the individual pixel sensors are preferably arranged in an array 302. Each element of the array comprises a photo-detector, a floating diffusion capacitor electrically coupled to the photo-detector and a comparator. The comparator has a first input for receiving a reference voltage, a second input electrically coupled to the floating diffusion capacitor and an output. Each element also includes a pixel data buffer, which may be a random access memory (RAM). The pixel array is addressed in a manner similar to that used to address standard memory (DRAM, SRAM, etc). Each column of pixels is preferably connected to its own data bus. A row address is sent to a pixel row address decoder 304 that selects a particular row of pixels using word lines 314. Pixel column address decoder 306 also includes a data decoder that may be used to receive data from or transmit data to selected columns of pixels, according to the selected row. This allows individual pixels to be addressed, so that data can be “written into” or “read out of” the pixels via pixel bit lines 316. A global sequencer 312 is coupled to the system controller 310. The global sequencer generates lookup table addresses 324 and 334 that are passed to lookup tables 326 and 334. Lookup table 1, 326, is used to convert the lookup table addresses 324 into voltage reference values which are passed to a digital to analog converter (DAC) 328. The DAC 328 in turn generates the reference voltage 108 that is passed to the pixel array 302. Lookup table 2, 334, is used to convert actual counter values into system appropriate digital code values that are passed to the pixels via the pixel column decoder 308. The digital code values need not be linearly related to the actual counter values. The digital code values may correspond to the optical power level associated with the each counter value for a given voltage reference. This avoids the need to compute the optical power levels later. In addition, a pixel timing controller 308 is coupled to the row and column decoders to control the timing of access to the individual elements of the array. The pixel bit data is sensed by the row decoder 306 via bit-lines 316 and the data is sent as a multiplexed data stream 322 to the image processor and system controller 310. The image processor performs the conversion from integration time to optical power for each of the pixel sensors and may perform other image processing functions, such as color processing or compression. Data representing the processed image is output from the image processor at 318. The conversion may be performed via a lookup table or via a calculation or by a combination thereof. The system controller, included in 310, provides pixel array timing and control signals 320 that are passed to a pixel timing and control unit 308. The pixel timing and control unit 308 controls the pixel row decoder 304 and the pixel column decoder 306. The system controller, included in 310, also provides control of the global counter 312.

[0033] A flow chart depicting one embodiment of the method of the current invention is shown in FIG. 4. Operation begins at start block 402. The pixel photo-detector is reset at block 404, by discharging the floating diffusion capacitor for example. The lower of the two reference voltages is selected at block 405. The output from the photo-detector is integrated at block 406. If a floating discharge capacitor is used, the photo-detector output current is integrated by the capacitor to produce a photo-voltage. At decision block 408 the photo-voltage is compared with the reference voltage. If the photo-voltage is less than the reference voltage as depicted by the positive branch from decision block 408, the current value of a global counter (which is supplied to the pixel sensor) is stored into a first pixel data buffer at block 410. Flow than continues to decision block 412. If the photo-voltage exceeds the reference voltage, as depicted by the negative branch from decision block 408, the higher reference voltage is selected at block 411 and the integration process continues. Decision block 408 may be implemented as a comparator. Thus the last value stored in the first pixel data buffer will be the counter value at which the photo-voltage reaches the lower reference voltage. The value is thus latched into the pixel data buffer. While the photo-voltage is less than the higher reference voltage as depicted by the positive branch from decision block 408, the current value of the global counter is stored into a second pixel data buffer at block 410. When the higher reference voltage is exceeded, the current global counter value is not longer written into the second pixel data buffer, so the value when the threshold was crossed is latched into the buffer. At decision block 412, a check is made to determine if the maximum time for integration has been exceeded. If the maximum time has been exceeded, as depicted by the positive branch from decision block 412, the pixel data buffer is read. If the maximum time has not been exceeded, as depicted by the negative branch from decision block 412, the system waits until the time has been exceeded. At block 414, the pixel data buffers are read, whether or not the reference voltages have been reached. At block 416, the optical power is determined from the counter values read from the pixel data buffers. This determination may be performed in an integrated processor or in a processor external to the sensor array. The determination may use the calculation $P_i=C\frac{V_2-V_1}{N_2-N_1},$

[0034] as described above. When inverter 132 in FIG. 1 is used, the value (−N₁) is stored in the first pixel data buffer, so the denominator in the expression can be computed by simply adding the values from the two pixel data buffers.

[0035] The calculation may be performed by use of a lookup table indexed by the counter difference N₂−N₁, or indexed by the integration time calculated from the counter difference.

[0036] In the embodiment described above, each pixel element includes two data buffers and the computation of the difference N₂−N₁is performed by a processor external to the pixel element. In an alternative embodiment the sum N₂+(−N₁) is performer by an adder integrated with each pixel element. The adder may be a serial adder or a parallel adder. An advantage of this embodiment is that the data rate from an array of pixel elements to an external processor is reduced by a factor of two, since only the difference between counter values is passed to the processor.

[0037] In a still further embodiment, the pixel array is configured as an integrated circuit that includes one or more adders that are shared by the pixel elements. Again, data flow to an external processor is reduced.

[0038] In a still further embodiment, the pixel data buffers are not integrated with each pixel element. Instead, a central memory is used for all of the pixel elements. This central memory may be part of an integrated circuit including the pixel array or may be a separate memory either packaged with the pixel array or connected to it via a data bus.

[0039] Some of these various embodiments are shown in FIGS. 5A-5C. FIG. 5A depicts a pixel sensor array 502 that includes an array of pixel elements 510. The adder 512 and the pixel data memory 514 is not integrated with each individual pixel element. Instead either may be integrated with the pixel array in a single integrated circuit, as depicted by the dashed line, or they may be separate from the pixel array integrated circuit and connected to it via a bus. FIG. 5B depicts a pixel sensor array 504 in which the adder 512 is not integrated with each individual pixel element. However, the pixel data memory and the pixel elements are integrated in merged pixel array/memory unit 516. As shown in FIG. 1, each pixel element has two data buffers associated with it. The adder 512 may be integrated with the pixel array in a single integrated circuit, as depicted by the dashed line, or separate from the pixel array integrated circuit and connected to it via a bus. FIG. 5C depicts a pixel sensor array 504 in which an adder and pixel data buffers are integrated with each individual pixel element, so that all elements are included in the merged pixel array/memory array/adder array.518.

[0040] A further embodiment of the invention is shown in FIG. 6. The embodiment implements digital double sampling of the photo-voltage. In order to capture two voltage readings within one single frame, and thereby perform digital double sampling, a pixel is designed to operate in a voltage capture mode. Referring to FIG. 6, the T_SAMP signal 602 is a trigger signal that is used to trigger a sample and hold unit 604 and read the photodiode voltage 106 at two different times. The sample and hold (S/H) unit 604 samples the voltage at the capacitor 104 at each sampling instance and latches the value to one of the inputs of the comparator 110. The same signal is also used to control the switching block (SW) 116 so that a digital value from the data bus 114 is read and stored in the register 130 or 134 as appropriate. The V_RAMP signal 608 is a linear voltage ramp used as reference to compare the sampled voltage of the photodiode and load, at the proper instant, a digital value from the bus 114 when the comparator 110 is triggered. Because two different values are sampled at the comparator at different times, the V_RAMP signal must also be ramped through twice to perform the digital mapping of both values. This requires that the data bus operates at twice the speed since a sequence of identical digital values needs to be available twice in the bus within a single frame. The remaining elements of FIG. 6 are described above with reference to FIG. 1.

[0041] FIG. 7 illustrates the temporal behavior of the signals T_SAMP and V_RAMP, and the sampled photodiode voltage. The T_SAMP signal provides triggers at times T1 and T2, corresponding to rising edges of the T_SAMP voltage signal. The voltage reference signal V_RAMP, shown as a broken line in the figure, rises from a minimum at times T1 and T2. In this embodiment, the V_RAMP signal has a “saw-tooth” waveform with two pulses in each frame period. At sample time T1 the photo-voltage has reached a level V1. This value is sampled and held, as indicated the plot of the sample and hold voltage. When the V_RAMP signal and the sample and hold signal are equal, as indicated by the point 702, the value from the digital data bus is stored in the first register (130 in FIG. 6). At sample time T2 the photo-voltage has reached a level V2. This value is sampled and held, as indicated the plot of the sample and hold voltage. When the V_RAMP signal and the sample and hold signal are equal, as indicated by the point 704, the value from the digital data bus is inverted stored in the second register (134 in FIG. 6). The values stored in the registers are then read via the data bus and the values are used to determine the optical power falling on this pixel. This process is repeated in each T_FRAME period.

[0042] Those of ordinary skill in the art will recognize that the present invention has been described in terms of exemplary embodiments based upon use of a capacitor to integrate the photo-detector output and a comparator to latch the global counter value into a pixel data buffers. However, the invention should not be so limited, since the present invention could be implemented using hardware or software component equivalents to those described and claimed. Many other variations will also be evident to those of ordinary skill in the art.

[0043] While the invention has been described in conjunction with specific embodiments, it is evident that many alternatives, modifications, permutations and variations will become apparent to those of ordinary skill in the art in light of the foregoing description. Accordingly, it is intended that the present invention embrace all such alternatives, modifications and variations as fall within the scope of the appended claims.