Information processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions

[0002] 1. Field of the Invention

[0003] The present invention is related to an information processing apparatus provided with an optimized executable instruction extracting unit for extending a compressed instruction into the corresponding executable instructions in accordance with the instruction code of a target executable program.

[0004] 2. Description of the Related Art

[0005] In the field of control systems with embedded microcomputers, the size of instruction code in the memory of a processor can influence the production cost of the entire system. A smaller size of instruction code in the memory has an advantage in costs. The technique of compressing the executable instructions and extending the compressed instructions is one for techniques of reducing the size of instruction code in the memory.

[0006] In the case of the executable instructions, each instruction as pointed by an address register and fetched from the memory is latched by an instruction register and transferred to an instruction decoding unit through a multiplexer in order to decode the executable instructions.

[0007] On the other hand, in the case of the compressed instructions, each instruction as pointed by the address register and fetched from the memory is extended into the corresponding executable instructions and then transferred to the instruction decoding unit through the multiplexer in order to decode the executable instructions.

[0008] In accordance with “Intel Architecture Optimization Manual”, 1997, Intel Corporation, a “macro-instruction” stored in the instruction memory of the processor as discussed therein is generally extended into a plurality of corresponding “micro-ops”. Furthermore, in accordance with “TMS320C3x User's Guide”, 1997, TEXAS INSTRUMENTS, two instructions of “MPYI3” and “ADDIY3” for example are compressed as a compressed instruction “MPYI3| |ADDIY3” by imposing restrictions upon the usage such as the restrictions upon the usage the range of the register number available within the register field in the instruction format.

[0009] Such a compressed instruction of this kind is generated by compressing an instruction sequence which frequently occurs in the instruction codes of many application programs. However, in the actual case, there are a variety of application programs. Namely, while the compressed instruction set as defined by one processor is effective for a specific type of application program, it frequently becomes ineffective for another type of application program.

[0010] In order to improve the shortcomings, it has been contemplated to change the processor for the respective application program under question in order to make use of the compressed instruction set as optimized for the application program. However, it is ineffective to use different processors for different application programs. This is because the programmers are requested to understand the basic architecture of the processor and the software development environment each time as a new processor is employed. On the other hand, it is frequently the case that there is no processor available supporting the compressed instructions which a user desires. This is because many processors are designed in order to support the compressed instructions suitable for major application programs of which a substantial output of copies are expected.

[0011] As explained above, in the case of the prior art information processing apparatuses, the compressed instruction set is fixedly defined for each system. For this reason, while the compressed instruction set as defined in the system is effective for a specific type of application program, it becomes ineffective for another type of application program. In this case, there is the disadvantage that the use of compressed instructions can no longer improve the performance of the system.

[0012] It is an object of the present invention to provide an information processing apparatus having a compact storage region required of an executable program with a reduced number of instructions constituting the executable program.

[0013] Particularly, the information processing apparatus in accordance with the present invention is characterized by provision of a executable instruction extracting unit for extending a compressed instruction into a plurality of corresponding executable instructions, and a reconfiguration unit for reconfiguring and optimizing the executable instruction extracting unit suitable for the executable program.

[0014] In accordance with the present invention, the executable instruction extracting unit is reconfigured for the respective target program so that the number of the constituent instructions can be suppressed, resulting in compaction of the storage region for storing the target program.

[0015] FIG. 1 is a block diagram showing an information processing apparatus in accordance with a first embodiment of the present invention.

[0016] FIG. 2 shows an exemplary table of a compressed/executable instruction correspondence table.

[0017] FIG. 3 shows an example of assemble code corresponding to the executable object code as illustrated in FIG. 1.

[0018] FIGS. 4A-4C show an example of a executable instruction extracting unit.

[0019] FIG. 5 is a block diagram showing an exemplary system comprising the processor and the main memory as illustrated in FIG. 1.

[0020] FIG. 6 is an operational timing chart of signals within a processor.

[0021] FIG. 7 is a block diagram showing an information processing apparatus in accordance with a second embodiment of the present invention.

[0022] FIG. 8 is a block diagram showing an information processing apparatus in accordance with a third embodiment of the present invention.

[0023] FIG. 9 illustrates an assembler source file and instruction sequence occurrence frequency data as illustrated in FIG. 8.

[0024] FIG. 10 shows an example of the compressed/executable instruction correspondence table as illustrated in FIG. 8.

[0025] FIG. 11 shows an example of the assembler source file corresponding to the executable object code as compressed.

[0026] FIG. 12 illustrates other examples of the assembler source file and instruction sequence occurrence frequency data as illustrated in FIG. 8.

[0027] FIG. 13 shows another example of the compressed/executable instruction correspondence table as illustrated in FIG. 8.

[0028] FIG. 14 shows an example of the instruction sequence which is not compressed as a compressed instruction.

[0029] FIG. 15 shows another example of the assembler source file corresponding to the executable object code as compressed.

[0030] FIG. 16 shows a block diagram showing an information processing apparatus in accordance with a fourth embodiment of the present invention.

[0031] FIG. 17 shows an example of the instruction sequence pattern templates as illustrated in FIG. 16.

[0032] FIG. 18 illustrates an example of the assembler source file corresponding to the executable object code as illustrated in FIG. 16 and an example of instruction sequence occurrence frequency data as illustrated in FIG. 16.

[0033] FIG. 19 shows a block diagram showing an information processing apparatus in accordance with a fifth embodiment of the present invention.

[0034] FIG. 20 illustrates an example of an assembler source file as illustrated in FIG. 19 and an example of assembler source code corresponding to the executable object code as compressed and generated on the basis of the assembler source file.

[0035] FIG. 21 illustrates an example of instruction sequence occurrence frequency data as illustrated in FIG. 19.

[0036] FIGS. 22A and 22B show another example of the compressed/executable instruction correspondence table as illustrated in FIG. 19.

[0037] Hereinbelow, several preferred embodiments in accordance with the present invention will be explained in conjunction with the accompanied drawings.

[0038] [EMBODIMENT 1]

[0039] FIG. 1 shows a block diagram showing an information processing apparatus in accordance with a first embodiment of the present invention.

[0040] In the figure, the information processing apparatus of this embodiment is provided with a processor 151 and an executable instruction extracting unit reconfiguration unit 9. The processor 151 is composed of an address register 100, an instruction register 102, a multiplexer 104, an instruction cache 105, an instruction decoding unit 12, an instruction execution unit 13 for executing instructions as decoded by the instruction decoding unit 12, and an executable instruction extracting unit 14.

[0041] A compressed/executable instruction correspondence table 7 is input to the executable instruction extracting unit reconfiguration unit 9. The executable instruction extracting unit reconfiguration unit 9 serves to reconfigure the executable instruction extracting unit 14 on the basis of the compressed/executable instruction correspondence table 7.

[0042] FIG. 2 shows an exemplary table of the compressed/executable instruction correspondence table 7.

[0043] Executable object code 110 having been compressed is input to a main memory 101.

[0044] FIG. 2 shows an example of assemble code corresponding to the executable object code 110.

[0045] The executable instruction extracting unit 14 is designed to be reconfigurable by external means and serves to convert the constituent compressed instructions into the corresponding sequence of executable instructions by extending the respective compressed instructions. For example, in the case that the processor 151 is fixedly designed, the executable instruction extracting unit 14 is composed of a Field Programmable Gate Array (FPGA), Programmable Logic Array and so forth. Alternatively, in the case that the processor 151 is defined by a class Hardware Description Languages (HDL) or a class of Description Languages for CAD or Netlist with the restriction conditions posed thereto and a variety of configuration files, the description, i.e., the configuration itself of the executable instruction extracting unit 14 is assumed to be given to allow reconfiguration.

[0046] FIGS. 4A and 4B show an example of source code of HDL to describe the executable instruction extracting unit 14. The HDL used in Verilog, which is one of the representative HDLs. Also, the same figures show an example that two compressed instructions, each of which consists of two executable instructions as illustrated in FIG. 2, are defined.

[0047] The file as illustrated in FIG. 4C is prepared and included by the name of “compress_extend_table” in line 3 of the source code as illustrated in FIG. 4A, and therefore the files as illustrated in FIGS. 4A, 4B and 4C are complied in order to construct the executable instruction extracting unit 14.

[0048] The executable instruction extracting unit reconfiguration unit 9 serves to perform reconfiguration of the executable instruction extracting unit 14 by rewriting the file as illustrated in FIG. 4C which is included in the file as illustrated in FIGS. 4A and 4B.

[0049] Also, the file as illustrated in FIGS. 4A and 4B itself can be rewritten to perform reconfiguration of the executable instruction extracting unit 14. Namely, if the “module extender” is included in the HDL description as the definition of the entirety of the processor 151, the included “module extender” is recognized as the executable instruction extracting unit 14 and therefore the process of generating the entirety of the “module extender” is recognized as the reconfiguration of the executable instruction extracting unit 14.

[0050] Next, the executable instruction extracting unit 14 will be explained in the case that it is implemented by an FPGA.

[0051] The FPGA is composed of a plurality of cells arranged within the chip. Each cell in turn is composed of combination of a plurality of F/Fs (flip-flops) and switches functioning as logics. The cells are arranged in a matrix array in the form of a grid with interconnection wirings between adjacent cells, i.e, across bars of the grid on which the switches are located in order to determine how to interconnect the respective cells. The information of the configuration of the interconnection is input in the form of packets, and the corresponding configuration is maintained as long as the electric power is being supplied. In other words, some packet is input in order to determine the states of the switches within a certain cell corresponding to a required logic while another packet is input in order to determine the states of the switches located on the interconnection between one cell and wirings. After the states of all the switches have been determined, the configuration of the FPGA is maintained.

[0052] In accordance with the present invention, an FPGA is formed within the same processor which is provided with I/O pins through which packets can be input in order to implement the reconfigurable portion of the executable instruction extracting unit 14.

[0053] Next, referring to FIG. 5 and FIG. 6, expansion of the compressed instruction into the corresponding executable instructions will be explained.

[0054] FIG. 5 shows a block diagram showing the connection relationship among the address register 100, the main memory 101, the instruction register 102, the multiplexer 104, the instruction cache 105, the instruction decoding unit 12, the instruction execution unit 13 and the executable instruction extracting unit 14 in accordance with the first embodiment.

[0055] In FIG. 5, each instruction as pointed by the address register 100 and fetched from the instruction cache 105 or the main memory 101 is either a executable instruction or a compressed instruction. In the case of a executable instruction, it is latched by the instruction register 102 and then transferred to the instruction decoding unit 12 through the multiplexer 104 in order to decode the executable instruction. On the other hand, in the case of a compressed instruction, it is extended into the corresponding executable instructions and then sequentially transferred to the instruction decoding unit 12 through the multiplexer 104 in order to decode the executable instructions.

[0056] FIG. 6 shows an operational timing chart of fetching executable and compressed instructions and decoding them.

[0057] As illustrated in FIG. 6, the executable instruction extracting unit 14 serves to extend a compressed instruction B into the corresponding executable instructions b1, b2 and b3 while it transmits control signals to the multiplexer 104 in order to input to the instruction decoding unit 12 an instruction A, the instruction b1, the instruction b2 and the instruction b3 in this order in synchronism with clocks, while it transmits control signals to the address register 100 to maintain the content thereof in order that the executable instruction C next to the compressed instruction B is supplied to the instruction decoding unit 12 just after the instruction b3.

[0058] In order to extend the compressed instruction B into the corresponding executable instructions b1, b2 and b3 and transferred in the appropriate order as illustrated in FIG. 6 by appropriate hardwired control, the executable instruction b1 is directly output; the executable instruction b2 is output through one flip-flop; and the executable instruction b3 is output through two flip-flops.

[0059] As explained above, in accordance with the first embodiment, the executable instruction extracting unit 14 is reconfigured on the basis of the compressed/executable instruction correspondence table 7 in order to extend each compressed instruction contained in the executable object code 110 as compressed into the corresponding executable instructions, which are then decoded by means of the instruction decoding unit 12 and executed by means of the instruction execution unit 13.

[0060] When the executable object code 110 as compressed is replaced by new executable object code as compressed, the executable instruction extracting unit 14 is reconfigured on the basis of a new compressed/executable instruction correspondence table for the new compressed instructions contained in the new executable object code. The executable instruction extracting unit 14 as reconfigured serves to extend each new compressed instruction into the corresponding executable instructions, which are then decoded by means of the instruction decoding unit 12 and executed by means of the instruction execution unit 13.

[0061] As explained above, in accordance with the first embodiment, the executable instruction extracting unit is optimally reconfigured for the respective target program so that the number of the constituent instructions can be suppressed, resulting in compaction of the storage region for storing the target program.

[0062] While the compressed instructions are input to the executable instruction extracting unit 14 from the main memory 101 located external to the processor through the instruction cache 105 and the instruction register 102 in the case of the first embodiment, as follows.

[0063] The compressed instructions are input to the executable instruction extracting unit from a main memory located external to the processor through the instruction register internal to the processor.

[0064] The compressed instructions are input to the executable instruction extracting unit from a ROM located external to the processor through the instruction register internal to the processor.

[0065] The compressed instructions are input to the executable instruction extracting unit from a main memory located external to the processor through an instruction SRAM internal to the processor and the instruction register internal to the processor.

[0066] The compressed instructions are input to the executable instruction extracting unit from a ROM located external to the processor through the instruction cache internal to the processor and the instruction register internal to the processor.

[0067] The compressed instructions are input to the executable instruction extracting unit from a ROM located external to the processor through an instruction SRAM internal to the processor and the instruction register internal to the processor.

[0068] The compressed instructions are input to the executable instruction extracting unit from a ROM located internal to the processor through the instruction register internal to the processor.

[0069] Usually, the memory space defined by the address available in an instruction SRAM is divided into two banks. For example, instructions are transferred to the bank 1 of the SRAM from the main memory under Direct Memory Access control while the instructions saved in the bank 2 of the SRAM are transferred to the executable instruction extracting unit from the bank 2 of the SRAM through the instruction register. When the execution of the instructions saved in the bank 2 of the SRAM has been finished, the banks of the SRAM are switched. Namely, the address range accessed under Direct Memory Access control and the address range accessed by the instruction register are switched followed by the similar operation.

[0070] [Embodiment 2]

[0071] Next, a second embodiment of the present invention will be explained with reference to FIG. 7. As illustrated in the same figure, the differences of the second embodiment from the first embodiment resides in that an instruction execution unit 22 functions also as the executable instruction extracting unit reconfiguration unit 9 and serves to reconfigure the executable instruction extracting unit 14 on the basis of the compressed/executable instruction correspondence table 7. While the other constituents elements have the same structures and functions of the previous embodiment, detailed explanation is not repeated.

[0072] The compression/expansion correspondence table 7 can be referred to by several procedures, for example, by defining compressed instructions for all or part of the entries with operands registered in the compression/expansion correspondence table 7 while the executable instruction extracting unit reconfiguration unit 9 is formed with one or more instruction sequences as illustrated in FIG. 9. Also, in accordance with another of the alternative techniques for referring to the compression/expansion correspondence table 7, the table 7 is written in the main memory 101 or a data SRAM located inside of the processor and referred to by means of a load instruction and so forth. Furthermore, in accordance with a further one of the alternative techniques for referring to the compression/expansion correspondence table 7, the instruction execution unit 22 is designed to incorporate the table 7 within itself.

[0073] In the case that the instruction execution unit 22 is designed to incorporate the compression/expansion correspondence table 7 within itself, it is implemented in the same manner as the executable instruction extracting unit 14 is reconfigured.

[0074] Also in accordance with the second embodiment of this design, there are similar advantages as in the first embodiment.

[0075] [Embodiment 3]

[0076] Next, a third embodiment of the present invention will be explained with reference to FIGS. 8 to 15.

[0077] FIG. 8 shows a schematic diagram showing the overall configuration of the third embodiment. The differences of the third embodiment from the first embodiment resides in that the compressed/executable instruction correspondence table 7 is generated by an instruction sequence occurrence frequency detecting unit 401 and a compressed instruction definition unit 601 and that executable object code 111 is generated by an object conversion unit 801.

[0078] FIG. 9 illustrates an assembler source file 203 and instruction sequence occurrence frequency data 501. With reference to the same figure, the instruction sequence occurrence frequency detecting unit 401 will be explained.

[0079] The instruction sequence occurrence frequency detecting unit 401 serves to obtain the occurrence frequency of the instruction sequences contained in the assembler source file 203 by comparing each adjacent pair of the executable instructions contained therein.

[0080] For example, from the instruction on the first line of the assembler source file 203, i.e,

[0081] sll r2, r2, 16

[0082] and the instruction on the second line, i.e,

[0083] lw r3, 0(r2),

[0084] the instruction sequence of

[0085] sll r2, r2, 16 and

[0086] lw r3, 0(2)

[0087] is counted as the occurrence frequency=1.

[0088] Also, from the instruction on the second line of the assembler source file 203, i.e,

[0089] lw r3, 0(r2)

[0090] and the instruction on the third line, i.e,

[0091] lw r3, 0(5)

[0092] the instruction sequence of

[0093] lw r3, 0(r2) and

[0094] lw r3, 0(5)

[0095] is counted as the occurrence frequency=1.

[0096] The occurrence frequency of the instruction sequence of the third line and the fourth line and the occurrence frequency of the instruction sequence of the fourth line and the fifth line are counted respectively in the same manner.

[0097] Next, the instruction on the fifth line, i.e,

[0098] sll r2, r2, 16

[0099] is identical to the instruction on the first line while the instruction on the sixth line, i.e,

[0100] lw r3, 0(r2)

[0101] is identical to the instruction on the second line.

[0102] Accordingly, the instruction sequence of

[0103] sll r2, r2, 16 and

[0104] lw r3, 0(2)

[0105] is counted as the occurrence frequency=2

[0106] The instruction sequence occurrence frequency data 501 is generated in this manner.

[0107] For example, the instruction sequence of

[0108] sll r2, r2, 16

[0109] lw r3, 0(r2)

[0110] is compressed as a compressed instruction as “compress_inst_—0 r2, r3”0 and registered in the compressed/executable instruction correspondence table 7.

[0111] FIG. 10 shows an example of the compressed/executable instruction correspondence table 7. The assembler source file is compressed on the basis of the compressed/executable instruction correspondence table 7 in order to generate an assembler source file as compressed. FIG. 10 shows an example of the assembler source file as compressed.

[0112] Next, an exemplary modification of the instruction sequence occurrence frequency detecting unit 401 will be explained.

[0113] Namely, the instruction sequence occurrence frequency detecting unit 401 serves to modify the value of a field of an instruction contained in the instruction sequence as detected under the condition that the result of execution of the executable program is not influenced by the modification, and as a result if the instruction sequence as detected is identical to one of the instruction sequences previously detected, the occurrence frequency of said one of the instruction sequences is counted up.

[0114] More specifically speaking with reference to FIG. 12, when the instructions on the first and second lines of the assembler source file 204 are taken into consideration, the register r2 appearing twice as operands in the instruction on the first line appears again as an operand in the instruction on the second line and therefore these operands are commonly labeled rA while the register r3 appearing as an operand in the instruction on the second line is labeled rB.

[0115] The instruction on the first line of the assembler source file 203, i.e,

[0116] sll r2, r2, 16

[0117] and the instruction on the second line, i.e,

[0118] lw r3, 0(r2),

[0119] are then represented by the instruction sequence of

[0120] sll rA, rA, 16 and

[0121] lw rB, 0(rA)

[0122] which is then counted as the occurrence frequency=1.

[0123] Also, the instructions on the fifth and sixth lines are expressed by the instruction sequence of

[0124] sll rA, rA, 16

[0125] lw rB, 0(rA)

[0126] which is then counted as the occurrence frequency=1 in the same manner.

[0127] Furthermore, the register r9 appearing as an operand in the instruction on the eighth line and the instruction on the ninth line is labeled rA. The instructions on the eighth and ninth lines are expressed also by the instruction sequence of

[0128] sll rA, rA, 16

[0129] lw rB, 0(rA)

[0130] which is then counted as the occurrence frequency=3.

[0131] The instruction sequence of the instruction on the sixth line, i.e,

[0132] lw r3, 0(r2)

[0133] and the instruction on the seventh line, i.e,

[0134] addu r3, r3, r2

[0135] and the instruction sequence of the instruction on the ninth line, i.e,

[0136] lw r3, 0(r9)

[0137] and the instruction on the tenth line, i.e,

[0138] addu r3, r3, r9

[0139] are commonly expressed by the instruction sequence of

[0140] lw rA, 0(rB)

[0141] addu rA, rA, rB

[0142] which is then counted as the occurrence frequency=2.

[0143] The instruction sequence of the instruction on the eleventh line, i.e,

[0144] mult r4, r7, r4

[0145] and the instruction on the twelve line, i.e,

[0146] sra r4, r4, 15

[0147] and the instruction sequence of the instruction on the fifteenth line, i.e,

[0148] mult r3, r7, r3

[0149] and the instruction on the sixteenth line, i.e,

[0150] sra r3, r3, 15

[0151] are commonly expressed by the instruction sequence of

[0152] mult rA, rB, rA

[0153] sra rA, rA, 15

[0154] which is then counted as the occurrence frequency=2.

[0155] The remaining instruction sequences are counted as the occurrence frequency=1. The instruction sequence occurrence frequency data 502 as illustrated in FIG. 12 is obtained in this manner.

[0156] As a result, two instruction sequences of

[0157] sll rA, rA, 16

[0158] lw rB, 0(rA)

[0159] and

[0160] mult rA, rB, rA

[0161] sra rA, rA, 15

[0162] as illustrated in FIG. 13 and one instruction sequence of

[0163] lw rA, 0(rB)

[0164] addu rA, rA, rB

[0165] as illustrated in FIG. 14 are the candidates of the compressed instructions.

[0166] In the case that the requirement of defining compressed instructions is the occurrence frequency of the corresponding sequence of executable instructions is determined as no smaller than 2, the above three candidates are defined as the compressed instructions.

[0167] On the other hand, in the case that the requirement of compressed instructions is the occurrence frequency of the corresponding sequence of executable instructions is no smaller than 3, only the candidate of

[0168] sll rA, rA, 16

[0169] lw rB, 0(rA)

[0170] is defined as the compressed instruction.

[0171] The compressed instructions may be given arbitrary mnemonics distinctive from each other, for example,

[0172] compress_inst_1 rA, rB={sll rA, rA, 16; lw rB, 0(rA)}

[0173] compress_inst_2 rA, rB={lw rA, 0(rB); addu rA, rA, rB}

[0174] compress_inst_3 rA, rB={mult rA, rB, rA; sra rA, rA, 15}

[0175] Meanwhile, in the case that there is a executable instruction contained in a plurality of candidates of compressed instructions, the compressed instruction as actually defined has to be selected with reference to the occurrence frequencies thereof.

[0176] More specifically speaking, the instruction on the ninth line, i.e,

[0177] lw r3, 0(r9)

[0178] is contained in two candidates of compressed instructions, i.e,

[0179] compress_inst_1 rA, rB={sll rA, rA, 16; lw rB, 0(rA)}

[0180] compress_inst_2 rA, rB={lw rA, 0(rB); addu rA, rA, rB}

[0181] and therefore the candidate having a higher occurrence frequency, i.e,

[0182] compress_inst_1 rA, rB={sll rA, rA, 16; lw rB, 0(rA)}

[0183] is defined as a compressed instruction while the other candidate, i.e,

[0184] compress_inst_2 rA, rB={lw rA, 0(rB); addu rA, rA, rB}

[0185] is not defined as a compressed instruction.

[0186] FIG. 13 shows the assembler source file obtained by compressing the assembler source file 204 as illustrated in FIG. 12 on the basis of the compressed/executable instruction correspondence table 7.

[0187] Furthermore, the format of the compressed instructions is desirably defined in order that the bit width of the compressed instructions is equal to the bit width of the respective instructions contained in the instructions sequence as compressed.

[0188] The advantages of the same bit width are as follows. In the case of RISC (Reduced Instruction Set Computer) processors, the improvement of the processing speed (i.e., elevation of the operational frequency) is implemented partly by simplifying the instruction fetch control and the decoding control. One of the measures of the simplification is the fixed bit width of the instructions. By this configuration, the operation code and the register number can be directly accessed from fixed positions of the instruction register without particular operation, and therefore, the hardwired operation can be accelerated by the time of the access operation. Alternatively, while the present invention is related to the compression of the instruction sequences, the bit width of the compressed instructions may be designed shorter than the bit width of the respective instructions contained in the instructions sequence as compressed, depending upon the case. However, taking into consideration the tradeoff made between the high speed operation and the compression, it may be effective to maintain the bit width of the compressed instructions in order to cope with the specification required of the application program.

[0189] Also, the instruction sequence occurrence frequency detecting unit 401 serves to modify the order of instructions contained in the instruction sequence as detected under the condition that the result of execution of the executable program is not influenced by the modification, and as a result if the instruction sequence as detected is identical to one of the instruction sequences previously detected, the occurrence frequency of said one of the instruction sequences is counted up.

[0190] For example, either of the instruction sequence of

[0191] addu r1,r2,r3

[0192] addu r4,r5,r6

[0193] and the instruction sequence of

[0194] addu r4,r5,r6

[0195] addu r1,r2,r3

[0196] can be inversed in order to arrange the same order.

[0197] Also in accordance with the third embodiment of this design, there are similar advantages as in the first embodiment. Furthermore, the compressed/executable instruction correspondence table 7 suitable for the respective executable program can be quickly and easily generated by means of the instruction sequence occurrence frequency detecting unit 401 and the compressed instruction definition unit 601. Furthermore, the executable program 10 having been compressed can be quickly and easily generated by means of the compressed/executable instruction correspondence table 7.

[0198] [Embodiment 4]

[0199] Next, a fourth embodiment of the present invention will be explained.

[0200] FIG. 1 shows a block diagram showing an information processing apparatus in accordance with a fourth embodiment of the present invention. The differences of the fourth embodiment from the third embodiment reside in that an instruction sequence occurrence frequency detecting unit 403 serves to generate an instruction sequence occurrence frequency data 508 by the use of an instruction sequence pattern templates 3.

[0201] The instruction sequence pattern templates 3 are templates which are registered in advance the patterns of the compressed instructions and the corresponding sequences of executable instructions to be compressed together with the formats of the compressed instructions for compressing the corresponding sequences of executable instructions. The compressed instructions may be given arbitrary mnemonies distinctive from each other, for example, compress_inst_1, compress_inst_2, compress_inst_3, . . . Furthermore, the format of the compressed instructions may be defined in order that he bit width of the compressed instructions is equal to the bit width of the respective instructions contained in the instructions sequence as compressed.

[0202] The instruction sequence occurrence frequency detecting unit 403 referrs to the instruction sequence pattern templates 3 and compares the instruction sequences contained in the executable object code 2 of the target program desired to run by the processor 151 with the instruction sequence pattern as registered in the instruction sequence pattern templates 3 by a pattern matching algorithm in order to detect instruction sequence patterns and obtain the occurrence frequency thereof and the instruction sequence occurrence frequency data 503.

[0203] Also in this case, the instruction sequence occurrence frequency detecting unit 403 serves to modify the value of a field of an instruction contained in the instruction sequence as detected under the condition that the result of execution of the executable program is not influenced by the modification, in the same manner as the instruction sequence occurrence frequency detecting unit 401, and as a result if the instruction sequence as detected is identical to one of the instruction sequences previously detected, the occurrence frequency of said one of the instruction sequences is counted up.

[0204] Furthermore, the instruction sequence occurrence frequency detecting unit 403 serves to modify the order of instructions contained in the instruction sequence as detected under the condition that the result of execution of the executable program is not influenced by the modification, in the same manner as the instruction sequence occurrence frequency detecting unit 401, and as a result if the instruction sequence as detected is identical to one of the instruction sequences previously detected, the occurrence frequency of said one of the instruction sequences is counted up.

[0205] The compressed instruction definition unit 6 referrs to the instruction sequence occurrence frequency data 503 as obtained by the instruction sequence occurrence frequency detecting unit 403, defines compressed instructions by selecting instruction sequences having occurrence frequencies higher than a predetermined value on the basis of the instruction sequence occurrence frequency data 503 and then generate the compressed/executable instruction correspondence table 7 indicative of the correspondence between the compressed instructions as defined with reference to the instruction sequence pattern templates 3 and the sequences of executable instructions corresponding to the compressed instructions.

[0206] FIG. 17 shows an example of the instruction sequence pattern templates 3. The instruction sequence pattern template supports up to three compressed instructions compatible with the instruction pattern as illustrated and corresponding to instruction sequences each composed of two executable instructions.

[0207] FIG. 18 illustrates examples of an assembler source file 203 and instruction sequence occurrence frequency data corresponding to the executable object code 2. When searching the instruction sequences as illustrated in FIG. 17, i.e., the instruction sequences having up to two operands, among from the instruction sequences contained in the assembler source file 201, the instruction sequence occurrence frequency data 503 as illustrated in FIG. 18 is obtained.

[0208] In this case, “the compression of the instruction sequence composed of two executable instructions” is for example such that the instruction on the first line of

[0209] sll r4, r4, 16

[0210] and the instruction on the first line of

[0211] lw r7, 0(r4)

[0212] constitutes the instruction sequence of

[0213] sll r4, r4, 16

[0214] lw r7, 0(r4)

[0215] which is compressed.

[0216] Also, “the instruction sequence having up to two operands” is for example such that the instruction sequence composed of the instruction on the first line and the instruction on the second line, i.e.,

[0217] sll r4, r4, 16

[0218] lw r7, 0(r4)

[0219] has two operands of r4 and r7 so that it is an instruction sequence of this kind. However, the instruction sequence composed of the instruction on the second line and the instruction on the third line, i.e.,

[0220] lw r7,0(r4)

[0221] lw r3,0(r5)

[0222] has four operands of r3, r4, r5 and r7 so that it is not an instruction sequence of this kind.

[0223] The candidates of the instruction sequences for definition of compressed instructions are selected on the basis of the instruction sequence occurrence frequency data in order to generate the compressed/executable instruction correspondence table 7 as illustrated in FIG. 13.

[0224] The object conversion unit 8 serves to generate the executable object code 112 as compressed by referring to the compressed/executable instruction correspondence table 7 generated by the compressed instruction definition unit 6 and converting the sequences of executable instructions to be compressed into the corresponding compressed instructions. The object conversion unit 8 also serves to store the executable object code 112 as compressed in the main memory 101.

[0225] The executable instruction extracting unit reconfiguration unit 9 serves to reconfigure the executable instruction extracting unit 14 in order that the compressed instructions as defined are extended into the corresponding executable instructions with reference to the compressed/executable instruction correspondence table 7 generated by the compressed instruction definition unit 6.

[0226] In the case that the executable instruction extracting unit 14 is implemented by an FPGA, the executable instruction extracting unit reconfiguration unit 9 corresponds to the configurator of the FPGA while in the case that the executable instruction extracting unit 14 is defined in terms of a description of HDL, the executable instruction extracting unit reconfiguration unit 9 is implemented by a conversion filter which converts the description to an HDL description corresponding to the compressed/executable instruction correspondence table 7. Also, the executable instruction extracting unit reconfiguration unit 9 serves to delete the compressed instructions previously implemented from the executable instruction extracting unit 14.

[0227] In this configuration, the instruction sequence as registered in the instruction sequence pattern template 3 are detected in the executable object code 2 which runs in the processor 151. The instruction sequences as detected are selectively defined as compressed instructions in accordance with the occurrence frequencies thereof. The compressed/executable instruction correspondence table 7 is generated by the compressed instruction definition unit 6 on the basis of the compressed instructions as defined and the corresponding sequence of executable instructions. On the basis of the compressed/executable instruction correspondence table 7 as generated, the executable instruction extracting unit 14 is reconfigured by means of the executable instruction extracting unit reconfiguration unit 9. Also, on the basis of the compressed/executable instruction correspondence table 7, the sequences of executable instructions within the executable object code 2 is converted into the corresponding the compressed instructions as defined in order to generate the executable object code 112 as compressed, which is then stored in the main memory 101. The executable object code 112 stored in the main memory 101 are extended into the corresponding executable instructions, which are sequentially decoded by the instruction decoding unit 12 for execution. On the other hand, when other executable object code than the previous executable object code is to run, the executable instruction extracting unit 14 is reconfigured by the executable instruction extracting unit reconfiguration unit 9 after defining the compressed instruction in the same manner as explained above, and then the new executable object code 112 as compressed is run.

[0228] In this manner, in accordance with the fourth embodiment, the compressed instructions can be optimally defined for the respective target program running on the same processor so that the number of the constituent instructions can be suppressed, resulting in compaction of the memory 101 for storing the target program.

[0229] [Embodiment 5]

[0230] Next, a fifth embodiment of the present invention will be explained. FIG. 19 shows a block diagram showing an information processing apparatus in accordance with the fifth embodiment.

[0231] In contrast to the information processing apparatus as illustrated in FIG. 16, the apparatus as illustrated in FIG. 19 is characterized in that the target program for running on the processor 1 is defined and given in the form of the assembler source file 202 as illustrated in FIG. 20A rather than executable object code and that an object code generation unit 21 is provided in place of the object conversion unit 8 as illustrated in FIG. 16 in order to convert the sequence of executable instructions contained in the assembler source file to the corresponding compressed instruction on the basis of the compressed/executable instruction correspondence table 7 while the instruction execution unit 22 functions also as the executable instruction extracting unit reconfiguration unit 9 as illustrated in FIG. 16 for reconfiguring the executable instruction extracting unit 14 with reference to the compressed/executable instruction correspondence table 7. While the other constituents elements have the same structures and functions of the previous embodiment, detailed explanation is not repeated.

[0232] FIG. 21 illustrates an example of the instruction sequence occurrence frequency of the assembler source file 202. The compressed/executable instruction correspondence table 7 generated on the basis of the instruction sequence occurrence frequency data 5 is, for example, as illustrated in FIG. 22A on the basis of which the assembler source file is converted in order to include the compressed instructions as defined.

[0233] In this manner, the present invention is not depending upon the representation of the original instruction code and whether or not the executable instruction extracting unit reconfiguration unit 9 is implemented inside or outside of the processor.

[0234] Also in accordance with this embodiment of this design, there are similar advantages as in the fourth embodiment.