US 6,587,863 B1Grant

Multiphase, interleaved direct digital synthesis methods and structures

Issue Date:2003-07-01

•25 Claims

•5 Drawing Sheets

Abstract

Direct digital synthesis (DDS) methods and structures are provided that increase DDS output frequencies f_outwithout requiring a corresponding increase in the rate f_clkat which DDS structures must operate. An exemplary method generates a periodic stream of digital words at a clock frequency f_clkwherein the words represent respective amplitudes of a predetermined periodic waveform, the periodic stream has a period P and the digital words are spaced by a phase step φ_s. This method comprises the steps of a) with a count capacity C, counting modulo nφ_sat a reduced clock frequency (1/n)f_clkto thereby generate a primary substream of digital words, b) phase offsetting the primary substream to form n−1 secondary substreams of digital words wherein the primary and secondary substreams are phase spaced by the phase step φ_s, c) converting the digital words of each of the primary, and secondary substreams to converted digital words that represent respective amplitudes of the predetermined waveform, and d) interleaving the primary and secondary substreams to thereby form the periodic stream of digital words that occur at the clock frequency f_clk.

Metadata

Assignee

Analog Devices, Inc.

Inventors

Ken Gentile
John Kornblum

Application Information

Application Number:US 09/605,099

Filing Date:2000-06-27

Priority Date:2000-06-27

Art Unit:7

Classifications

IPC:

G06F 102

Field of Search:

708651

Patent Drawings (5 sheets)

Description

Background of the Invention

[0002] 1. Field of the Invention

[0003] The present invention relates generally to direct digital synthesis.

[0004] 2. Description of the Related Art

[0005] Direct digital synthesis (DDS) utilizes digital processing to generate output signals whose stability is referenced to a precision clock and whose frequency and phase are tunable. An exemplary conventional DDS generator 20 is shown in FIG. 1A. It includes a phase accumulator 22 and a phase-to-amplitude (φ-A) converter 24 that both receive a clock signal f_clkfrom a system clock 25.

[0006] The phase accumulator 22 is basically a modulo φ_sdigital N-bit counter that counts at a rate f_clkwherein φ_sis a phase step that is provided to the phase accumulator at a generator port 26. Accordingly, the phase accumulator delivers a periodic stream of digital works over a circuit path 27 to the φ-A converter 24.

[0007] This operation can be illustrated with reference to a digital phase wheel 30 of FIG. 1B. As exemplified by successive radial rays 31A, 31B, 31C, 31D and 31E in this wheel, the phase accumulator repetitively counts around the wheel perimeter 32 (e.g., from an initial N-bit digital word 0000 . . . 0 to a final N-bit digital word 1111 . . . 1) to form the periodic stream of digital words. As further indicated in association with a process direction arrow 33, the N-bit phase accumulator 22 of FIG. 1A has a word capacity C=2^Nso that it generates a periodic stream of digital words over the circuit path 27 with a period P=C/(φ_sf_clk). Stated differently, the phase accumulator 22 places digital words on the circuit path 27 at a rate of f_clkand the periodic stream of words repeats at an output frequency of f_out=(φ_sf_clk)/C.

[0008] FIG. 1B appears to indicate that the phase step φ_smoves only between adjacent digital words 34. It should be understood, however, that FIG. 1B would need to show 268,435,456 digital words along its perimeter 32 to completely illustrate the operation of an exemplary 28-bit phase accumulator. Because of illustrative limits, such word density cannot be shown in the figures and, accordingly, the enlarged view of FIG. 1C indicates that additional words 36 may be located between each adjacent pair of the words 34 of FIG. 1B—the number of the additional words being a function of the size of the selected phase step φ_s.

[0009] The periodic stream of digital words on the circuit path 27 of FIG. 1A includes a repetitive sequence from 000 . . . 0 to 111 . . . 1. This sequence expresses a linear relationship and, accordingly, a periodic analog ramp would be generated if the periodic stream were fed directly to a digital-to-analog converter (DAC). Therefore, the DDS generator 20 includes a φ-A converter 24 which converts the digital words at respective phase locations to converted digital words at the generator output port 28 wherein the converted digital words represent respective amplitudes of any predetermined waveform (e.g., a sinusoidal waveform). A DDS synthesizer may then be realized by coupling a DAC to the generator output port 28.

[0010] When compared to other waveform synthesis techniques (e.g., phase-locked loop synthesis), DDS offers a number of attractive features which include:

[0011] a) extremely fine tuning resolution of the output frequency f_out,

[0012] b) fast change of output phase and fast phase-continuous change of output frequency f_out;

[0013] c) generation of multiple phase-related periodic streams,

[0014] d) performance that is not affected by component changes (due, for example, to aging and temperature),

[0015] e) remote control (e.g., by digital processors), and

[0016] f) integrated structure on a single chip (including an output DAC).

[0017] It is apparent that the output frequency f_outof the DDS generator 20 can only be increased with a corresponding increase in the rate f_clkat which the phase accumulator 22 and φ-A converter 24 operate. This rate, however, is limited by the DDS generator's fabrication process. Complementary metal-oxide semiconductor (CMOS) processes, for example, are characterized by the minimum gate length (e.g., 0.25 microns) they can achieve and this gate length sets an upper bound on the operating rate of devices fabricated with the process.

[0018] In addition to this absolute limit, attempts to increase the operating rate f_clkface other problems such as higher current slew rates, tighter timing requirements and the need for more extensive signal pipelining. As a result, circuit complexity and power dissipation are increased and larger device geometries are required. It is apparent, therefore, that substantial benefits would be realized with methods and structures that increased DDS output frequencies f_outwithout requiring a corresponding increase in the operating rate f_clk.

Summary of the Invention

[0019] The present invention is directed to DDS methods and structures that increase DDS output frequencies f_outwithout requiring a corresponding increase in the rate f_clkat which DDS structures must operate.

[0020] An exemplary method of the invention generates a periodic stream of digital words at a clock frequency f_clkwherein the words represent respective amplitudes of a predetermined periodic waveform, the periodic stream has a period P and the digital words are spaced by a phase step φ_s. The method comprises the steps of:

[0021] a) with a count capacity C, counting modulo nφ_sat a reduced clock frequency (1/n)f_clkto thereby generate a primary substream of digital words;

[0022] b) phase offsetting the primary substream to form n−1 secondary substreams of digital words wherein the primary and secondary substreams are phase spaced by the phase step φ_s;

[0023] c) converting the digital words of each of the primary and secondary substreams to converted digital words that represent respective amplitudes of the predetermined waveform; and

[0024] d) interleaving the primary and secondary substreams to thereby form the periodic stream of digital words that occur at the clock frequency f_clk.

[0025] These process steps can be practiced with any integer n and they form a multiphase, interleaved method that generates a periodic stream of digital words that occur at a clock frequency f_clkbut realizes this stream with counting, offsetting and converting processes that are realized at a substantially reduced frequency (1/n)f_clk. Therefore, significant improvements in DDS operational parameters (e.g., decrease of current slew rates, decrease of data pipelining, reduced circuit complexity and power dissipation and smaller device geometries) are realized.

[0026] DDS generator and synthesizer embodiments are also provided for practicing the methods of the invention.

[0027] The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0028] FIG. 1A is a block diagram of a conventional DDS generator;

[0029] FIG. 1B is a digital phase wheel diagram that illustrates functional methods of the conventional DDS generator of FIG. 1A;

[0030] FIG. 1C is an enlarged view of elements within the curved line 1C in FIG. 1B;

[0031] FIG. 2A is a digital phase wheel diagram that illustrates a DDS method embodiment of the present invention;

[0032] FIG. 2B is an enlarged view of elements within the curved line 2B in FIG. 2A;

[0033] FIG. 3 is a flow chart that shows process steps of the invention that are exemplarized by the digital phase wheel diagram of FIG. 2A;

[0034] FIG. 4 is a block diagram of a DDS synthesizer embodiment of the invention for practicing the processes of FIG. 4; and

[0035] FIG. 5 is a block diagram of an offset generator embodiment in the DDS synthesizer of FIG. 3.

Detailed Description of the Preferred Embodiments

[0036] The flow chart 40 of FIG. 3 recites DDS process steps of the present invention which increase DDS output frequencies f_outwithout requiring a corresponding increase in the rate f_clkat which important DDS structures must operate. To facilitate a description of these steps, reference will be made to FIGS. 2A and 2B which have elements similar to those of FIGS. 1B and 1C and, accordingly, like elements of these figures are indicated by like reference numbers.

[0037] In particular, the flow chart 40 is directed to a method for generating, a periodic stream of digital words that occur at a clock frequency f_clkand represent respective amplitudes of a predetermined periodic waveform wherein the periodic stream has a period P and the digital words are spaced by a phase step φ_s.

[0038] The first process step 42 utilizes a count capacity C to count modulo nφ_sat a reduced clock frequency (1/n)f_clkto thereby generate a primary substream of digital words. Although the processes of the invention may be practiced with any integer n, FIGS. 2A and 2B illustrate an exemplary n of 4. Thus, FIG. 2A shows an exemplary phase step 4φ_sas indicated by successive radial rays 31A and 31E.

[0039] In process step 43, the primary substream is phase offset to form n−1 secondary substreams of digital words wherein the primary and secondary substreams are phase spaced by the phase step φ_s. This step is illustrated in FIG. 2A by three (n−1) successive radial rays 31B, 31C and 31D which are arranged so that they and the radial ray 31A are spaced by the phase step φ_s.

[0040] It is noted at this point that the secondary substreams are not generated by counting as is the primary substream but, rather, are formed by being offset from the primary substream. This is indicated by FIG. 2B which also illustrates the generated radial ray 31A and the successively offset radial rays 31B, 31C and 31D and further illustrates additional digital words 36 that may lie between the digital words 34 that correspond to these radial rays.

[0041] The digital words of each of the primary and secondary substreams are converted in process step 44 of FIG. 3 to converted digital words that represent respective amplitudes of the predetermined periodic waveform (the phrases “digital words” and “converted digital words” are used herein to clearly differentiate words before and after the conversion of process step 44). Finally, the primary and secondary substreams are time interleaved in process step 45 to thereby form the desired periodic stream of digital words that occur at the clock frequency f_clk.

[0042] It is apparent that the process steps of FIG. 3 generate a periodic stream of digital words that occur at a clock frequency f_clkbut realizes this stream with counting, offsetting and converting processes (processes 42-44 of FIG. 3) that can be realized at a significantly reduced frequency (1/n)f_clk. In particular, digital words of the primary substream are provided by counting at the reduced rate (1/n)f_clk, the subsequent offsetting step is performed on each digital word and is therefore also performed at the reduced rate (1/n)f_clkand, the converting step is performed separately on each of the primary and secondary substreams of digital words and thus also proceeds at the reduced rate (1/n)f_clk.

[0043] Because the speed at which the process steps of FIG. 3 operate is reduced by 1/n (e.g., by ¼ or by ⅛), significant improvements of many DDS parameters (e.g., decreased current slew rates, decreased data pipelining, reduced circuit complexity and power dissipation and smaller device geometries) may be realized.

[0044] The process steps 42-45 of FIG. 3 facilitate the DDS generation of a periodic stream of digital words. This stream may then be converted into a periodic waveform by the process 48 of FIG. 3 which converts the converted digital words to analog signals that have the respective amplitudes (of step 44). The step 48 is shown in broken lines to indicate that it is an addition to the steps 42-45 that generate a periodic stream of digital words.

[0045] The processes illustrated by FIG. 3 may be practiced with the DDS synthesizer 60 of FIG. 4. The synthesizer 60 includes a phase step latch 62, a DDS generator 64, a DAC 66 and timing and control 68. The latter module provides a phase step update command to the phase step latch 62, a DDS clock (1/n)f_clkto the DDS generator 64 and a system clock f_clkto the DAC 66 and to a multiplexer (MUX) 69 of the DDS generator 64.

[0046] The DDS synthesizer 60 has an input port 70 that is coupled to the latch 62 and an output port 72 that is coupled to the DAC 66. In addition to the mulitplexer 69, the DDS generator 64 includes a multiplier 74, a phase accumulator 76 and a φ-A converter 78 that are serially coupled between the latch 62 and the multiplexer 69. The output of the latch 62 is coupled through a time delay 79 to an offset generator 80 which also receives an input from the phase accumulator 76. Offset signals of the offset generator are coupled through additional φ-A converters 82, 84 and 86 to the multiplexer 69.

[0047] In operation of the DDS synthesizer 60, the value of the phase step φ_sat the input port 70 determines the quantization resolution in an analog waveform that will be synthesized at the output port 72. Once the phase step φ_shas been selected, it is latched to the DDS generator 64 by the phase step update command (from the timing and control 68) and is multiplied by an integer n in a multiplier 74 to thereby apply a phase step nφ_sto the phase accumulator 76. The DDS clock (1/n)f_clkand the system clock f_clkare related by the same integer n. Although the invention can be practiced with any integer n (e.g., 8), the exemplary DDS architecture of FIG. 4 is shown for a selected value of 4 (the selection of n is indicated by selection arrow 87 in the upper left of FIG. 4).

[0048] Because n has been selected to be 4, the multiplier 74 applies a phase step 4φ_sto the phase accumulator 76. Accordingly, the phase accumulator counts modulo 4φ_sto generate a periodic primary substream of digital words as recited in process step 42 of FIG. 3 and illustrated in FIG. 2A. The primary substream of digital words is mathematically expressed in FIG. 4 by the expression Σ4φ_sand it is converted to converted digital words that represent respective amplitudes of a predetermined waveform (e.g., a sinusoidal waveform) by the φ-A converter 78. This conversion is in accordance with process step 44 of FIG. 3.

[0049] The phase step φ_sand the primary substream Σ4φ_sare both input to the offset generator 80 which responds by generating n−1 secondary substreams of digital words that are offset from the primary substream Σ4φ_sby phases 1φ_s, 2φ_sand 3φ_s. Thus, the primary and secondary substreams are phase spaced by the phase step φ_sthat is applied to the input port 70. The delay 79 is preferably selected to match delays through the phase accumulator 76 so that the phase step φ_sand the primary substream Σ4φ_sare aligned when received by the offset generator 80.

[0050] In the DDS generator embodiment of FIG. 4, the offset generator 80 is arranged to phase delay the secondary substreams from the primary substream so that they are mathematically expressed in FIG. 4 as Σ4φ_s−1φ_s, Σ4φ_s−2φ_sand Σ4φ_s−3φ_s. This exemplary offset arrangement is the same as that illustrated in the digital phase wheel 30 of FIG. 2A and the offsetting operation of the offset generator 80 is in accordance with process step 43 of FIG. 3. Each of the φ-A converters 82, 84 and 88 convert their respective secondary substream to converted digital words that represent respective amplitudes of the predetermined waveform. This converting operation is recited as process step 44 in FIG. 3.

[0051] The multiplexer 69 then interleaves the primary and secondary substreams at a rate f_clkto form a periodic stream of digital words that are provided to the DAC 66. The interleaving sequence of the multiplexer 69 must be in accordance with the particular offset arrangement of secondary substreams that has been generated by the offset generator 80. It can be seen from the same offset arrangement that is shown in FIG. 2A, that the multiplexer 69 must couple the converter outputs to the DAC 66 in the sequence of φ-A converter 86, φ-A converter 84, φ-A converter 82 and φ-A converter 78 (i.e., the multiplexing must follow the direction arrow 33 in FIG. 2A. This interleaving operation is in accordance with process step 45 of FIG. 3.

[0052] At the rate of the system clock f_clk, the DAC 66 then converts the digital words of the periodic stream to analog signals that have the respective amplitudes that are represented by the digital words. This final operation is in accordance with process step 48 of FIG. 3.

[0053] The phase accumulator 76 and offset generator 80 can be realized in various embodiments. In an exemplary structure, the phase accumulator of FIG. 4 comprises an adder 89 and a latch 90 that responds to the adder. A first input of the adder receives the phase step nφ_sfrom the multiplier 74 and the output of the latch 90 is coupled to a second input of the adder.

[0054] FIG. 5 shows an exemplary embodiment of the offset generator 80 that includes differencers 92, 93 and 94, a multiplier 95 and an adder 96. The phase step φ_s(received from the time delay 79 of FIG. 4) is multiplied by the multiplier 95 to provide a phase 2φ_s. The adder 96 provides a phase 3φ_sin response to the phase step and the multiplier 95. The phases 1φ_s, 2φ_sand 3φ_sare coupled respectively to the differencers 92, 93 and 94 which also receive the primary substream Σ4φ_s(from the phase accumulator 76 of FIG. 4). In response to their inputs, the differencers then generate the secondary substreams Σ4φ_s−1φ_s, Σ4φ_s−2φ_sand Σ4φ_s−3φ_sas shown in FIG. 5.

[0055] The digital phase wheel 30 of FIG. 2A shows that the radial rays 31B, 31C and 31D are spaced by the phase step φ_s, but various successive arrangements that meet this condition can be used in practicing the invention. For example, the secondary substreams can lead the primary substream rather than lag it as indicated by the phase wheel 30. This is achieved in the offset generator 80 of FIG. 5 by replacing each of the differencers 92, 93 and 94 with an adder 97 as indicated by the exemplary replacement arrow 98. Other successive arrangements can be formed, for example, by having at least one secondary substream leading the primary substream and the other secondary substreams lagging the primary substream. The only limitation is that all of the substreams are spaced by the phase step φ_s.

[0056] The DDS generator 64 of FIG. 4 can be advantageously used to construct various useful synthesis structures of which the DDS synthesizer 60 is but one example. Because of the features of the invention, the DDS generator 64 can generate digital words at rates that are extended by an integer n above rates that are limited by the generator's fabrication process.

[0057] This rate extension is enhanced by increasing the integer n but this increases the circuit complexity (e.g., it increases the number of φ-A converters in FIG. 4 and the number of differencers 92, 93 and 94 in FIG. 5) and, slows the rate at which new phase step selections can be latched through the latch 62 of FIG. 4. Circuit simulations have shown, however, that the benefits of the reduced power dissipation (realized particularly in the phase accumulator 76 and φ-A converters 78, 82, 84 and 86) more than outweigh the additional circuit complexity.

[0058] Multipliers of the invention (e.g., multipliers 74 and 95 shown respectively in FIGS. 4 and 5) are configured to perform a multiplier function and may be realized with various conventional structures and functions (e.g., discrete logic elements and bit shifting).

[0059] The multiphase, interleaved teachings of the invention may be practiced with various semiconductor processes. In an exemplary fabrication, for example, the DDS generator 23 of FIG. 4 is realized with CMOS transistors and the multiplexer 29 and DAC 30 are realized with bipolar junction transistors.

[0060] The preferred embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.

Claims

We claim:

1. A method of generating a periodic stream of digital words that occur at a clock frequency f_clkand represent respective amplitudes of a predetermined periodic waveform wherein said periodic stream has a period P and said digital words are spaced by a phase step φ_sthat is a portion of said period, the method comprising the steps of:

with a count capacity C, counting modulo nφ_sat a reduced clock frequency (1/n)f_clkto thereby generate a primary substream of digital words;

phase offsetting said primary substream to form n−1 secondary substreams of digital words wherein said primary and secondary substreams are phase spaced by said phase step φ_s;

converting the digital words of each of said primary and secondary substreams to converted digital words that represent respective amplitudes of said predetermined waveform; and

interleaving said primary and secondary substreams to thereby form said periodic stream of digital words that occur at said clock frequency f_clk.

2. The method of claim 1, wherein n=4.

3. The method of claim 1, wherein n=8.

4. The method of claim 1, wherein said converting step includes the step of providing, at said reduced clock frequency (1/n)f_clk, said converted digital words from a lookup table.

5. The method of claim 1, wherein said converting step includes the step of generating, at said reduced clock frequency (1/n)f_clk, said converted digital words with a computational engine.

6. The method of claim 1, wherein said predetermined periodic waveform is a sinusoidal waveform.

7. A method of generating a periodic stream of digital words that occur at a clock frequency f_clkand represent respective amplitudes of a predetermined periodic waveform wherein said periodic stream has a period P and said digital words are spaced by a phase step φ_sthat is a portion of said period, the method comprising the steps of:

with a count capacity C, counting modulo nφ_sat a reduced clock frequency (1/n)f_clkto thereby generate a primary substream of digital words; phase offsetting said primary substream to form n−1 secondary substreams of digital words wherein said primary and secondary substreams are phase spaced by said phase step φ_s;

converting the digital words of each of said primary and secondary substreams to converted digital words that represent respective amplitudes of said predetermined waveform; and

interleaving said primary and secondary substreams to thereby form said periodic stream of digital words that occur at said clock frequency f_clk;

wherein said offsetting step includes the steps of:

providing n−1 phase steps kφ_swherein k represents integers from 1 to n−1; and

subtracting said phase steps kφ_sfrom said primary substream to generate said secondary substreams.

8. A method of generating a periodic stream of digital words that occur at a clock frequency fclk and represent respective amplitudes of a predetermined periodic waveform wherein said periodic stream has a period P and said digital words are spaced by a phase φ_sthat is portion of said period, the method comprising the steps of:

with a count capacity C, counting modulo nφ_sat a reduced clock frequency (1/n)f_clkto thereby generate a primary substream of digital words;

phase offsetting said primary substream to form n−1 secondary substreams of digital words wherein said primary and secondary substreams are phase spaced by said phase step φ_s;

converting the digital words of each of said primary and secondary substreams to converted digital words that represent respective amplitudes of said predetermined waveform; and

interleaving said primary and secondary substreams to thereby form said periodic stream of digital words that occur at said clock frequency f_clk;

wherein said offsetting step includes the steps of:

providing n−1 phase steps kφ_swherein k represents integers from 1 to n−1; and

adding said phase steps kφ_sto said primary substream to generate said secondary substreams.

9. A method of generating a periodic stream of digital words that occur at a clock frequency f_clkand represent respective amplitudes of a predetermined periodic waveform wherein said periodic stream has a period P and said digital words are spaced by a phase step φ_sthat is a portion of said period, the method comprising the steps of:

with a count capacity C, counting modulo nφ_sat a reduced clock frequency (1/n)f_clkto thereby generate a primary substream of digital words;

phase offsetting said primary substream to form n−1 secondary substreams of digital words wherein said primary and secondary substreams are phase spaced by said phase step φ_s;

converting the digital words of each of said primary and secondary substreams to converted digital words that represent respective amplitudes of said predetermined waveform; and

interleaving said primary and secondary substreams to thereby form said periodic stream of digital words that occur at said clock frequency f_clk;

wherein said interleaving step includes the step of multiplexing said primary and secondary streams at said clock frequency f_clk.

10. A method of generating a periodic waveform that has a period P and is quantized in a phase step φ_sthat occurs at a clock frequency f_clk, the method comprising the steps of:

with a count of capacity C, counting modulo nφ_sat a reduced clock frequency (1/n)f_clkto thereby generate a primary substream of digital words;

phase offsetting said primary substream to form n−1 secondary substreams of digital words wherein said primary and secondary substreams are phase spaced by said phase step φ_s;

converting the digital words of each of said primary and secondary substreams to converted digital words that represent respective amplitudes of said periodic waveform;

interleaving said primary and secondary substreams to thereby form a periodic stream of converted digital words that occur at said clock frequency f_clk; and

converting said converted digital words to analog signals, that have said respective amplitudes to thereby form said periodic waveform.

11. The method of claim 10, wherein n=4.

12. The method of claim 10, wherein n=8.

13. The method of claim 10, wherein said converting step includes the step of providing, at said reduced clock frequency (1/n)f_clk, said converted digital words from a lookup table.

14. The method of claim 10, wherein said interleaving step includes the step of multiplexing said primary and secondary streams at said clock frequency f_clk.

15. The method of claim 10, further including the step of performing said converting step with a digital-to-analog converter.

16. A method of generating a periodic waveform that has a period P and is quantized in a phase step φ_sthat occurs at a clock frequency f_clkthe method comprising the steps of:

with a count of capacity C, counting modulo nφ_sat a reduced clock frequency (1/n)f_clkto thereby generate a primary substream of digital words;

phase offsetting said primary substream to form n−1 secondary substreams of digital words wherein said primary and secondary substreams are phase spaced by said phase step φ_s;

converting the digital words of each of said primary and secondary substreams to converted digital words that represent respective amplitudes of said periodic waveform;

interleaving said primary and secondary substreams to thereby form a periodic stream of converted digital words that occur at said clock frequency f_clk; and

converting said converted digital words to analog signals that have said respective amplitudes to thereby form said periodic waveform;

wherein said offsetting step includes the steps of:

providing n−1 phase steps kφ_swherein k represents integers from 1 to n−1; and

subtracting said phase steps kφ_sfrom said primary substream to generate said secondary substreams.

17. A method of generating a periodic waveform that has a period P and is quantized in a phase step φ_sthat occurs at a clock frequency f_clk, the method comprising the steps of:

with a count of capacity C, counting modulo nφ_sat a reduced clock frequency (1/n)f_clkto thereby generate a primary substream of digital words;

phase offsetting said primary substream to form n−1 secondary substreams of digital words wherein said primary and secondary substreams are phase spaced by said phase step φ_s;

converting the digital words of each of said primary and secondary substreams to converted digital words that represent respective amplitudes of said periodic waveform;

interleaving said primary and secondary substreams to thereby form a periodic stream of converted digital words that occur at said clock frequency f_clk; and

converting said converted digital words to analog signals that have said respective amplitudes to thereby form said periodic waveform;

wherein said offsetting step includes the steps of:

providing n−1 phase steps kφ_swherein k represents integers from 1 to n−1; and

adding said phase steps kφ_sto said primary substream to generate said secondary substreams.

18. A method of generating a periodic waveform that has a period P and is quantized in a phase step φ_sthat occurs at a clock frequency f_clk, the method comprising the steps of:

with a count of capacity C, counting modulo nφ_sat a reduced clock frequency (1/n)f_clkto thereby generate a primary substream of digital words;

phase offsetting said primary substream to form n−1 secondary substreams of digital words wherein said primary and secondary substreams are phase spaced by said phase step φ_s;

converting the digital words of each of said primary and secondary substreams to converted digital words that represent respective amplitudes of said periodic waveform;

interleaving said primary and secondary substreams to thereby form a periodic stream of converted digital words that occur at said clock frequency f_clk; and

converting said converted digital words to analog signals that have said respective amplitudes to thereby form said periodic waveform;

wherein said periodic waveform is a sinusoidal waveform.

19. A generator that generates a periodic stream of digital words that occur at a clock frequency f_clkand represent respective amplitudes of a predetermined periodic waveform wherein said periodic stream has a period P and said digital words are spaced by a phase step φ_sthat is a portion of said period, the generator comprising:

a phase accumulator that generates, at a reduced clock frequency (1/n)f_clk, a primary substream of digital words wherein said primary substream has said period P and said digital words are spaced by a phase step nφ_s;

an offset generator that offsets said primary substream to thereby generate n−1 secondary substreams of digital words wherein said primary and secondary substreams are phase spaced by said phase step φ_s;

n phase-to-amplitude converters that each convert a respective one of said primary and secondary substreams to converted digital words that represent respective amplitudes of said periodic waveform; and

a multiplexer that interleaves said primary and secondary substreams to thereby form said periodic stream of digital words that occur at said clock frequency f_clk.

20. The generator of claim 19, wherein said phase accumulator includes:

an adder having first and second input ports; and

a latch that responds to said adder and has an output port coupled to said second input port;

said latch thus providing said primary substream at said output port when said phase step nφ_sis coupled to said first input port.

21. The generator of claim 19, wherein each of said phase-to-amplitude converters comprises a memory having a stored lookup table.

22. The generator of claim 19, wherein each of said phase-to-amplitude converters comprises a computational engine.

23. A generator that generates a periodic stream of digital words that occur at a clock frequency f_clkand represent respective amplitudes of a predetermined periodic waveform wherein said periodic stream has a period P and said digital words are spaced by a phase step φ_sthat is a portion of said period, the generator comprising:

a multiplexer that interleaves said primary and secondary substreams to thereby form said periodic stream of digital words that occur at said clock frequency f_clk;

wherein said offset generator includes:

a phase-step generator that provides n−1 phase steps kφ_swherein k represents integers from 1 to n−1; and

n−1 differencers that generate said n−1 secondary substreams in response to said primary substream and said n−1 phase step kφ_s.

24. A generator that generates a periodic stream of digital words that occur at a clock frequency f_clkand represent respective amplitudes of a predetermined periodic waveform wherein said periodic stream has a period P and said digital words are spaced by a phase step φ_sthat is a portion of said period, the generator comprising:

a multiplexer that interleaves said primary and secondary substreams to thereby form said periodic stream of digital words that occur at said clock frequency f_clk;

wherein said offset generator includes:

a phase-step generator that provides n−1 phase steps kφ_swherein k represents integers from 1 to n−1; and

n−1 adders that generate said n−1 secondary substreams in response to said primary substream and said n−1 phase steps kφ_s.

25. A synthesizer that generates a periodic waveform that has a period P and is quantized with a phase step φ_sat a clock frequency f_clk, the synthesizer comprising:

n phase-to-amplitude converters that each convert a respective one of said primary and secondary substreams to converted digital words that represent respective amplitudes of said periodic waveform;

a multiplexer that interleaves said primary and secondary substreams to thereby form a periodic stream of digital words that occur at said clock frequency f_clk; and

a digital-to-analog converter that generates said periodic waveform in response to said periodic stream of digital words.

Patent Citations (12)

Patent	Date	Inventor	Cited By
US4992743(A)	1991-02-01	Sheffer	Examiner
US5371765(A)	1994-12-01	Guilford	Examiner
US5430764(A)	1995-07-01	Chren, Jr.	Examiner
US5467294(A)	1995-11-01	Hu et al.	Applicant
US5519343(A)	1996-05-01	Britz	Applicant
US5598437(A)	1997-01-01	Gourse	Examiner
US5673212(A)	1997-09-01	Hansen	Applicant
US5761101(A)	1998-06-01	Erhage	Examiner
US5905388(A)	1999-05-01	Van Der Valk et al.	Examiner
US5999581(A)	1999-12-01	Bellaouar et al.	Examiner
US6005419(A)	1999-12-01	Rudish	Examiner
US6060917(A)	2000-05-01	Saul	Examiner

Non-Patent Literature (3)

Amir Sodagar et al., aplitude Conversion in Sine-Output Direct Digital Frequency Synthesizers, 2000, IEEE, pp. 515-518.Applicant
Stane Ciglarie et al., Special Considerations for Alternatively Designed Digital Phase Angle Standard, 1998, IEEE Transactions on Instrumentation and Measurement vol. 47 No. 1, pp. 199-203.Applicant
Synthesizer Data Book, pp. 39-48 and 83-88, Qualcom Incorporated, San Diego, California, 92121.Applicant

Abstract