Symbol sampling time settlement of a hard decision radio receiver

[0002] The present invention relates in general to the telecommunications field and, in particular, to a method and apparatus for improving bit error performance within a hard decision radio interface processing environment.

[0003] Economic feasibility of wireless links between portable devices and their associated accessories require implementation of low-power, low-cost equipment. Many existing portable devices use infrared links to meet this requirement. Although infrared transceivers are inexpensive, they have limited range, are sensitive to direction, and can generally only be used between two devices. By contrast, radio transceivers have a much greater range, can propagate around objects and connect to many devices simultaneously.

[0004] Many radio transceivers use hard decision type radio receivers. A radio receiver is said to use hard decisions when the size of the channel alphabet (i.e., the number of possible signals that can be transmitted) equals the size of the demodulator output alphabet (i.e., the number of possible output signals from the radio demodulator).

[0005] For instance, the Bluetooth system uses a binary signal alphabet for which the channel symbol duration time is T=10⁻⁶seconds (sec). The output of a radio receiver implementation for that system might be discrete in amplitude, but continuous in time. Consequently, a switch between the two possible amplitudes can take place at any instant of time. As such, the Bluetooth receiver is a hard decision receiver.

[0006] In general, the baseband processing in any binary digital communication system requires a bit stream rate of 1/T bits/sec. Therefore, the output of the time continuous demodulator needs to be converted to a discrete time sequence. However, a significant design problem is to determine the correct sampling time or phase of the discrete time sequence. Baseband processing performance for each module in a Bluetooth system depends on how well a receiver can attain an accurate timing synchronization with the transmitter of the information sequence. An inferior timing synchronization will severely degrade the bit error rate (BER) performance of a receiver within a Bluetooth system. Additionally, to avoid the loss of information at the beginning of the information bit stream which will further degrade the BER performance of the receiver, an accurate timing synchronization needs to be attained within a relatively short period of time.

[0007] Referring to FIG. 1, an eye-diagram 50 of a received signal is plotted to illustrate the problem of choosing a correct sampling time or phase within a hard decision radio interface processing environment. The eye-diagram 50 represents a time before the hard decisions have been performed (in order to clarify the issue). As illustrated, all points above zero represent a “+1”, while all points below zero represent a “−1”. The horizontal axis 51 represents the duration of one channel symbol and the four vertical bars 52-55 represent four possible sampling phases. Clearly, in this example, the best phase to choose is the second sampling phase 53 since it more or less is positioned in the middle of the eye opening. If the first sampling phase 52 or third sampling phase 54 is chosen, the result would be a decreased tolerance to noise and timing shifts between transmitter and receiver. Obviously, the fourth sampling phase 55 is a bad choice and should be avoided.

[0008] Referring to FIG. 2, each channel within a Bluetooth system is divided into 625 microsecond intervals or slots 30. One packet 34 of information can be transmitted per slot 30. Each packet 34 includes an access code 31, a header 32 and a payload 33. The access code 31 can be used for packet identification, synchronization and compensation for offsets.

[0009] FIG. 3 illustrates a radio 70 and correlator 74 which can be used for timing synchronization within a Bluetooth system. In this example, there are four possible phase values that should be checked, thus, the following discussion is in terms of establishing and comparing four phase samplings. Timing synchronization is accomplished by oversampling the demodulator output four times, i.e., f=1/T_s=4/T, where f is the sampling frequency and T_sis the sampling time. Subsequently, the oversampled binary sequence is correlated with a known access code which precedes the actual data. Generally, the known access code is also a binary sequence. For soft decision type receivers, the correct phase choice would be the phase that generates a maximum correlation with the known binary sequence. Unfortunately, hard decision type receivers make the task of finding the correct sampling phase more difficult than if a soft decision would have been available. Given hard values, there is potentially more than one phase that results in maximum correlation. Additional details of the sample selection process are described below.

[0010] The blocks 75 depicted in FIG. 3 represent memory elements in a shift register 72. For each phase sample, the contents of the shift register 72 is shifted one step to the right. Thus, the shift register 72 contains four sampling sequences of the received bit stream. An additional register 71 contains the known sequence with which the four sampling sequences are correlated. A correlation value or correlator output 76 is determined by the correlator 74 for each sample and compared with a threshold value by means of a threshold comparator 77. The threshold comparator 77 can be part of the correlator 74 or a separate process or device.

[0011] In a straight-forward implementation, the correlator output exceeds a predetermined threshold value, the timing is assumed to be correct and the phase of the sample values that caused the correlator trigger is used as a reference for the sampling time of the remaining part of the packet 34 (FIG. 2). Generally this approach works because the access code words are carefully chosen in a way that ensures good autocorrelation results. In other words, for all reasonable threshold values, the correlator output is unlikely to trigger unless the entire access code is within the correlator window. Thus, the phase that generates the first trigger output (binary representation of an indication that the correlator output 76 exceeds the preset threshold value) is chosen, unless a better value is found within a few sampling intervals. However, this type of phase decision within a hard decision radio interface processing environment is not optimal because the chosen phase value may be closer to the beginning of the eye rather than in the middle of the eye (FIG. 1). An erroneous choice of a sampling phase causes a receiver to be more sensitive to thermal noise and other interference from radio sources in the used frequency band. Consequently, an erroneous choice leads to degraded BER performance.

[0012] The Bluetooth system is only one example of a wireless system which uses a hard decision radio interface processing environment. The present invention relates to all digital radio interface processing environments which use hard decision decoding.

[0013] In accordance with a preferred embodiment of the present invention, a method and apparatus for improving bit error performance within a hard decision radio interface processing environment is provided, whereby a sampling unit samples an input signal to generate a sampling stream, and a correlator computes the correlation between the generated sample stream and a predetermined bit sequence. The correlation values are fed into a threshold comparator utilizing a variable threshold, and a phase decision unit determines the optimum sampling phase from the resultant threshold comparator values.

[0014] An important technical advantage of the present invention is that a method and apparatus for improving bit error performance within a hard decision radio interface processing environment is provided, whereby baseband processing of the receiver attains accurate timing synchronization with the transmission of the information sequence.

[0015] Another important technical advantage of the present invention is that a method and system for improving bit error performance within a hard decision radio interface processing environment is provided, whereby the required signal-to-noise ratio of the receiver is reduced.

[0016] Another important technical advantage of the present invention is that a method and apparatus is provided which adapts to a better channel by updating the comparator threshold value and thereby decreasing the probability of a false alarm.

[0017] Still another important technical advantage of the present invention is that the behavior of the receiver can be modified by changing the contents of a phase decision table.

[0018] A more complete understanding of the method and system of the present invention will be had by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein:

[0019] FIG. 1 is an eye diagram of a radio receiver output before making a hard decision;

[0020] FIG. 2 is a block diagram of a Bluetooth packet illustrating an access code structure;

[0021] FIG. 3 is a block diagram illustrating a time synchronization circuit;

[0022] FIG. 4 is a block diagram of a modified time synchronization circuit which can be implemented in accordance with a preferred embodiment of the present invention;

[0023] FIG. 5 is a table of exemplary phase decision rules which can be implemented in accordance with a preferred embodiment of the present invention; and

[0024] FIG. 6 is a flowchart illustrating a method that can be implemented in accordance with the present invention.

[0025] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, like numerals being used for like and corresponding parts of the various drawings.

[0026] Essentially, in accordance with a preferred embodiment of the present invention, a method and apparatus for improving bit error performance within a hard decision radio interface processing environment is provided, whereby a sampling unit collects a number of samples per channel symbol of an input signal to generate a number of sampling streams, and a correlator computes a correlation value of each of the number of sampling streams with a predetermined bit sequence. The correlation values are fed into a threshold comparator which utilizes a variable threshold value to generate threshold comparator values or trigger output values. By examining a set of trigger output values, a phase decision unit determines the optimum sampling timing or sampling phase.

[0027] Reference is now made to FIG. 4 which shows a block diagram of a modified time synchronization circuit 100 which can be implemented in accordance with a preferred embodiment of the present invention. For this exemplary embodiment, unit 100 includes a memory 181 comprising three cells. Each cell can store one trigger output value 178 (discussed below). In other embodiments in which the number of samples per channel symbol is greater than four, the number of cells in the memory is set equal to the number of samples per channel symbol minus one. Also, these memory cells are adaptable and can be reset.

[0028] For the preferred embodiment, only time instants t which are some multiple k of the sampling time, T_s, are considered (i.e., t=kT_s). For each time instant t, the correlation between the shift register 72 and register 71 is computed. The correlation value is denoted s_k=s(kT_s) The correlation value s_kis coupled to the threshold comparator 177 which compares the correlation value with a variable threshold value y_k.

[0029] The output of the threshold comparator 177 (trigger output value 178) is a binary representation defined by the following equation: $\begin{array}{cc}{x}_k=\{\begin{array}{cc}0& s_k<y_k,\\ 1& \mathrm{otherwise}.\end{array}& \left(1\right)\end{array}$

[0030] The threshold value y_kcan initially be set to any desired value. In the preferred embodiment, a default threshold value, denoted ŷ, is set to y₀=ŷ. Then, for k≧0, the threshold value y_kcan be updated according to the following equation: $\begin{array}{cc}{y}_{k+1}=\{\begin{array}{cc}{s}_k,& s_k>y_k,\\ \hat{y},& \mathrm{decision}\mathrm{on}\mathrm{phase}\mathrm{is}\mathrm{made},\\ y_k,& \mathrm{otherwise}.\end{array}& \left(2\right)\end{array}$

[0031] Consequently, in accordance with equation 2, if a current correlation value s_kexceeds the threshold value y_k, the threshold value y_k+1is updated to the value of the current correlation value s_k, and the subsequent correlation value is compared to the updated threshold value y_k+1. Furthermore, if a phase decision is to be made, the threshold is reset to the default threshold value ŷ. Otherwise, the threshold value remains unchanged for the subsequent comparison. As such, in order to make optimum phase decisions, a plurality of correlation values can be stored in memory 182 (described below).

[0032] Sequential trigger output values are grouped together to define a trigger output state X_k. Assume that x₀=x₋₁=x₋₂=x₋₃=0. Then, at time instant k, the trigger output state X_kis defined by the following equation: $\begin{array}{cc}{X}_k=\{\begin{array}{cc}\left[1,0,0,0\right],& s_k>y_k,\\ \left[x_k,x_{k-1},x_{k-2},x_{k-3}\right],& \mathrm{otherwise}.\end{array}& \left(3\right)\end{array}$

[0033] In accordance with equation 3, in most cases the trigger output state X_kis the current trigger output x_kcombined with the three previous trigger outputs and if the correlator output exceeds the current threshold, the three trigger output memory cells 181 are reset. Initially, X₀=[0,0,0,0] for the preferred embodiment.

[0034] Based on the trigger output state X_k, a decision on phase selection is made by means of a phase decision unit 185. The phase decision unit 185 can be implemented using hardware or software either separately or locally in the comparator 174. For the preferred embodiment, the phase value at sample k, denoted φ_k, is defined as

[0035] φ_k=kmod 4.  (4)

[0036] Reference is now made to FIG. 5 which shows a table of phase decision rules 90 which can be implemented in accordance with a preferred embodiment of the present invention. As shown by the phase decision table 90, the phase decision unit 185 executes no phase decision if the trigger output value corresponding to position x_k−3in the trigger output state X_kis equal to “0”, irrespective of the values in the other positions.

[0037] For a trigger output state X_kcorresponding to [0,0,1,1], the phase decision unit 185 also determines if the corresponding correlation value s_k−4is less than the corresponding correlation value s_k−1(both of which are stored in memory 182). The phase value of φ_k−2is chosen if the correlation value s_k−4is less than the correlation value s_k−1, otherwise the phase value φ_k−3is chosen. A phase decision of φ_k−3is also made for a trigger output state X_kcorresponding to [0,0,0,1].

[0038] In addition, for trigger output states X_kcorresponding to [0,1,0,1], [0,1,1,1], [1,0,0,1], [1,0,1,1] and [1,1,1,1], a phase decision of φ_k−2is made. Finally, for a trigger output state X_kcorresponding to [1,1,0,1], a phase decision of φ_k−1is made. After the phase decision is made, the threshold value y_kis set to the default value ŷ.

[0039] Reference is now made to FIG. 6 which illustrates a method 200 for implementing the preferred embodiment of the present invention. At step 202, a packet type signal is received. At step 204, part of the access code 31 (FIG. 2) or synchronization sequence is sampled a predetermined number of times per channel symbol to generate a corresponding number of sampling sequences with each representing a different phase value. For the preferred embodiment, each channel symbol is sampled four times. At step 206, each of the generated sampling sequences is correlated with a reference sequence to generate a respective correlation value for each of the sampling sequences. At step 208, the respective correlation values are compared with the threshold value y_kto generate respective threshold comparator values or trigger output values x_k. For the preferred embodiment, the trigger output values x_kare binary values.

[0040] The threshold value y_kcan be updated prior to each successive comparison with a subsequent correlation value. More specifically, if a current correlation value s_kexceeds the threshold value y_k, the threshold value y_k+1is updated to the value of the current correlation value s_k, and the subsequent correlation value is compared to the updated threshold value y_k+1. Also, if a phase decision is made, the threshold value is set to a predefined value. Otherwise, the threshold value remains unchanged for the subsequent comparison. At step 210, a phase decision is made based on a trigger output state X_k. The trigger output state X_kis compared with a predetermined set of decision rules to select a sampling phase that agrees with the trigger output state X_kand the determined set of decision rules.

[0041] Although embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.