Semiconductor device for supplying output voltage according to high power supply voltage

[0002] This application is a continuation of application Ser. No. 08/626,104 filed Apr. 3, 1996.

[0003] 1. Field of the Invention

[0004] The present invention relates to a semiconductor device, and more particularly to a semiconductor device which supplies a prescribed output voltage according to a high power supply voltage in response to an internally generated signal.

[0005] 2. Description of the Background Art

[0006] In order to drive a plasma display or the like, a high driving voltage (e.g., 100 V) is required and thus a high voltage semiconductor integrated circuit device (HVIC) is employed. A conventional structure of an output stage incorporated in such an HVIC is shown in FIG. 12. An equivalent circuit of the structure shown in FIG. 12 is the same as that of Embodiment 1 shown in FIG. 2, which will be described later. As shown in FIG. 2, this output stage is formed by a half bridge of an n channel D (Double Diffused) MOS transistor. A pnp bipolar transistor 107, resistor elements 109, 111 and an n channel DMOS transistor 113 in FIG. 2 are not shown in FIG. 12.

[0007] Referring to FIG. 12, an n⁻type epitaxial layer 20 is formed on a p⁻type semiconductor substrate 10. This epitaxial layer 20 is electrically isolated by p⁺type isolating diffused regions 31 to 34 to be divided into island regions IR1, IR3, and IR4.

[0008] An n channel DMOS transistor 101 is formed in island region IR1. The source of this DMOS transistor 101 is formed by n⁺type diffused regions 61 and 62. The drain of DMOS transistor 101 is formed by n type diffused region 81, epitaxial layer 20 and the like. The gate of DMOS transistor 101 is formed on a p type diffused region 51.

[0009] A Zener diode 105 is formed in island region IR3. The anode of Zener diode 105 is formed by a p⁻type diffused region 71. The cathode of Zener diode 105 is formed by an n⁺type diffused region 63.

[0010] An n channel DMOS transistor 103 is formed in island region IR4. The source of DMOS transistor 103 is formed by an n⁺diffused region 64. The drain of DMOS transistor 103 is formed by an n⁺type diffused region 66 and epitaxial layer 20. The gate electrode 93 of DMOS transistor 103 is formed on a p type diffused region 53.

[0011] A high power supply voltage Vdc of, for example, 100 V is supplied externally to this HVIC. In response to the signal generated in HVIC, output voltage Vout is changed between high power supply voltage Vdc and a ground (common) voltage.

[0012] A control signal generated by a logic circuit (not shown) in the HVIC is applied to the gates of DMOS transistors 103 and 113. When DMOS transistor 103 is turned on and DMOS transistor 113 is turned off, gate charge of DMOS transistor 101 is discharged and output terminal 104 is short-circuited to a ground terminal 106 through Zener diode 105, by DMOS transistor 103. As a result, output voltage Vout drops from high power supply voltage Vdc (e.g., 100 V) to ground voltage COM (0 V). Meanwhile, when DMOS transistor 103 is turned off and DMOS transistor 113 is turned on, a voltage is generated between two ends of a resistor element 109 by the power flowing to DMOS transistor 113. Accordingly, a bipolar transistor 107 is turned on so that gate voltage of DMOS transistor 101 is increased, and as a result, DMOS transistor 101 is turned on. Therefore, output voltage Vout is increased from ground voltage COM (0 V) to high power supply voltage Vdc (e.g., 100 V).

[0013] In the above-described conventional structure, there has been a problem that the chip size of this HVIC is made large since the area occupied by Zener diode 105 is large. The increase in the chip size owing to a single Zener diode 105 is small, but an HVIC generally includes many output stages, and thus the increase in the chip size owing to Zener diodes 105 cannot be ignored.

[0014] In addition, since the breakdown voltage of DMOS transistor 103 must be set high, the threshold voltage of DMOS transistor 103 tends to be high. Accordingly, DMOS transistor 103 cannot be turned on sufficiently with the voltage of the logical level. Thus, there has been a problem that on-resistance of DMOS transistor 103 is increased and the dropping rate of output voltage Vout from high power supply voltage Vdc to ground voltage COM is reduced.

[0015] Based upon the foregoing, it is an object of the present invention to provide a semiconductor device having a small size.

[0016] It is another object of the present invention to provide a semiconductor device in which the dropping rate of output voltage is fast.

[0017] According to one aspect of the present invention, a semiconductor device for supplying a prescribed output voltage according to high power supply voltage in response to an internally generated signal includes a first region, a first MOS transistor, a second region, a Zener diode and a second MOS transistor. The first region is formed at a semiconductor substrate. The first MOS transistor is formed at the first region, and has a drain receiving the high power supply voltage and a source supplying the output voltage. The second region is formed at the semiconductor substrate and is electrically isolated from the first region. The Zener diode is formed at the second region and has an anode connected to the source of the first MOS transistor and a cathode connected to the gate of the first MOS transistor. The second MOS transistor is formed at the second region and has a drain connected to the gate of the first MOS transistor and a source which is connected to the ground.

[0018] In this semiconductor device, the Zener diode and the second MOS transistor are formed at the same region so that the area occupied by the Zener diode is reduced. Accordingly, the size of this semiconductor device is made small.

[0019] According to another aspect of the present invention, a semiconductor device for supplying a prescribed output voltage according to a high power supply voltage in response to an internally generated signal includes a first MOS transistor, a bipolar transistor, and a second MOS transistor. The first MOS transistor has a drain receiving a high power supply voltage and a source supplying an output voltage. The bipolar transistor has a base connected to the gate of the first MOS transistor, an emitter connected to the source of the first MOS transistor, and a collector which is connected to the ground. The second MOS transistor has a drain connected to the gate of the first MOS transistor and a source which is connected to the ground.

[0020] In this semiconductor device, the current flowing to the second MOS transistor is amplified by the bipolar transistor so that the dropping rate of the output voltage is made faster. In addition, since the emitter and the base of the bipolar transistor function as a Zener diode, a high power supply voltage is applied between the gate and the source of the first MOS transistor and thus destruction of its gate film is prevented.

[0021] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

[0022] FIG. 1 is a schematic cross sectional view showing a structure of a semiconductor device according to Embodiment 1 of the present invention.

[0023] FIG. 2 shows an equivalent circuit of the semiconductor device of FIG. 1.

[0024] FIG. 3 is a schematic cross sectional view showing a structure of a semiconductor device according to Embodiment 2 of the present invention.

[0025] FIG. 4 shows an equivalent circuit of the semiconductor device of FIG. 3.

[0026] FIG. 5 is a schematic cross sectional view showing a structure of a semiconductor device according to Embodiment 3 of the present invention.

[0027] FIG. 6 shows an equivalent circuit of the semiconductor device of FIG. 5.

[0028] FIG. 7 is a schematic cross sectional view showing a structure of a semiconductor device according to Embodiment 4 of the present invention.

[0029] FIG. 8 is a schematic cross sectional view showing a structure of a semiconductor device according to Embodiment 5 of the present invention.

[0030] FIG. 9 shows an equivalent circuit of a semiconductor device of FIG. 8.

[0031] FIG. 10 is a schematic cross sectional view showing a structure of a semiconductor device according to Embodiment 6 of the present invention.

[0032] FIG. 11 shows an equivalent circuit of the semiconductor device of FIG. 10.

[0033] FIG. 12 is a schematic cross sectional view showing a structure of a conventional semiconductor device.

[0034] Embodiments of the present invention will be described hereinbelow in detail with reference to the figures. In the figures, the same reference characters denote the same or corresponding portions.

[0035] [Embodiment 1]

[0036] FIG. 1 is a schematic cross sectional view showing a structure of a semiconductor device according to Embodiment 1 of the present invention. FIG. 2 shows an equivalent circuit of the structure shown in FIG. 1. However, while an n channel MOS transistor 101, a Zener diode 105, and an n channel MOS transistor 103 in FIG. 2 are also shown in FIG. 1, an npn bipolar transistor 107, resistor elements 109 and 111, and an n channel DMOS transistor 113 are not shown in FIG. 1.

[0037] Referring to FIG. 1, this semiconductor device includes a p⁻type semiconductor substrate 10, an n⁻type epitaxial layer 20 formed on semiconductor substrate 10, n⁺type buried diffused regions 41 and 42 formed at the interface of semiconductor substrate 10 and epitaxial layer 20, p⁺type isolating diffused regions 31 to 33 formed in epitaxial layer 20 to reach semiconductor substrate 10, n type diffused regions 81 to 84 formed in epitaxial layer 20 to reach buried diffused regions 41 and 42, a p⁻type diffused region 71 formed shallower than diffused regions 81 to 84 in epitaxial layer 20, p type diffused regions 51 to 53 formed shallower than diffused region 71 in epitaxial layer 20, an n⁺type diffused region 61 formed shallower than diffused regions 51 to 53 in epitaxial layer 20, and gates 91 to 93 of polycrystalline silicon or the like formed on diffused regions 51 and 53 with an oxide film (not shown) therebetween.

[0038] Epitaxial layer 20 is electrically isolated by isolating diffused regions 31 to 33 to form island regions IR1 and IR2. In island region IR1, n⁻type epitaxial layer 20, n⁺type buried diffused region 41, n type diffused regions 81 and 82 form an n type well. In island region IR2, n⁻type epitaxial layer 20, buried diffused region 42, n type diffused regions 83 and 84 form an n type well. The n channel DMOS transistor 101 shown in FIG. 2 is formed in island region IR1. DMOS transistor 101 consists of a drain formed by n type diffused region 81 and n⁻type epitaxial layer 20, a source formed by n⁺type diffused region 61 and 62, and gates 91 and 92 formed of polycrystalline silicon. DMOS transistor 101 has its drain connected to a power supply terminal 102 and its source connected to an output terminal 104. The p type diffused region 51 forms a backgate of DMOS transistor 101. This backgate and the above-mentioned source are commonly connected at output terminal 104.

[0039] Zener diode 105 and n channel DMOS transistor 103 shown in FIG. 2 are formed in island region IR2. Zener diode 105 has an anode formed by diffused regions 52 and 71 as well as a cathode formed by a diffused region 63. The anode of Zener diode 105 is connected to the source of DMOS transistor 101. The cathode of Zener diode 105 is connected to the gate of DMOS transistor 101.

[0040] In addition, n channel DMOS transistor 103 has a drain formed by diffused region 84 and epitaxial layer 20, a source formed of a diffused region 64, and gate 93 formed of polycrystalline silicon or the like. Diffused region 53 forms a backgate of DMOS transistor 103. The source and the backgate of DMOS transistor 103 is commonly connected at ground terminal 106. DMOS transistor 103 has its drain connected to the gate of DMOS transistor 101.

[0041] This semiconductor device differs from the conventional device of FIG. 12 in that Zener diode 105 and DMOS transistor 103 are formed within the same island region IR2. More particularly, isolating diffused region 34 and diffused region 66 shown in FIG. 12 are not provided in this semiconductor device, and instead of the omitted diffused region 66, diffused region 84 is connected to the gate of DMOS transistor 101. Accordingly, diffused region 84 functions as the drain of DMOS transistor 103 in this Embodiment 1.

[0042] In the above-described semiconductor device, a power supply terminal 102 is supplied with a high power supply voltage Vdc (of, for example, 100 V) while a ground terminal 106 is connected to the ground. Logic signals which are complementary to each other generated by logic circuit (not shown) in this semiconductor device are applied to the gates of DMOS transistors 103 and 113, respectively. Accordingly, when DMOS transistor 113 is turned on, DMOS transistor 103 is turned off. On the contrary, when DMOS transistor 113 is turned off, DMOS transistor 103 is turned on.

[0043] When DMOS transistor 113 is turned on, current flows from power supply terminal 102 to ground terminal 106 through resistor elements 109, 111 and DMOS transistor 113. Therefore, voltage is generated between the two ends of resistor element 109, and bipolar transistor 107 is turned on. Accordingly, current flows from power supply terminal 102 to the gate of DMOS transistor 101 through bipolar transistor 107, thereby charging this gate. When the gate voltage of DMOS transistor 101 is increased, DMOS transistor 101 is turned on so that output voltage Vout is increased from the ground voltage to reach high power supply voltage Vdc eventually. When bipolar transistor 107 is turned on, the gate voltage of DMOS transistor 101 is increased nearly to power supply voltage Vdc, but increase of output voltage Vout is slightly delayed from this increase of gate voltage. Accordingly, a high power supply voltage is temporarily applied between the gate and the source of DMOS transistor 101. However, since Zener diode 105 is connected in parallel between the gate and the source of DMOS transistor 101, the gate oxide film of DMOS transistor 101 would not be destroyed.

[0044] Meanwhile, when DMOS transistor 103 is turned on, the gate of DMOS transistor 101 is discharged by DMOS transistor 103, thereby turning off DMOS transistor 101. Then, output terminal 104 is short-circuited to ground terminal 106 via Zener diode 105 and DMOS transistor 103. Accordingly, output voltage Vout drops down from the high power supply voltage Vdc and eventually reaches ground voltage COM.

[0045] According to this Embodiment 1, since Zener diode 105 and DMOS transistor 103 are formed within the same island region IR2, the chip size is reduced. More particularly, the chip is made shorter by the distance between diffused regions 66 and 84 (which is a portion forming a ring shape when observed from above) in the conventional structure shown in FIG. 12. Conversely, since margin is created around the chip, it is also possible to increase the size of DMOS transistor 103. When the size of DMOS transistor 103 is made larger, its on-resistance can be made small such that it would be possible to increase the dropping rate of output voltage Vout.

[0046] [Embodiment 2]

[0047] FIG. 3 is a schematic cross sectional view showing a structure of a semiconductor device according to Embodiment 2 of the present invention. FIG. 4 shows an equivalent circuit of the structure shown in FIG. 3. Embodiment 2 differs from Embodiment 1 of FIG. 1 in that it has an epitaxial layer 20 electrically isolated into island regions IR1, IR3, IR4 by isolating diffused regions 31 to 34. In addition, a pnp bipolar transistor 115 instead of Zener diode 105 is formed in island region IR3. An DMOS transistor 103 is formed in island region IR4. The structure of DMOS transistor 101 is completely the same as the one shown in FIG. 1. Also, the structure of DMOS transistor 103 is completely the same as the one shown in FIG. 12.

[0048] Bipolar transistor 115 has an emitter formed by a p type diffused region 54, a base formed by epitaxial layer 20, and a collector formed by a semiconductor substrate 10. The emitter of bipolar transistor 115 is connected to an output terminal 104. The base of bipolar transistor 115 is connected to the gate of DMOS transistor 101 and the drain of DMOS transistor 103 through an n⁺type diffused region 65. The collector of bipolar transistor 115 is connected to a ground terminal 106 through isolating diffused region 33 and a diffused region 53. Accordingly, this pnp bipolar transistor 115 has a vertical structure.

[0049] According to this Embodiment 2, since bipolar transistor 115 is provided instead of the Zener diode, the dropping rate of output voltage Vout can be increased. This is because a base current flows into bipolar transistor 115 when DMOS transistor 103 is turned on, and a collector current which is hFE times as large as that base current is made to flow. In addition, although there is no Zener diode connected in series between the gate and the source of DMOS transistor 101, a pn junction of bipolar transistor 115 is connected instead, and thus this pn junction functions as the Zener diode. Accordingly, the gate oxide film of DMOS transistor 101 would not be destroyed even when a high voltage is applied between the gate and the source of DMOS transistor 101.

[0050] Furthermore, since a buried diffused region 43 is formed at the interface of semiconductor substrate 10 and epitaxial layer 20 within island region IR3, the breakdown voltage of bipolar transistor 115 is made higher. In addition, since n⁺type diffused region 65 is in slight contact with p type diffused region 54 forming the emitter of bipolar transistor 115, the Zener voltage of the parasitic Zener diode in bipolar transistor 115 is made lower. Accordingly, the gate oxide film of DMOS transistor 101 can be protected from high voltage effectively.

[0051] [Embodiment 3]

[0052] FIG. 5 is a schematic cross sectional view showing a structure of a semiconductor device according to Embodiment 3 of the present invention. FIG. 6 shows an equivalent circuit of the structure shown in FIG. 5. This Embodiment 3 differs from Embodiment 2 in FIG. 3 in that it has a Zener diode 105 in addition to pnp bipolar transistor 115 within an island region IR3. This Zener diode 105 has an anode formed by a p⁻type diffused region 71 and a cathode formed by an n⁺type diffused region 63. A diffused region 65 which is in slight contact with diffused region 71 also functions as a cathode. On this diffused regions 63 and 65, polycrystalline silicon films 201 and 202 are formed, respectively. Polycrystalline silicon films 201 and 202 function as a resistor element 117. Accordingly, the cathode of Zener diode 105 is connected to the gate of a DMOS transistor 101 through resistor element 117. The anode of Zener diode 105 is connected to the source of DMOS transistor 101.

[0053] According to this Embodiment 3, since Zener diode 105 is connected in parallel between the emitter and the base of bipolar transistor 115, it is ensured that destruction of the gate oxide film of DMOS transistor 101 can be prevented even when the Zener voltage of the parasitic Zener diode in bipolar transistor 115 is large. This is because the clamp voltage between the gate and the source of DMOS transistor 101 is determined by the newly provided Zener diode 105 instead of the parasitic Zener diode in bipolar transistor 115.

[0054] In addition, since resistor element 117 is connected in series with Zener diode 105, injection efficiency of the hole into bipolar transistor 115 would not be reduced even when the forward voltage Vf between the emitter and the base of bipolar transistor is larger than the forward voltage Vf of Zener diode 105, since there would be a voltage drop at resistor element 117 such that the voltage across Zener diode 105 would be made lower. In other words, resistor element 117 increases the apparent forward voltage of Zener diode 105. The required amount of voltage drop at resistor element 117 is only about a few volts. This resistor element 117 increases the resistance owing to Zener avalanche current, which in general is approximately as large as the current upon application of forward bias. Accordingly, it does not significantly affect the operation actually, since the voltage drop owing to the resistance at the time of avalanche is only about a few volts.

[0055] Although resistor element 117 is connected in series with Zener diode 105 in this Embodiment 3, this resistor element 117 does not have to be connected when the forward voltage between the emitter and the base of bipolar transistor 115 is smaller than the forward voltage of Zener diode 105.

[0056] [Embodiment 4]

[0057] FIG. 7 is a schematic cross section showing a structure of a semiconductor device according to Embodiment 4 of the present invention. The equivalent circuit of this structure is identical to the one shown in FIG. 4. This Embodiment 4 differs from Embodiment 2 of FIG. 3 in that it has a pnp bipolar transistor 115 and a DMOS transistor 103 formed in the same island region IR2. More particularly, isolated diffused region 34 and diffused region 66 in FIG. 3 are not provided in this Embodiment 4. Accordingly, the size of the chip is reduced by the distance between diffused regions 54 and 66. The drain of DMOS transistor 103 in this Embodiment 4 is connected to the gate of a DMOS transistor 101 through a diffused region 65. Thus, these bipolar transistor 115 and DMOS transistor 103 form an insulated gate type bipolar transistor (IGBT).

[0058] In addition, by thus increasing the complexity of the transistors, the electron current from DMOS transistor 103 and the hole current of bipolar transistor 115 flows into an epitaxial layer 20 simultaneously so that conductivity of epitaxial layer 20 is modulated, increasing the electron current of DMOS transistor 103. Accordingly, provided that hFE of bipolar transistor 115 is the same as that of Embodiment 2, collector current of bipolar transistor 115 is increased by the same rate as that of the increase in the electron current owing to the conductivity modulation. Therefore, the dropping rate of output voltage Vout is made faster than that of Embodiment 2.

[0059] As in the case of Embodiment 2, a parasitic Zener diode in bipolar transistor 115 prevents destruction of gate oxide film of DMOS transistor 101. A Zener diode 105 may also be added as in the above-described Embodiment 3, and furthermore, a resistor element 117 may also be added.

[0060] [Embodiment 5]

[0061] FIG. 8 is a schematic cross sectional view showing a structure of a semiconductor device according to Embodiment 5 of the present invention. FIG. 9 is an equivalent circuit diagram of the structure shown in FIG. 8. This Embodiment 5 differs from Embodiment 4 shown in FIG. 7 in that it has an npn bipolar transistor 119 formed instead of DMOS transistor 103. This bipolar transistor 119 has a collector formed by an n⁻type epitaxial layer 20, a base formed by a p type diffused region 55, and an emitter formed by an n⁺type diffused region 67. The collector of bipolar transistor 119 is in connection with the gate of a DMOS transistor 101 through diffused region 65. The collector of a bipolar transistor 115 is in connection with a ground terminal 106. Accordingly, bipolar transistor 115 having a vertical structure and bipolar transistor 119 having a lateral structure are formed within the same island region IR2.

[0062] According to this Embodiment 5, since bipolar transistor 119 starts operating in response to a base voltage higher than a forward bias voltage Vf, this bipolar transistor 119 is turned on sufficiently in response to general logical voltage (5 V). Therefore, a sufficient collector current flows into bipolar transistor 119, and in addition, a sufficient collector current flows into bipolar transistor 115 such that the dropping rate of output voltage Vout is made faster.

[0063] A parasitic Zener diode in bipolar transistor 115 prevents destruction of gate oxide film of DMOS transistor 101. Also, as in the case of Embodiment 3, a Zener diode 105 may also be added, and furthermore, a resistor element 117 may also be added.

[0064] [Embodiment 6]

[0065] FIG. 10 is a schematic cross sectional view showing a structure of a semiconductor device according to Embodiment 6 of the present invention FIG. 11 is a equivalent circuit diagram of a structure shown in FIG. 10. In this Embodiment 6, n channel DMOS transistors 121 and 123 are formed within the same island region IR2 in addition to the structure of FIG. 8. DMOS transistor 121 has a drain formed by an epitaxial layer 20, a source formed by an n⁺type diffused region 67, and a gate 94 formed of polycrystalline silicon. DMOS transistor 121 has its drain connected to the gate of a DMOS transistor 101 through a diffused region 65. The source of DMOS transistor 121 is connected to a ground terminal 106. DMOS transistor 123 has its drain connected to a p type diffused region 56. This diffused region 56 forms a collector of a bipolar transistor 115. The source of DMOS transistor 123 is connected to ground terminal 106.

[0066] Accordingly, bipolar transistors 115 and 119 form a thyristor. DMOS transistor 121 is provided to turn this thyristor on, while DMOS transistor 123 is provided to turn this thyristor off.

[0067] When DMOS transistor 121 is turned off, a base current flows into bipolar transistor 115 and a collector current which is hFE times as large as that base current flows into ground terminal 106 through the base and the emitter of bipolar transistor 119. Once the thyristor is turned on as described above, a large current flows regardless of the on-resistance of DMOS transistor 121. Therefore, the dropping rate of output voltage Vout is made faster. Meanwhile, when DMOS transistor 123 is turned on, bipolar transistor 119 is turned off, thus turning off the thyristor.

[0068] A parasitic Zener diode in bipolar transistor 115 prevents destruction of the gate oxide film of DMOS transistor 101. As in the case of Embodiment 3, a Zener diode 105 may also be added, and furthermore, a resistor element 117 may also be added.

[0069] Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.