Parallelism and crosstalk check on a printed circuit board (PCB)

[0002] 1. Field of the Invention

[0003] This invention relates generally to computer hardware and software and, more particularly, to a method for testing signal integrity on a printed circuit board (PCB) design.

[0004] 2. Description of the Related Art

[0005] There is a constant drive within the computer industry to reduce signal integrity problems on printed circuit boards (PCBs). In particular, there is often a need to reduce signal integrity problems associated with parallelism or crosstalk in the design of PCBs. Parallelism or crosstalk involves the long parallel runs of traces interconnecting elements on the PCBs. The long parallel runs of traces may couple electrical noise onto one another. Often, after a PCB has been routed, the board designer has no easy way to verify that board has been routed according to the specified parallelism guidelines.

[0006] Conventionally, the board designer may eyeball the nets of traces one layer at a time. However, even if there is a way manually to identify the problem nets of traces, there is a very limited capability to quantify the severity of the problem. Without a method to quantify the severity of the parallelism problem, given that thousands of traces may be present in a device, the board designer may not know where to begin to fix the problem nets of traces.

[0007] The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.

[0008] In one aspect of the present invention, a method is provided, the method comprising associating each net of traces in a list of nets of the traces on a routed PCB with a parallelism index value and sorting the list of the nets of the traces on the routed PCB based on the parallelism index values. The method also comprises providing a list of victim nets of traces on the routed PCB based on the parallelism index values, each of the victim nets on the list of the victim nets associated with at least one offending net of traces on the routed PCB.

[0009] In another aspect of the present invention, a system is provided, the system comprising a representation of a routed PCB having a plurality of nets of traces thereon and a list of nets of the traces on the representation of the routed PCB with a parallelism index value associated with each net of the traces in the list of the nets of the traces on the representation of the routed PCB, the list of the nets of the traces on the representation of the routed PCB sorted based on the parallelism index values. The system also comprises a list of victim nets of traces on the representation of the routed PCB provided based on the parallelism index values, each of the victim nets on the list of the victim nets associated with at least one offending net of traces on the representation of the routed PCB.

[0010] In yet another aspect of the present invention, a device is provided, the device comprising means for associating each net of traces in a list of nets of the traces on a routed PCB with a parallelism index value and means for sorting the list of the nets of the traces on the routed PCB based on the parallelism index values. The device also comprises means for providing a list of victim nets of traces on the routed PCB based on the parallelism index values, each of the victim nets on the list of the victim nets associated with at least one offending net of traces on the routed PCB.

[0011] The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which the leftmost significant digit(s) in the reference numerals denote(s) the first figure in which the respective reference numerals appear, and in which:

[0012] FIGS. 1-3 schematically illustrate various embodiments of a device and a system according to the present invention; and

[0013] FIGS. 4-8 schematically illustrate various embodiments of a method practiced in accordance with the present invention.

[0014] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0015] Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0016] Illustrative embodiments of a method and device according to the present invention are shown in FIGS. 1-8. As shown in FIG. 1, a system 100 may comprise a routed PCB 110 having a plurality of nets of traces 130 thereon, a list 120 of the nets of the traces 130 and a list of victim nets of the traces 150. The plurality of the nets of the traces 130 on the routed PCB 110 may include nets of traces 130 (shown in phantom) that are disposed at a different level on the routed PCB 110 than other nets of traces 130. For example, as shown in FIG. 2, traces 230 and 240 are disposed between plane n 200 and plane n+1 210 whereas traces 250, 260 and 270 are disposed between plane n+1 210 and plane n+2220, where the value of n may range from 1 to any finite number. Similarly, trace 250 is disposed at a different level than traces 260 and 270 even between plane n+1 210 and plane n+2 220.

[0017] The list of the victim nets of the traces 150 may be associated with at least one offending net of traces 160 (as indicated by arrow 165). The list of the victim nets of the traces 150 may also be associated with another offending net of traces 170 (shown in phantom and as indicated by arrow 175, also shown in phantom).

[0018] The list 120 of the net of the traces 130 on the routed PCB 110 may have a parallelism index (∥-ism index) i 140 value (where i may range from 1 to the number of nets of traces 130) associated with each net of the traces 130 on the routed PCB 110. The list 120 of the net of the traces 130 on the routed PCB 110 may be sorted based on the parallelism index (∥-ism index) i 140 values. The list of the victim nets of the traces 150 may be provided based on the parallelism index (∥-ism index) i 140 values from the list 120 of the net of the traces 130 on the routed PCB 110 (as indicated by arrow 125). Similarly, the list(s) of the offending nets of the traces 160 and/or 170 may be provided based on the parallelism index (∥-ism index) i 140 values from the list 120 of the net of the traces 130 on the routed PCB 110 (as indicated by arrows 125, the one connecting to the offending nets of the traces 170 shown in phantom). The list 120 of the net of the traces 130 on the routed PCB 110 may be derived by an analysis of the routed PCB 110 (as indicated by arrow 115).

[0019] For example, Innoveda Inc.'s XTK® toolkit (QuadDesign TLC) may be used to extract values from Cadence Inc.'s Allegros board (.brd) file. The XTK® toolkit has the advantage that XTK® captures both same-layer parallelism between traces (such as between either traces 230 and 240 or traces 260 and 270) and broadside parallelism between traces (such as between either traces 250 and 260 or traces 250 and 270). The XTK® toolkit also captures same-layer parallelism between nets of traces at substantially the same level of the routed PCB 110 and/or between nets of traces at different levels of the routed PCB 110. In addition, the XTK® toolkit has the advantage that XTK® output files are text (.txt) format and, consequently, readable by most tools. The XTK® toolkit also has an XNS® simulator inside the toolkit that is able to perform post-routing timing simulations.

[0020] The XTK® toolkit may scan for parallel nets of the traces 130 given a spacing of 1-mil (0.00254 cm), to capture direct broadside parallel nets of the traces 130. As shown in FIG. 3, the spacings s₁, and s₂between traces 300 and 310, and the spacings s₃and s₄between traces 320 and 330, may be measured from substantially the center of the relevant portion of one trace to substantially the center of the relevant portion of another trace. Similarly, the parallel lengths L₁and L₂between respective relevant portions of the traces 300 and 310, and the parallel lengths L₃and L₄between respective relevant portions of the traces 320 and 330, may be measured as shown in FIG. 3. The traces 310 and 320 may be separated by a spacing s₅and may have a parallel length L₅.

[0021] The XTK® toolkit may then find all parallel nets of the traces 130 identified by XTK® to be problem nets of traces, either victim nets of the traces 150 and/or offending nets of the traces 160 and 170, facing a parallelism problem with a varying degree of severity that may correspond to the respective parallelism index (∥-ism index) i 140 value. For example, one set of the problem nets of the traces may correspond to the victim nets of the traces 150 being victimized by one or more of the offending nets of the traces 160 and/or 170.

[0022] The XTK® toolkit may then reset the spacing to 2-mil (0.00508 cm) and repeat the actions described above when the spacing is set to 1-mil (0.00254 cm). The XTK® toolkit may then reset the spacing to 3-mil (0.00762 cm) and repeat the actions described above when the spacing is set to 1-mil (0.00254 cm). The XTK® toolkit may repeatedly reset the spacing by 1-mil (0.00254 cm) increments, until a predetermined spacing limit (for example, 20-mil or 0.0508 cm) is reached, depending on the run time requirements.

[0023] After all the parallelism nets of the traces 130 are completed and/or compiled according to the incremental 1-mil (0.00254 cm) spacings, the following condition may be imposed: The problem or violation nets of the traces 130 for the 1-mil (0.00254 cm) spacing iteration will be a subset of the problem or violation nets of the traces 130 for the 2-mil (0.00508 cm) spacing iteration, the problem or violation nets of the traces 130 for the 2-mil (0.00508 cm) spacing iteration will be a subset of the problem or violation nets of the traces 130 for the 3-mil (0.00762 cm) spacing iteration, and so forth. By performing a “diff” function or operation through the resulting script, it can be found exactly when the nets of the traces 130 have 1-mil (0.00254 cm), 2-mil (0.00508 cm), 3-mil (0.00762 cm) spacings and so forth. This is one way to get this piece of the information with the XTK® toolkit.

[0024] A final script may apply appropriate weightings (due to the respective spacings), scalings (due to the respective relative voltage swings) and saturation cutoff (due to the crosstalk saturation effect) to the effective parallelism lengths. The effective parallelism lengths for a given victim net of the traces 150 may then be summed up, arriving at a “worst-case” parallelism length for the given victim net of the traces 150. The statistical “worst-case” parallelism length for a given victim net of the traces 150 may be derived by taking the square root of the sum of the squares of all the effective parallelism lengths for the given victim net of the traces 150. In this way, the final list of the problem or violation nets the traces 130 may be determined.

[0025] FIGS. 4-8 schematically illustrate particular embodiments of respective methods 400-800 practiced in accordance with the present invention. FIGS. 1-3 schematically illustrate various devices and systems with which the methods 400-800 may be practiced. For the sake of clarity, and to further an understanding of the invention, the methods 400-800 shall be disclosed in the context of the various devices and systems shown in FIGS. 1-3. However, the present invention is not so limited and admits wide variation, as is discussed further below.

[0026] As shown in FIG. 4, the method 400 begins, as set forth in box 420, by associating each net of the traces 130 in the list 120 of the nets of the traces 130 on the routed PCB 110 with a parallelism index (∥-ism index) i 140 value. The method 400 proceeds, as set forth in box 430, by sorting the list 120 of the nets of the traces 130 on the routed PCB 110 based on the parallelism index (∥-ism index) i 140 values. The method 400 then proceeds, as set forth in box 440, by providing the list of the victim nets of the traces 150 on the routed PCB 110 based on the parallelism index (∥-ism index) i 140 values. Each of the victim nets on the list of the victim nets of the traces 150 is associated with at least one offending net of traces 160 and/or 170 on the routed PCB 110.

[0027] As shown in FIG. 5, the method 500 begins, as set forth in box 420, by associating each net of the traces 130 in the list 120 of the nets of the traces 130 on the routed PCB 110 with a parallelism index (∥-ism index) i 140 value. The method 500 proceeds, as set forth in box 430, by sorting the list 120 of the nets of the traces 130 on the routed PCB 110 based on the parallelism index (∥-ism index) i 140 values. The method 500 then proceeds, as set forth in box 440, by providing the list of the victim nets of the traces 150 on the routed PCB 110 based on the parallelism index (∥-ism index) i 140 values. Each of the victim nets on the list of the victim nets of the traces 150 is associated with at least one offending net of traces 160 and/or 170 on the routed PCB 110. The method 500 then proceeds, as set forth in box 550, by associating each net of the traces 130 with the parallelism index (∥-ism index) i 140 value corresponding to the severity of a parallelism problem faced by each net of the traces 130 as a victim net of traces 150 being victimized by at least one offending net of traces 160 and/or 170 on the routed PCB 110. In various illustrative embodiments, sorting the list of the nets of the traces 130 on the routed PCB 110 based on the parallelism index (∥-ism index) i 140 values comprises sorting the list of the nets of the traces 130 in decreasing order of the severity of the parallelism problem faced by each net of the traces 130 on the routed PCB 110.

[0028] As shown in FIG. 6, the method 600 begins, as set forth in box 420, by associating each net of the traces 130 in the list 120 of the nets of the traces 130 on the routed PCB 110 with a parallelism index (∥-ism index) i 140 value. The method 600 proceeds, as set forth in box 430, by sorting the list 120 of the nets of the traces 130 on the routed PCB 110 based on the parallelism index (∥-ism index) i 140 values. The method 600 then proceeds, as set forth in box 440, by providing the list of the victim nets of the traces 150 on the routed PCB 110 based on the parallelism index (∥-ism index) i 140 values. Each of the victim nets on the list of the victim nets of the traces 150 is associated with at least one offending net of traces 160 and/or 170 on the routed PCB 110. The method 600 then proceeds, as set forth in box 650, by associating each net of the traces 130 with the parallelism index (∥-ism index) i 140 value based on same-layer parallelism and/or broadside parallelism, as described above.

[0029] As shown in FIG. 7, the method 700 begins, as set forth in box 420, by associating each net of the traces 130 in the list 120 of the nets of the traces 130 on the routed PCB 110 with a parallelism index (∥-ism index) i 140 value. The method 700 proceeds, as set forth in box 430, by sorting the list 120 of the nets of the traces 130 on the routed PCB 110 based on the parallelism index (∥-ism index) i 140 values. The method 700 then proceeds, as set forth in box 440, by providing the list of the victim nets of the traces 150 on the routed PCB 110 based on the parallelism index (∥-ism index) i 140 values. Each of the victim nets on the list of the victim nets of the traces 150 is associated with at least one offending net of traces 160 and/or 170 on the routed PCB 110. The method 700 then proceeds, as set forth in box 750, by associating each net of the traces 130 with the parallelism index (∥-ism index) i 140 value based on both same-layer parallelism and broadside parallelism, as described above.

[0030] As shown in FIG. 8, the method 800 begins, as set forth in box 420, by associating each net of the traces 130 in the list 120 of the nets of the traces 130 on the routed PCB 110 with a parallelism index (∥-ism index) i 140 value. The method 800 proceeds, as set forth in box 430, by sorting the list 120 of the nets of the traces 130 on the routed PCB 110 based on the parallelism index (∥-ism index) i 140 values. The method 800 then proceeds, as set forth in box 440, by providing the list of the victim nets of the traces 150 on the routed PCB 110 based on the parallelism index (∥-ism index) i 140 values. Each of the victim nets on the list of the victim nets of the traces 150 is associated with at least one offending net of traces 160 and/or 170 on the routed PCB 110. The method 800 then proceeds, as set forth in box 850, by associating each net of the traces 130 with the parallelism index (∥-ism index) i 140 value based on a backward crosstalk equation.

[0031] In various illustrative embodiments, a method and a device for parallelism and crosstalk checking according to the present invention may associate each net of the traces 130 from a routed Allegro® board file (.brd) with a parallelism index (∥-ism index) i 140 value corresponding to the severity of the parallelism problem, viewing each net of the traces 130 as a victim net of traces 150. Such a parallelism and check may comprise both same-layer parallelism and broadside parallelism, as described above. By way of contrast, conventional versions of Allegro® do not capture data indicative of broadside parallelism.

[0032] In these various illustrative embodiments, the parallelism and crosstalk checking according to the present invention may sort the list 120 of the nets of the traces 130 in decreasing order of the severity of the parallelism problem. The parallelism and crosstalk checking according to the present invention may provide, in a separate file, the offending nets of the traces 160 and/or 170 associated with each victim net of the traces 150 to allow the designer to start with the worst-case offending nets of the traces 160 and/or 170.

[0033] In various illustrative embodiments according to the present invention, the backward crosstalk equation may be used. If L_parallel>L_saturated, then the backward crosstalk is saturated. Here L_parallelis the actual parallel length of the trace $L_{\mathrm{saturated}}=\frac{t_{\mathrm{rise}}}{2t_{\mathrm{propagation}\mathrm{delay}}},$

[0034] t_riseis the rise time of the offending logic and t_{propagation delay}is the signal propagation delay of the trace per unit length. When L_parallel>L_saturated, and the backward crosstalk is saturated, then $V_{\mathrm{noise}}=V_{\mathrm{noise}}^{\mathrm{saturated}}=K_{\mathrm{backward}\mathrm{crosstalk}}{V}_{\mathrm{swing}},$

[0035] where V_noiseis the crosstalk noise voltage, $V_{\mathrm{noise}}^{\mathrm{saturated}}$

[0036] is the saturated crosstalk noise voltage, K_{backward crosswalk}is the backward crosstalk coefficient and V_swingis the voltage swing of the offending net of the traces 160 or 170.

[0037] If L_parallel≦L_saturated, then the backward crosstalk is not saturated. In this case, $V_{\mathrm{noise}}=K_{\mathrm{backward}\mathrm{crosstalk}}{V}_{\mathrm{swing}}\frac{L_{\mathrm{parallel}}}{L_{\mathrm{saturated}}}=V_{\mathrm{noise}}^{\mathrm{saturated}}\left(\frac{L_{\mathrm{parallel}}}{L_{\mathrm{saturated}}}\right).$

[0038] When the backward crosstalk is not saturated, the crosstalk noise voltage V_noiseis proportional to the length of the traces L_parallelrunning parallel to the victim net of the traces 150, as long as the coupled length L_parallel, of the traces running parallel to the victim net of the traces 150 is less than or equal to $L_{\mathrm{saturated}}=\frac{t_{\mathrm{rise}}}{2t_{\mathrm{propagation}\mathrm{delay}}},$

[0039] where again t_riseis the rise time of the offending logic and t_{propagation delay}is the signal propagation delay of the trace per unit length, as described, for example at pages 82-89 of the MECL System Handbook.

[0040] Note that only backward crosstalk is considered. The forward crosstalk is ignored, since the forward crosstalk is small for most stripline transmission line structures of interest. Note also that the crosstalk noise is proportional to the length of the traces running parallel to the victim net of the traces 150 as long as coupled length L_parallelis less than $L_{\mathrm{saturated}}=\frac{t_{\mathrm{rise}}}{2t_{\mathrm{propagation}\mathrm{delay}}}.$

[0041] The crosstalk noise is also a function of the spacing between the offending nets of the traces 160 and/or 170 and the victim net of the traces 150. The spacing between two traces may be defined as the center-to-center spacing (or pitch) between the two traces, as described above.

[0042] In various illustrative embodiments according to the present invention, the effective parallel lengths are weighted according to the spacing between the nets. The “weight” table is specified for each routed printed circuit board (PCB) since each stackup on the respective routed PCB may be different, requiring a different weight table.

[0043] In various illustrative embodiments according to the present invention, the effective parallel lengths are scaled (multiplied) based on the relative voltage swing of the offending and victim nets of traces. For example, an LVTTL to DTL will be scaled up by 2.0 since LVTTL will have twice as a big a voltage swing as the DTL. Note that the effective parallel length may saturate (as in the backward crosstalk case described above) when reaching a fixed length based on the input/output (I/O) technology involved, as described above.

[0044] In various illustrative embodiments according to the present invention, the worst-case parallelism length for a victim net of traces 150 is a summation of the all the effective parallel lengths. In these various illustrative embodiments, the statistical worst-case parallelism length for a victim net is a square root of a sum of the squares (root-sum-square or RSS) of all the effective lengths.

[0045] As shown in FIG. 3, to give a simplified illustrative example, the spacings s₁and s₂between traces 300 and 310 may be taken to be 1 mil (0.00254 cm) and 2 mil (0.00508 cm), respectively. Similarly, the spacings s₃and s₄between traces 320 and 330, may also be taken to be 1 mil (0.00254 cm) and 2 mil (0.00508 cm), respectively, the spacing s₅between the traces 310 and 320 may be taken to be 3 mil (0.00762 cm) and the respective voltage swing scaling factors may all be taken to be unity. The effective parallel length $L_{\mathrm{parallel}12}^{\mathrm{effective}}$

[0046] between the traces 300 and 310, weighted relative to the spacing s₁, may be given by $L_{\mathrm{parallel}12}^{\mathrm{effective}}=\frac{L_1}{s_1/s_1}+2\frac{L_2}{s_2/s_1}=\frac{L_1}{1}+2\frac{L_2}{2}=L_1+L_2.$

[0047] Similarly, the effective parallel length $L_{\mathrm{parallel}34}^{\mathrm{effective}}$

[0048] between the traces 320 and 330, weighted relative to the spacing s₁, may be given by $L_{\mathrm{parallel}34}^{\mathrm{effective}}=\frac{L_3}{s_3/s_1}+2\frac{L_4}{s_4/s_1}=\frac{L_3}{1}+2\frac{L_4}{2}=L_3+L_4.$

[0049] Likewise, the effective parallel length $L_{\mathrm{parallel}5}^{\mathrm{effective}}$

[0050] between the traces 310 and 320, weighted relative to the spacing s₁, may be given by $L_{\mathrm{parallel}5}^{\mathrm{effective}}=\frac{L_5}{s_5/s_1}=\frac{L_5}{3}.$

[0051] The effective parallel length $L_{\mathrm{parallel}54}^{\mathrm{effective}}$

[0052] between the traces 310 and 330, similarly weighted relative to the spacing s₁, may be given by $L_{\mathrm{parallel}54}^{\mathrm{effective}}=\frac{L_3}{\left(s_3+s_5\right)/s_1}+2\frac{L_4}{\left(s_4+s_5\right)/s_1}=\frac{L_3}{4}+2\frac{L_4}{5}.$

[0053] The worst-case parallelism length $L_{\mathrm{parallel}}^{\mathrm{worst}-\mathrm{case}}$

[0054] for the trace 310 as a victim net being victimized by the traces 300, 320 and 330 as offending nets may be given by the sum of the respective effective parallel lengths: $L_{\mathrm{parallel}}^{\mathrm{worst}-\mathrm{case}}=L_{\mathrm{parallel}12}^{\mathrm{effective}}+L_{\mathrm{parallel}5}^{\mathrm{effective}}+L_{\mathrm{parallel}54}^{\mathrm{effective}}.$

[0055] In various illustrative embodiments, a suitable definition of the parallelism index (∥-ism index) i 140 value $I_{\mathrm{parallelism}\mathrm{index}}^{\mathrm{worst}-\mathrm{case}}$

[0056] for the trace 310 may be given by the ratio of the worst-case parallelism length $L_{\mathrm{parallel}}^{\mathrm{worst}-\mathrm{case}}$

[0057] for the trace 310 to the spacing $s_1:I_{\mathrm{parallelism}\mathrm{index}}^{\mathrm{worst}-\mathrm{case}}=L_{\mathrm{parallel}}^{\mathrm{worst}-\mathrm{case}}/s_1.$

[0058] With such a definition, as the spacing between the respective nets of traces increases, the severity of the parallelism problem would decrease, as indicated by the decrease in such a parallelism index (∥ism index) i 140 value $I_{\mathrm{parallelism}\mathrm{index}}^{\mathrm{worst}-\mathrm{case}}.$

[0059] Conversely, as the spacing between the respective nets of traces decreases, the severity of the parallelism problem would increase, as indicated by the increase in the parallelism index (∥-ism index) i 140 value $I_{\mathrm{parallelism}\mathrm{index}}^{\mathrm{worst}-\mathrm{case}}.$

[0060] Similarly, as the worst-case parallelism length $L_{\mathrm{parallel}}^{\mathrm{worst}-\mathrm{case}}$

[0061] for the respective net of traces increases (decreases), the severity of the parallelism problem would increase (decrease), as indicated by the increase (decrease) in the parallelism index (∥-ism index) i 140 value $I_{\mathrm{parallelism}\mathrm{index}}^{\mathrm{worst}-\mathrm{case}}.$

[0062] Similarly, the statistical worst-case parallelism length $L_{\mathrm{parallel}}^{\mathrm{statistical}\mathrm{worst}-\mathrm{case}}$

[0063] for the trace 310 as the victim net being victimized by the traces 300, 320 and 330 as the offending nets may be given by the root-sum-square of the respective effective parallel lengths: $L_{\mathrm{parallel}}^{\mathrm{statistical}\mathrm{worst}-\mathrm{case}}=\sqrt{{\left(L_{\mathrm{parallel12}}^{\mathrm{effective}}\right)}^2+{\left(L_{\mathrm{parallel5}}^{\mathrm{effective}}\right)}^2+{\left(L_{\mathrm{parallel54}}^{\mathrm{effective}}\right)}^2}.$

[0064] In various alternative illustrative embodiments, an alternative suitable definition of the parallelism index (∥-ism index) i 140 value $I_{\mathrm{parallel}\mathrm{ism}\mathrm{index}}^{\mathrm{statistical}\mathrm{worst}-\mathrm{case}}$

[0065] for the trace 310 may be given by the ratio of the statistical worst-case parallelism length $L_{\mathrm{parallel}}^{\mathrm{statistical}\mathrm{worst}-\mathrm{case}}$

[0066] for the trace 310 to the spacing $s_1:I_{\mathrm{parallel}\mathrm{ism}\mathrm{index}}^{\mathrm{statistical}\mathrm{worst}-\mathrm{case}}=L_{\mathrm{parallel}}^{\mathrm{statistical}\mathrm{worst}-\mathrm{case}}/s_1.$

[0067] With such a definition, as with the previously described definition, as the spacing between the respective nets of traces increases, the severity of the parallelism problem would decrease, as indicated by the decrease in such a parallelism index (∥-ism index) i 140 value $I_{\mathrm{parallel}\mathrm{ism}\mathrm{index}}^{\mathrm{statistical}\mathrm{worst}-\mathrm{case}}.$

[0068] Conversely, as with the previously described definition, as the spacing between the respective nets of traces decreases, the severity of the parallelism problem would increase, as indicated by the increase in the parallelism index (∥-ism index) i 140 value $I_{\mathrm{parallel}\mathrm{ism}\mathrm{index}}^{\mathrm{statistical}\mathrm{worst}-\mathrm{case}}.$

[0069] Similarly, as the worst-case parallelism length $L_{\mathrm{parallel}}^{\mathrm{statistical}\mathrm{worst}-\mathrm{case}}$

[0070] for the respective net of traces increases (decreases), the severity of the parallelism problem would increase (decrease), as indicated by the increase (decrease) in the parallelism index (∥-ism index) i 140 value $I_{\mathrm{parallel}\mathrm{ism}\mathrm{index}}^{\mathrm{statistical}\mathrm{worst}-\mathrm{case}}.$

[0071] In various other alternative embodiments, other suitable definitions of the parallelism index (∥-ism index) i 140 value I_{parallelism index}for the trace 310 may be given.

[0072] In various illustrative embodiments according to the present invention, the parallelism weight may be derived as follows. A baseline crosstalk level may be picked, such as about 10%. The center-to-center spacing of the traces with approximately 10% crosstalk may be determined. That particular center-to-center spacing may be used as an index of 1.0. For example, for the system shown in FIG. 2 of the traces 230 and 240 disposed between the plane n 200 and the plane n+1 210, in the case where the distance d₁, between the plane n 200 and the plane n+1 210 is about 13 mil (0.03302 cm), the distance d₂between the traces 230 and 240 and the plane n+1 210 is about 4 mil (0.01016 cm), the width w of each of the traces 230 and 240 is about 4 mil (0.01016 cm) and the center-to-center spacing s is about 6 mil (0.01524 cm), which is known as a 4 mil-6 mil-4 mil conductor system, the backward crosstalk is calculated to be roughly about 10%.

[0073] The relative backward crosstalk coefficient $K_{\mathrm{backward}\mathrm{crosstalk}}^{\mathrm{relative}}$

[0074] for all possible spacings may be calculated from broadside parallelism of 1 mil (0.00254 cm) all the way to the desired maximum spacing, normally around 20 mils (0.0508 cm). All the backward crosstalk coefficients K_{backward crosstalk}may be normalized against the center-to-center spacing s that corresponds to the 10% crosstalk case with an index of 1.0, as described above.

[0075] The voltage swing scale factor may be specified as follows. The voltage swing scale factor takes in account the relative voltage swing of the offending net(s) of traces as compared to the respective victim net(s) of traces. For example, an LVTTL to DTL will be scaled up by 2.0 since LVTTL will have twice as a big a voltage swing as the DTL. This may be done for all combinations of the input/output (I/O) technology. Additionally, a SPICE simulation may be done to justify the scale factors because there may be subtleties such as a termination or terminations or a lack thereof that might affect the voltage swing. This also implies that an input/output (I/O) technology type may be attached with each net of traces 130. The net name may also have a key prefix and suffix to identify the input/output (I/O) type.

[0076] Any of the above-disclosed embodiments of a method and a device according to the present invention enables a printed circuit board (PCB) designer an easy way to verify, after a PCB has been routed, that the routed PCB has been routed according to specified parallelism guidelines. The PCB designer does not need to eyeball the nets of traces on the routed PCB one layer at a time. Any of the above-disclosed embodiments of a method and a device according to the present invention enables quantification of the severity of the parallelism problem(s) automatically identified for the problem nets of traces. With such a method to quantify the severity of the parallelism problem, even given a net count of thousands or so, the PCB designer knows where to begin to fix the problem nets of traces. Additionally, any of the above-disclosed embodiments of a method of manufacturing according to the present invention enables device fabrication with increased device accuracy and precision, increased efficiency and increased device yield, enabling a streamlined and simplified process flow, thereby decreasing the complexity and lowering the costs of the manufacturing process and further increasing throughput.

[0077] The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. In particular, every range of values (of the form, “from about a to about b,” or, equivalently, “from approximately a to b,” or, equivalently, “from approximately a-b”) disclosed herein is to be understood as referring to the power set (the set of all subsets) of the respective range of values, in the sense of Georg Cantor. Accordingly, the protection sought herein is as set forth in the claims below.