Transponder system with acknowledgements associated with respective transponders

[0002] 1. Field of the Invention

[0003] The present invention generally relates to a communication between a write/read station of a transponder system and at least one transponder of the transponder system. The present invention specifically relates to a generation of an acknowledge data block and an identification data block during the communication between the write/read station and the transponder.

[0004] 2. Description of the Related Art

[0005] U.S. Pat. No. 5,539,394 A describes a transponder system in which communication between the write/read station and a plurality of transponders takes place, in successive time slots of time slot sequences, communication between the write/read station and a transponder actually taking place exclusively if only a single transponder is associated with each time slot. This is the case when a sole transponder transmits its associated identification data block to the write/read station in a time slot, i.e. if no collision occurs between two or more identification data blocks from two or more transponders in one time slot. In the known transponder system, the write/read station transmits an acknowledge data block to each sole transponder having transmitted its associated identification data block to the write/read station in a time slot, so that each of these transponders is signaled that the write/read station has correctly recognized and hence selected the relevant transponder. As described in the cited patent document U.S. Pat. No. 5,539,394 A, the transmission of the respective acknowledge data block associated with a transponder can take place in the same time slot in which a transponder has transmitted its identification data block to the write/read station. In this case, each acknowledge data block may have the same bit configuration and consist, for example of a predetermined number of “0” bits or “1” bits, for example one byte with a total of eight “0” bits, however, without an own acknowledge data block being associated with each transponder. The cited patent document U.S. Pat. No. 5,539,394 A does not provide further information as regards the bit configuration of the acknowledge data blocks transmitted to the transponders by the write/read station in each time slot.

[0006] The cited patent document U.S. Pat. No. 5,539,394 A also describes a second possibility for the transfer of acknowledgements from the write/read station to the selected transponders. This second possibility consists in that acknowledgement takes place at the end of a time slot sequence, consisting of a plurality of time slots, in that at the end of such a time slot sequence a group acknowledge data block and subsequently additionally all identification data blocks of the sole transponders having transmitted their associated identification data block to the write/read station in a time slot in the preceding time slot sequence are transmitted to these transponders by the write/read station. It is thus achieved that for each transponder the write/read station transmits only an acknowledgement exclusively associated with this transponder to this transponder; however each acknowledgement associated with a transponder then consists of the group acknowledge data block and the overall identification data block of the relevant transponder. Consequently, each acknowledgement in the known transponder system has a detrimentally long data block length; this is unattractive with a view to achieving an as short as possible communication time between the write/read station and the plurality of selected transponders, and also with a view to achieving an as small as possible number of modulation steps for the transmission of an acknowledgement from the write/read station to the transponders. An as small as possible number of modulation steps is always desirable, because a comparatively high number of modulation steps has an adverse effect on the level of side bands of the carrier signal occurring during a transmission utilizing a modulated carrier signal; this is because a comparatively high number of modulation steps causes detrimentally high levels of the side bands, giving rise to conflicts in many countries with official rules and regulations which define a maximum permissible level for these side bands.

[0007] It is an object of the invention to avoid the described problems and to provide an improved method, an improved write/read station, an improved transponder and an improved integrated circuit.

[0008] In order to achieve this object, a method according to the invention is characterized in that in the write/read station an acknowledge data block is generated for each transponder wherefrom an identification data block has been received, the bit configuration of said acknowledge data block being formed while using only a part of the identification data block associated with the relevant transponder.

[0009] In order to achieve the described object, a write/read station according to the invention is characterized in that the generating means are arranged to generate a respective acknowledge data block for a transponder, the bit configuration of said acknowledge data block being formable while using only a part of the identification data block associated with the relevant transponder.

[0010] In order to achieve the described object, a transponder according to the invention is characterized in that the transponder includes generating means for generating the acknowledge data block associated with the transponder, and that the transponder includes comparison means which can be supplied with the acknowledge data block generated by the generating means and with the acknowledge data block transmitted by a write/read station and received by the transponder, and can output at least control information representing the comparison result.

[0011] In order to achieve the described object, an integrated circuit according to the invention is characterized in that the circuit includes generating means for generating the acknowledge data block associated with the circuit, and that the circuit includes comparison means which can be supplied with the acknowledge data block generated by the generating means and with the acknowledge data block transmitted by a write/read station and received by the circuit, and can output at least control information representing the comparison result.

[0012] Using only simple means, the steps according to the invention simply ensure that, in order to acknowledge the selection of a transponder according to the invention, an acknowledge data block which is associated only with the relevant transponder is transmitted from a write/read station according to the invention to a relevant transponder according to the invention; the foregoing is advantageously achieved by means of an acknowledge data block having only a short data block length, which is advantageous with a view to achieving an as short as possible communication time or transmission time and also with a view to achieving as few as possible modulation steps for the transmission.

[0013] These and other aspects of the invention will be apparent from the embodiment described hereinafter.

[0014] The invention will be described in detail hereinafter with reference to an embodiment shown in the drawings; however, the invention is not restricted thereto.

[0015] FIG. 1 shows a block diagram of an in this context essential part of a write/read station in an embodiment according to the invention.

[0016] FIG. 2 shows a block diagram of an in this case essential part of a data carrier and an integrated circuit for this data carrier in an embodiment according to the invention.

[0017] FIG. 1 shows a block diagram of a part of a write/read station 1 of a transponder system which will be referred to hereinafter as the station 1 for the sake of brevity. The station 1 is arranged and constructed for communication with a plurality of transponders 2 of such a transponder system. FIG. 2 shows such a transponder 2 which will be referred to hereinafter as the data carrier 2.

[0018] In respect of the communication between the station 1 and the data carriers 2, it is to be noted in advance that such communication takes place mainly in the form of data blocks DB, each data block DB consisting of a predetermined number of bytes, each byte consisting of a predetermined number of bits, being 8 bits in the present case. Instruction data blocks can be transferred from the station 1 to the data carriers 2 in the course of a communication between the station 1 and the data carriers 2; only one instruction data block thereof will be elaborated upon herein, that is to say a selection data block SDB. The station 1 can also transmit further instruction data blocks to the data carriers 2, for example a read data block, a write data block and a stop data block which, however, are not elaborated upon herein.

[0019] A selection data block SDB contains a selection instruction code, a hash value HV which is contained in the station 1, and information concerning a given number of time slots TS as well as, indirectly, information concerning the length of these time slots TS. A data carrier 2, or a plurality of data carriers 2, can be selected from a plurality of data carriers 2 by means of a selection data block SDB.

[0020] The station 1 can also generate an acknowledge data block QDB in the course of a communication between the station 1 and a data carrier 2. Using an acknowledge data block QDB, the station 1 informs a carrier 2 first of all that the station 1 has correctly received an identification data block IDB transmitted to the station 1 by a data carrier 2, and secondly that the instruction corresponding to an instruction data block previously transmitted to a data carrier 2, for example a read data block or a write data block or a stop data block, is to be executed by a data carrier 2. The acknowledge data block QDB may be formed, for example as a data block containing a given, invariable bit configuration or a given, invariable bit pattern. However, it is much more advantageous to generate for each data carrier 2 an acknowledge data block QDB which is exclusively associated with the relevant data carrier and whose bit configuration is related to the identification data block IDB which is transmitted to the station 1 by the relevant data carrier 2 and is associated with the relevant data carrier 2 as a characteristic. This aspect will be described in detail hereinafter.

[0021] In the course of a communication between the station 1 and a data carrier 2, a data carrier 2 transmits an identification data block IDB to the station 1. The identification data block IDB is significant and characteristic of the relevant data carrier 2. Each data carrier 2 contains an identification data block IDB, which is reserved specifically for this carrier and is issued only once. For example, such an identification data block IDB may represent a so-called serial number.

[0022] The construction of the station 1 will be described in detail hereinafter with reference to FIG. 1.

[0023] The station 1 includes sequencing module SM 3, which controls a plurality of routines and functions, only the in this context essential routines and functions thereof being described in detail hereinafter.

[0024] The station 1 also includes a clock signal generator CKSG 4, which generates a clock signal CLK having a frequency of 13.56 MHz. The clock signal CLK can be applied to the sequencing module SM 3 via a connection 5.

[0025] The station 1 also includes a first generating stage FGS 6 which is arranged to generate the instruction data blocks, i.e. to generate selection data blocks SDB, read data blocks, write data blocks and stop data blocks. The first generating stage FGS 6 can be controlled by the sequencing module SM 3 via a connection 7. Via a further connection 8, the first generating stage FGS 6 can be supplied with a so-called hash value HV which is contained in the sequencing module SM 3 as diagrammatically denoted by way of a block 9. The hash value HV is integrated in each generated selection data block SDB and hence is transmitted, together with the selection data block SDB, to the data carriers present within the communication range of the station 1.

[0026] The station 1 also includes generating module 10, which is arranged to generate each time an acknowledge data block QDB. The generating module 10 include a memory 11 for storing an identification data block IDB transmitted by a data carrier 2 and received by the station 1. The identification data block IDB consists, for example of a total of 8 bytes, each of which contains 8 bits. A received identification data block can be applied to the memory 11, via a connection 12, from the sequencing module SM 3. The memory 11 can also be controlled by the sequencing module SM 3 via a further connection 13. Via the connection 13, the memory 11 can be supplied with a bit address BA(HV)1, which corresponds to the hash value HV and forms an initial address for a part PM1 of the identification data block IDB stored in the memory 11. In the present case, the bit address BA(HV)1 is formed directly by the hash value HV. Such a bit address is often referred to as a “pointer”. The part PM1 of the identification data block IDB, determined by the hash value HV, can be output via a connection 14 by controlling the memory 11, via the connection 13, with the bit address BA(HV)1.

[0027] The generating module 10 of the station 1 also includes a so-called CRC8 stage 15. It is to be noted that the abbreviation CRC8 stands for “Cross Redundancy Check”. The CRC8 stage 15 can be controlled by the sequencing module SM 3 via a connection 16. The CRC8 stage 15 can receive the part PM1 of the identification data block IDB via the connection 14. The part PM1 applied to the CRC8 stage 15 is shifted through the CRC8 stage 15; during this shift an algorithm which can be realized by the CRC8 stage 15 is executed, after which a given value k1 is obtained at an output 17 of the CRC8 stage, which value constitutes control information corresponding to the read part PM1 of the stored identification data block IDB.

[0028] The generating module 10 also includes a second generating stage SGS 18 for generating a respective acknowledge data block QDB having a given bit configuration. The second generating stage SGS 18 can be controlled by the sequencing module SM 3 via a connection 19. Furthermore, the second generating stage SGS 18 can be controlled by a time slot counter TSC 21, via a further connection 20, as will be described in detail hereinafter. Furthermore, via a connection 22, the second generating stage SGS 18 can also be supplied with control information in the form of the value k1 delivered via the output 17 of the CRC8 stage 15. The second generating stage SGS 18 can be activated by the time slot counter TSC 21, via the connection 20, in a given time slot TS(1 . . . n . . . N) from among a total of N time slots. When the second generating stage SGS 18 is activated, it is arranged to generate an acknowledge data block QDB having a bit configuration which is determined by the value k1 output as control information by the CRC8 stage 15. It is thus achieved that the acknowledge data block QDB each time generated has a bit configuration which is generated by using only a part PM of the identification data block IDB associated with a data carrier 2, which identification data block IDB is each time stored in the memory 11 and the part PM1 of which can be applied to the CRC8 stage 15 in which it can be processed so as to generate the control information formed by the value k1. The acknowledge data block QDB each time generated by the generating module 10 can be output, via a connection 23, by the second generating stage SGS 18 of the generating module 10. The selection data block SDB each time output by the first generating stage FGS 6 can also be output via the connection 23.

[0029] The station 1 also includes the above-mentioned time slot counter TSC 21, which is capable of determining each time slot TS(1 . . . n . . . N) of time slot sequences, each of which consists of a given number N of successive time slots TS. For example, a time slot sequence may consist of 1, 4, 8, 16, 32, 64, 128 or 256 time slots. The time slot counter TSC 21 can be controlled by the sequencing module SM 3 via a connection 24. The clock signal CLK can be applied to the time slot counter TSC 21 via a connection 25. The relevant content 1 . . . n . . . N of the time slot counter TSC 21 can be applied, via the connection 20, to the second generating stage 18 of the generating module 10.

[0030] The station 1 also includes an encoder ENC 26, which can be supplied with the instruction data blocks generated by the first generating stage FGS 6, for example the selection data block SDB and the acknowledge data block QDB, each time generated by the generating module 10, and realize encoding of the data blocks applied thereto. The encoder ENC 26 can be controlled by the sequencing module SM 3 via a connection 27.

[0031] A modulator MOD 27, which can be supplied with the encoded data blocks, is connected to the encoder ENC 26. In the present case the modulator MOD 27 is formed by an amplitude modulation which can be supplied with a carrier signal CS and realize amplitude modulation of the carrier signal CS in dependence on the encoded data blocks supplied by the encoder ENC 26. The modulator MOD 27 are arranged to carry out a 10% amplitude modulation (ASK 10%) and output an amplitude modulated carrier signal CSM.

[0032] The station 1 includes a carrier signal generator CSG 28 for generating the carrier signal CS; this generator can be supplied with the clock signal CLK, via a connection 29, and generates the carrier signal CS in dependence on the clock signal CLK, which carrier signal also has a frequency of 13.56 MHz in this case.

[0033] Connected to the modulator MOD 27 are transmitter/receiver 30, which includes a transmitter coil 31 which can inductively transmit the amplitude modulated carrier signal CSM, output by the modulator MOD 27, to a receiver included in data carriers 2.

[0034] The transmitter/receiver 30 at the same time can receive signals inductively transmitted to the station 1 by data carriers 2. Such signals can be applied, via a connection 32, to demodulator DEM 33 of the station 1. In the present case the demodulator DEM 33 is arranged to demodulate a load modulated carrier signal CSB, because the inductive data transmission from the carriers 2 to the station 1 is performed in known manner by so-called load modulation of the carrier signal CS.

[0035] Connected to demodulator DEM 33 is a decoder DEC 34 whereby received data blocks can be decoded. The decoder DEC 34 can be controlled by the sequencing module SM 3 via a connection 35. Decoded identification data blocks IDB output by the decoder DEC 34 can be applied, via a connection 36, to the sequencing module SM 3 in order to be subjected to further processing by the sequencing module SM 3, notably in order to be stored in the memory 11 of the generating module 10 with the aid of the sequencing module SM 3.

[0036] Collision detection module CDM 37 which can be controlled by the sequencing module SM 3, via a connection 38, are connected to the decoder DEC 34. The collision detection module CDM 37 are arranged to detect collisions between two identification data blocks IDB, a collision of this kind being detected on a bit basis. Such a collision of identification data blocks IDB is liable to occur when two or more identification data blocks IDB are received in the station 1 in the same time slot. When the collision detection module CDM 37 detects such a collision of identification data blocks IDB, collision information CI is applied to the sequencing module SM 3, via a connection 39, so that the sequencing module SM 3 can perform an appropriate control operation.

[0037] The construction of the data carrier 2 will be described in detail hereinafter on the basis of the data carrier 2 shown in FIG. 2.

[0038] The data carrier 2, being constructed for contactless communication with at least one write/read station, such as the station 1 shown in FIG. 1, includes receiver/transmitter means 40 which include a transmitter coil 41 and constitute receiver means for receiving data blocks as well as transmitter means for transmitting data blocks.

[0039] The data carrier 2 includes a circuit 42, of which FIG. 2 shows only those parts which are of essential importance in the present context. The circuit 42 is constructed as an integrated circuit. The circuit 42 includes a first terminal 43 and a second terminal 44, which terminals are connected to the receiver/transmitter 40. In this case the terminals 43 and 44 form receiving connectors for receiving data blocks received by the receiver/transmitter 40 as well as output connectors for outputting data blocks to be transmitted by the receiver/transmitter 40.

[0040] The circuit 42 includes sequencing module SM 45 whereby a plurality of routines and functions of the data carrier 2 can be controlled; however, only the routines and functions thereof which are of relevance in the present context will be described in detail hereinafter.

[0041] The circuit 42 also includes a memory 46 which is arranged to store the identification data block IDB which characterizes the data carrier 2. The identification data block IDB consists of, for example a total of 8 bytes of 8 bits each. The memory 46 can be controlled by the sequencing module SM 45, via a connection 47, so as to output the identification data block IDB, stored in the memory 46, via a connection 48.

[0042] The memory 46 can also be controlled by the sequencing module SM 45 via a further connection 49. The memory 46 can be supplied, via the connection 49, with two bit addresses BA(HV)1 and BA(HV)2, each of which corresponds to the hash value HV and forms an initial address for a part PM1, PM2, respectively, of the identification data block IDB stored in the memory 46. In the present case the first bit address BA(HV)1 is formed directly by the hash value HV. The second bit address BA(HV)2 is formed by adding a given number, for example the number “8”, to the hash value HV. The hash value HV is transmitted to the data carrier 2 by the station 1 of FIG. 1 while using the selection data block SDB, so that the hash value HV present in the station 1 and the hash value present in the data carrier 2 are identical. The part PM1 or PM2 of the identification data block IDB, determined by the applied bit address BA(HV)1 or BA(HV)2, respectively, can be output via a connection 50 by driving the memory 46, via the connection 49, with one of the two bit addresses BA(HV)1 and BA(HV)2.

[0043] The data carrier 2 includes demodulator DEM 51 which is connected to the first terminal 43 and is suitable for demodulating the amplitude modulated carrier signal CSM transmitted by a station 1. The demodulator DEM 51 outputs the data blocks DB, transmitted to the data carrier 2, in demodulated but still encoded form, via an output 52.

[0044] The data carrier 2 also includes clock signal regenerating module CSR 53 which are also connected to the first terminal 43. The clock signal regenerating module CSR 53 can regenerate the clock signal CLK from the received amplitude modulated carrier signal CSM, so that the clock signal CLK is available in the data carrier 2 as well as in the station 1 transmitting the modulated carrier signal CSM. The regenerated clock signal CLK is applied to the sequencing module SM 45 via a connection 54.

[0045] The data carrier 2 also includes DC voltage generator DCVG 55 which is also connected to the first terminal 43 and can generate, while using the amplitude modulated carrier signal CSM, a DC supply voltage V which serves to feed the entire circuit 42. It is to be noted that the DC voltage generator DCVG 55 includes a voltage limiter in order to prevent in known manner the occurrence of an excessive supply voltage V.

[0046] A reset signal generator RSG 57 is connected to the DC voltage generator DCVG 55, via a connection 51, in order to generate a reset signal RS upon occurrence of a DC supply voltage V as is the case when the data carrier 2 enters the communication range of a station 1, said reset signal being capable of initiating a so-called “power-on-reset”. The reset signal RS can be applied to the sequencing module SM 45 via a connection 58.

[0047] The data carrier 2 includes a series of decoders for the decoding of encoded data blocks which are output via the output 52 of the demodulator DEM 51. A decoder DEC 59 is for decoding a selection data block SDB and decoder DEC 60 is for decoding an acknowledge data block QDB. The inputs of the decoders DEC 59 and DEC 60 are connected to the output 52 of the demodulator DEM 51. The decoder DEC 59 can be controlled by the sequencing module SM 45 via a connection 61, and the decoder DEC 60 can be controlled thereby via a connection 62. The outputs of the decoders DEC 59 and DEC 60 are connected, via connections 63 and 64, to the sequencing module SM 45 so that the decoded data blocks SDB and QDB can be applied to the sequencing module SM 45 for the purpose of further processing.

[0048] To the output of the decoder DEC 59 there are connected a detection module DM 65 which can be controlled by the sequencing module SM 45 via a connection 66. The detection module DM 65 is arranged and constructed so as to detect the hash value HV which is contained in a selection data block SDB transmitted to the data carrier 2. The hash value HV detected by the detection module DM 65 can be output by the detection module DM 65, via a connection 67, to the sequencing module SM 45 in order to be processed in the sequencing module SM 45.

[0049] To the output of the decoder DEC 60 there are connected a test module TM 68 which can be controlled by the sequencing means 45 via a connection 69. The test module TM 68 are constructed in such a manner that they can test the validity of an acknowledge data block QDB transmitted by a station 1 and received by the data carrier 2. In the present case the test module TM 68 is constructed as a comparator. In case a received acknowledge data block QDB is recognized as a valid acknowledge data block QDB, the test module TM 68 generates an “acknowledge valid” signal QV which can be applied, via a connection 70, to the sequencing module SM 45 for further processing.

[0050] The circuit 42 of the data carrier 2 also includes an encoder ENC 71, to the input of which there is connected the connection 48. The encoder ENC 71 can be controlled by the sequencing module SM 45 via a connection 72. The encoder ENC 71 is capable of encoding the identification data block IDB read from the memory section 46, as well as data blocks read from a further memory which is not shown. After completion of the encoding by the encoder ENC 71, the encoded data blocks can be applied to a modulator MOD 73. In the modulator MOD 73, an auxiliary carrier signal is subjected in known manner to a modulation in conformity with the encoded data blocks, after which the modulated auxiliary carrier signal is applied, via the first terminal 43, to the receiver/transmitter 40 so as to be inductively transmitted to a station 1.

[0051] The circuit 42 of the data carrier 2 also includes a so-called CRC8-stage 74 which can be controlled by the sequencing module SM 45 via a connection 75. The CRC8-stage 74 can receive, via the connection 50, the each time selected part PM1 or PM2 of the identification data block IDB which can be read, by the sequencing module SM 45, from the memory 46 in conformity with the hash value HV detected by the detection module DM 65 and supplied by the sequencing module SM 45. The part PM1 or PM2 each time applied to the CRC8 stage 74 is shifted through the CRC8 stage 74; during this operation an algorithm that can be realized by the CRC8 stage 74 is executed, after which a given value k1 or k2 is obtained at the output of the CRC8 stage 74, said values k1 and k2 being determined by the part PM1 or PM2, respectively, shifted through the CRC8 stage 74. The value k1 is used for generating the acknowledge data block QDB, as will be described in detail hereinafter. The value k2 is stored in a time slot register TSR 76 which can be controlled by the sequencing module SM 45 via a connection 77.

[0052] The circuit 42 of the data carrier 2 also includes a time slot counter TSC 78 which can be controlled by the sequencing module SM 45 via a connection 79. The time slot counter TSC 78 is arranged to determine each time slot TS(1 . . . n . . . N) of possibly repeatedly successively running time slot sequences. Each of these time slot sequences consists of a given number N of successive time slots TS. The number N, that can be determined by the time slot counter TSC 78, and the length of successive time slots TS of time slot sequences always correspond to the number and the length of the time slots TS of time slot sequences determined by the time slot counter 24 of a station 1. The time slot counter TSC 78 can be supplied, via a further connection 80 which is branched off from the connection 54, with the clock signal CLK regenerated by the clock signal regenerator 53. The time slot counter TSC 78 determines each time slot TS of successively running time slot sequences on the basis of the regenerated clock signals CLK. The relevant content 1 . . . n . . . N of the time slot counter TSC 78 can be applied from the output of the time slot counter TSC 78, via a connection 81, to the sequencing module SM 45 so that the relevant contents are available for control purposes in the sequencing module SM 45.

[0053] The circuit 42 of the data carrier 2 also includes a comparator 82 which can be controlled by the sequencing module SM 45 via a connection 83. The comparator 82 can be supplied, via a connection 84, with the content k2 of the time slot register TSR 76 as well as, via a connection 85 which is branched off from the connection 81, with the content 1 . . . n . . . N of the time slot counter TSC 78. The comparator 82 provides comparison of the contents k2 and 1 . . . n . . . N received and outputs, in the case of corresponding received contents, a comparator signal COS to the sequencing module SM 45 via a connection 86. Communication between the carrier 2 and a station 1 can be enabled during a given time slot TS in dependence on the comparator signal COS, i.e. during the time slot TS(k2) fixed by the value k2.

[0054] The circuit 42 of the data carrier 2 also includes a generating stage GS 87 for generating an acknowledge data block QDB. The generating stage GS 87 can be controlled by the sequencing module SM 45 via a connection 88. The generating stage GS 87 can be supplied, via a connection 89, with control information in the form of the value k1 generated by the CRC8 stage 74. The generating stage GS 87 is constructed in such a manner that it is suitable to generate the acknowledge data block QDB having a bit configuration determined by the value k1 output as control information by the CRC8 stage 74. The acknowledge data block QDB generated by the generating stage GS 87 can be output via a connection 90 which is connected to the test module TM 68. The test module TM 68, constructed in the form of a comparator, can be supplied with the acknowledge data block QDB generated by the generating stage GS 87 and with the acknowledge data block QDB transmitted by a station 1, received by the circuit 42 and decoded by the decoder DEC 60. The test module TM 68 compares the two acknowledge data blocks QDB, the test module TM 68 output the “acknowledge valid” signal QV in the case of correspondence of the two acknowledge data blocks QDB, which signal QV can be applied to the sequencing module SM 45 via the connection 70.

[0055] The decoder DEC 59 decodes a selection data block SDB which is transmitted by a station 1 in order to initiate a selection operation and is received via the terminal 43, the selection data block SDB enabling the selection of the data carrier 2 from among a plurality of data carriers 2.

[0056] The encoder ENC 71 encodes an identification data block IDB which is stored in the circuit 42 of the data carrier 2 and the modulator 73 modulates the identification data block IDB where, during a given time slot TS of a time slot sequence, the identification data block IDB is applied to the receiver/transmitter 40, via the terminal 33, for transmission to a station 1. The given time slot should be the n^thtime slot, where 1≦n≦N and n=k2.

[0057] The decoder DEC 60, after correct reception in a station 1 of an identification data block IDB transmitted to this station 1 by the data carrier 2, decodes an acknowledge data block QDB which is transmitted by the station 1 to the data carrier 2 and is received via the terminal 43, which acknowledge data block can set the circuit 42 of the data carrier 2 to a “selected” state.

[0058] The time slot register TSR 76 in the data carrier 2 which can fix, after the processing of the acknowledge data block QDB by the decoder DEC 60, the each time n^thtime slot TS of successively generated time slot sequences for the circuit 42 of the data carrier 2, or the data carriers 2, where n=k2.

[0059] The comparator 82 and the sequencing module SM 45 constitute a controller 91 whereby, after fixation of the circuit 42 of the data carrier 2 to the each time n^thtime slot TS, communication can be enabled between the data carrier 2 and a station 1 only during the each time n^thtime slot TS fixed for the circuit 42 of the data carrier 2, where n=k2.

[0060] The memory 46 and the CRC8 stage 74 and the generating stage GS 87 collectively generate the acknowledge data block QDB associated with the data carrier 2 or the circuit 42.

[0061] The method for communication between the station 1 as shown in FIG. 1 and the data carrier 2 as shown in FIG. 2 will be described in detail hereinafter on the basis of a communication operation which is chosen by way of example.

[0062] Such a communication operation can be automatically started, for example by sequencing module SM 3 of the station 1, at regularly successive time intervals. After the start of a communication operation, a selection data block SDB is generated by the first generating stage FGS 6 of the station 1 in order to initiate a selection operation. Subsequently, the previously generated selection data block SDB is encoded by the encoder ENC 26; this means at the same time that the encoded selection data block SDB is amplitude modulated by the modulator MOD 27 and is subsequently transmitted, by the transmitter/receiver 30, to all data carriers 2 present within the communication range of the station 1, so also to the data carrier 2 shown in FIG. 2.

[0063] Subsequently, the content of the time slot counter TSC 24 of the station 1 is set to the value “1”, the first time slot TS1 of a time slot sequence then running. The content “1” of the time slot counter TSC 24 is applied to the second generating stage SGS 18 via the connection 20.

[0064] After the transmission of the selection data block SDB, carried out by the station 1 at the beginning of the communication operation, the transmitted selection data block SDB is received by the receiver/transmitter 40 of the data carrier 2, demodulated by the demodulator DEM 51 and decoded by the decoder DEC 59. On the basis of the received, demodulated and decoded selection data block SDB, the detection module DM 65 detects the hash value HV, transmitted to the data carrier 2 by the station 1 within the selection data block SDB; this hash value is then applied to the sequencing module SM 45.

[0065] Subsequently, the sequencing module SM 45 generate the second bit address BA(HV)2 which is dependent on the hash value HV and is applied to the memory 46, thus fixing the part PM2 of the identification data block IDB stored in the memory 46. Subsequently, the value k2, for example being the value k2=1 in the present case, is determined by the CRC8 stage 74. Subsequently, the value k2=1 is stored in the time slot register TSR 76 and hence the first time slot TS1 is fixed for the data carrier 2. The value k2 generated as the control information by the CRC8 stage 74, in this case being the value k2=1, is applied, via the connection 84, to the comparator 82 which in this case receives the value n=1 from the time slot counter TSC 78 while the first time slot TS1 is running. The two values applied to the comparator 82 are thus equal, with the result that the comparator 82 applies the comparator signal COS to the sequencing module SM 45 via the connection 86. As a result, the sequencing module SM 45 control, via the connection 46, the memory 46 in such a manner that the memory 46 applies the identification data block IDB, being associated with the data carrier 2 and being characteristic of this data carrier 2, to the encoder ENC 71 via the connection 48. Subsequently, the identification data block IDB is encoded by the encoder ENC 7171, after which it is modulated by the modulator MOD 73 and applied from the modulator MOD 73 to the transmitter/receiver 40 in order to be transmitted to the station 1.

[0066] After application of the detected hash value HV to the sequencing module SM 45, subsequent to the generating of the second bit configuration BA(HV)2 by the sequencing module SM 45, in this case the first bit address BA(HV)1 which is dependent on the hash value HV is generated and applied to the memory 46, thus fixing the part PM1 of the identification data block IDB stored in the memory 46. Subsequently, the value k1 is determined as the control information by the CRC8 stage 74. Subsequently, the value k1 is applied to the generating stage GS 87, with the result that the generating stage GS 87 generates the acknowledge data block QDB whose bit configuration is determined by the part PM1 of the identification data block IDB. The acknowledge data block QDB generated by the generating stage GS 87 is applied to the test module TM 68 via the connection 90.

[0067] After the transmission of the selection data block SDB it may occur that during the first time slot TS1 either no data carrier 2 or just one data carrier 2 or also more than one data carrier 2 receives the selection data block SDB and responds to the received selection data block SDB while transmitting its associated identification data block IDB, each of which has a given bit configuration, to the station 1 in response to the selection data block SDB transmitted by the station 1.

[0068] An identification data block IDB transmitted by a data carrier 2 is received by the station 1, that is to say by the transmitter/receiver 30. Subsequently, each identification data block IDB received is demodulated by the demodulator DEM 33 and each identification data block IDB received is decoded by the decoder DEC 34. Subsequently, the collision detection module CDM 37 detects whether a collision has taken place between at least two identification data blocks IDB or whether no identification data block IDB has even been received and decoded. When this is the case, the collision detection module CDM 37 apply collision information CI to the sequencing module SM 3, with the result that no identification data block IDB is applied to the memory 11 via the connection 12; therefore, subsequently no acknowledge data block QDB will be generated by the generating module 10.

[0069] However, if the collision detection module CDM 37 detects that only one identification data block IDB has been received and decoded by the decoder DEC 34, the decoded identification data block IDB is applied, via the connection 36, to the sequencing module SM 3 which ensure that subsequently the identification data block IDB received in the first time slot TS1 is applied to the memory 11 via the connection 12. Subsequently, using the hash value HV which is contained in the sequencing module SM 3 and has already been transmitted to the data carrier 2 by way of the selection data block SDB, and also using the bit address BA(HV)1, corresponding to the hash value HV, the part PM1 of the identification data block IDB is selected so as to be applied to the CRC8 stage 15. Subsequently, the selected part PM1 of the identification data block IDB is applied from the memory 11, via the connection 14, to the CRC8 stage 15, so that subsequently at the output 17 of the CRC8 stage there is obtained the value k1 which is derived in dependence on the part PM1 and serves as control information which is applied to the second generating stage SGS 18 in order to generate the acknowledge data block QDB. Subsequently, using the second generating stage SGS 18, an acknowledge data block QDB, having a bit configuration determined by the value k1 and being associated with the data carrier 2 having transmitted its identification data block to the station 1 during the first time slot TS1, is generated in response to the received identification data block IDB. The bit configuration of this acknowledge data block QDB is formed while utilizing only the part PM1 of the identification data block IDB, associated with the relevant data carrier 2, which was stored in the memory 11.

[0070] Subsequently, the generated acknowledge data block QDB is applied to the encoder ENC 26 via the connection 23. The encoder ENC 26 provide encoding of the acknowledge data block QDB, after which the decoded acknowledge data block QDB is modulated by the modulator MOD 27; the encoded and modulated acknowledge data block QDB is then transmitted, by the transmitter/receiver 30, to the data carrier 2 with which the generated acknowledge data block QDB is associated.

[0071] Subsequently, the transmitted acknowledge data block QDB is also received by the data carrier 2 with which the acknowledge data block QDB transmitted by the station 1 is associated. The reception of the acknowledge data block QDB associated with the data carrier 2 of FIG. 2 takes place by the receiver/transmitter 40 which apply the received acknowledge data block QDB to the demodulator DEM 51. The demodulator DEM 51 applies the demodulated acknowledge data block QDB to the decoder DEC 60 which provides decoding and the decoded acknowledge data block QDB is subsequently applied to the test module TM 68.

[0072] When the acknowledge data block QDB transmitted to the data carrier 2 by the station 1 is applied to the test module TM 68, the test module TM 68 compares the acknowledge data block QDB transmitted to the data carrier 2 by the station 1 with the acknowledge data block QDB generated by the generating stage GS 87. If no disturbing effects have been exerted on the acknowledge data block QDB transmitted by the station 1 to the data carrier 2, the two acknowledge data blocks QDB applied to the test module TM 68 will be identical; the test module TM 68 then outputs the “acknowledge valid” signal QV to the sequencing module SM 45. This “acknowledge valid” signal, can set the data carrier 2 to a “selected” state.

[0073] After the transmission of the selection data block SDB, it may occur that two data carriers 2 receive the transmitted selection data block SDB in the first time slot TS1, each data carrier containing a respective identification data block IDB1 and IDB2, of which both parts PM2, however, correspond; consequently, the value k2=1 is determined for both data carriers 2 and hence both data carriers 2 transmit their identification block IDB1, IDB2 in the first time slot TS1. In that case it may occur that a first one of these two data carriers 2 is situated near enough to the station 1, but the second one of these data carriers is situated too far from the station 1, so that the station 1 receives only the identification data block IDB1 from the first data carrier 2. Using the identification data block IDB1 received from the first data carrier 2, the control information corresponding to the part PM1 of this identification data block IDB1, i.e. the value k1, is determined and an acknowledge data block QDB1 is generated whose bit configuration is determined by this value k1, so by the part PM1. This acknowledge data block QDB1, whose bit configuration is determined by the value k1, is transmitted by the station 1 to the first data carrier 2 as well as to the second data carrier 2. In these two data carriers a respective acknowledge data block QDB1 and QDB2 is also generated, their bit configurations being dependent on the part PM1 of their identification data blocks IDB1 and IDB2, respectively. Even though the part PM2 of the identification data blocks IDB1 and IDB2, respectively, which is decisive as regards the fixation of the first time slot TS1 is the same for both data carriers 2, it has to be assumed with the greatest likelihood that, despite the correspondence of the parts PM2, the parts PM1 of the identification data blocks IDB1 and IDB2 of the two data carriers 2 are different, so that it must be assumed that the acknowledge data block QDB1 is generated only in the first data carrier 2 and that a different acknowledge data block QDB2 is generated in the second data carrier 2, so that the acknowledge data block QDB1 transmitted by the station 1 is valid only for the first data carrier 2 which is situated near enough to the station 1, and hence only the data carrier 2 situated near enough to the station 1 is acknowledged, i.e. set to its “selected” state, whereas the second data carrier 2 which is situated further from the station 1 is not acknowledged. Undue acknowledgement of a data carrier 2 which is situated too far from a station 1 is thus definitely precluded. Thus, despite the use of acknowledge data blocks QDB having a short data block length of only, for example 8 bits, correct and error-free acknowledgement of only a single data carrier 2 is always ensured, even if a data carrier 2 which is not recognized by the station 1 is situated within the communication range of the station 1; because of its comparatively large distance from the station 1, such a non-recognized data carrier 2 can receive data blocks from the station 1 but cannot transmit data blocks to the station 1.

[0074] The operation described above for the first time slot TS1 is carried out for all further time slots TS2, TS3 to TSN, after which a communication operation for the selection and acknowledgement of data carriers 2 is terminated.

[0075] It is to be noted that, after such a communication operation for the selection and acknowledgement of data carriers 2 which are then in their “selected” state, further communication operations may be executed, for example a read operation for reading data, stored in data carriers 2, from the selected data carriers 2 during the read operation so as to transmit this data to the station 1, or a write operation during which data contained in the station 1 is transmitted to the selected data carriers 2 and written into memories of these data carriers 2.

[0076] As will be apparent from the foregoing description, in the station 1 shown in FIG. 1 and in the data carrier 2 shown in FIG. 2 it is simply achieved that for the acknowledgement of the selection of a data carrier 2 an acknowledge data block QDB which is associated exclusively with the relevant data carrier 2 is transmitted to this data carrier 2 by the station 1, and that this is advantageously achieved by an acknowledge data block QDB having only a short data block length, because the acknowledge data block QDB is formed while utilizing only a part PM1 of the identification data block IDB associated with the relevant data carrier 2. The advantages of such an acknowledge data block QDB of only short data block length reside mainly in an as short as possible transmission time as required for the transmission from a station 1 to a data carrier 2, and in the fact that as few modulation steps as possible suffice for the transmission of such acknowledge data block QDB from a station 1 to a data carrier 2, this is very advantageous with a view to achieving as low as possible levels of the side bands of the carrier signal CS used for the transmission.

[0077] The scope of protection of the invention is not limited to the examples given herein. The invention is embodied in each novel characteristic and each combination of characteristics. Reference numerals in the claims do not limit the scope of protection thereof. The use of the term “comprising” does not exclude the presence of elements other than those mentioned in the claims. The use of the word “a” or “an” before an element does not exclude the presence of a plurality of such elements.