US 6,583,466 B2Grant
Vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions
Issue Date:2003-06-24
•16 Claims
•6 Drawing Sheets
Abstract
A vertical transistor memory device includes FET cells formed in rows and columns with the rows orthogonally arranged relative to the columns. Several cells in a single row have a common source region and adjacent cells have a common drain region FOX regions are formed between the rows. A set of trenches are formed with sidewalls and a bottom in a semiconductor substrate with threshold implant regions formed in the sidewalls. Doped drain regions are formed near the surface of the substrate and doped source regions are formed in the base of the device below the trenches with oppositely doped channel regions therebetween. A tunnel oxide layer is formed over the substrate including the trenches aside from FOX regions. Floating gates of doped polysilicon are formed over the tunnel oxide layer in the trenches. An interelectrode dielectric layer covers the floating gate layer. Control gate electrodes of doped polysilicon are formed over the interelectrode dielectric layer. Spacers are formed adjacent to the sidewalls of the control gate electrode.
Metadata
Assignee
- Taiwan Semiconductor Manufacturing Company
Inventors
- Chrong Jung Lin
- Shui-Hung Chen
- Di-Son Kuo
Application Information
Application Number:US 10/117,889
Filing Date:2002-04-08
Priority Date:1998-03-05
Art Unit:7
Classifications
IPC:
H01L 2976
Field of Search:
438201438211
Patent Drawings (6 sheets)
Description
[0002] This is a division of patent application Ser. No. 09/035,058, filing date Mar. 5, 1998 now U.S. Pat. No. 6,087,222, Method Of Manufacture Of Vertical Split Gate Flash Memory Device And Device Manufactured Thereby, assigned to the same assignee as the present invention.
Background of the Invention
[0003] 1. Field of the Invention
[0004] This invention relates to the manufacture of semi-conductor memory devices and more particularly to a method of manufacture of vertical FET devices formed in trenches in a semiconductor substrate and the devices formed thereby.
[0005] 2. Description of Related Art
[0006] Currently, split gate flash memory devices have a misalignment problem and scaling down issues.
[0007] U.S. Pat. No. 5,108,938 of Solomon for “Method of Making a Trench Gate Complimentary Metal Oxide Semiconductor Transistor” shows a FET (Field Effect Transistor) with the source (S) and drain (D) regions on the substrate surface separated by a trench.
[0008] U.S. Pat. No. 5,391,506 of Tada et al. for “Manufacturing Method for Semiconductor Devices with Source/Drain Formed in Substrate Projection” shows a method for semiconductor devices with source/drain formed in substrate projection. A projection is formed in a substrate by anisotropic etching and a transistor is contained in the projection. The central portion of the projection covered with a gate electrode is formed as a channel region, and drain and source regions are formed on both sides of the projection by oblique ion implantation with the gate electrode as a mask. However, this reference differs from the configuration of the invention's split gate Flash with the source region at the bottom of the trench and the drain at the substrate surface.
[0009] U.S. Pat. No. 5,312,767 of Shimizu et al. for “MOS Type Field Effect Transistor and Manufacturing Method Thereof” shows a vertical SOI (Silicon On Insulator) transistor that has the source S and D regions on opposite ends of a trench. However the device is not a Flash memory.
[0010] U.S. Pat. No. 5,229,310 of Sivan “Method of Making a Self-Aligned Vertical Thin-Film Transistor in a Semiconductor Device” shows an EEPROM with a vertical orientation in a trench.
Summary of the Invention
[0011] Objects of this invention are as follows:
[0012] 1. Scaling down the size of split gate flash memory devices.
[0013] 2. Providing devices without a misalignment issue for the polysilicon 1 layer and the polysilicon 2 mask.
[0014] 3. The cell area can be compared with stacked gate flash memory.
[0015] A vertical, split gate, flash memory device in accordance with this invention has the features as follows:
[0016] 1. Small cell area;
[0017] 2. No misalignment;
[0018] 3. high channel current.
[0019] In accordance with this invention a vertical transistor memory device is provided with FET cells formed in rows and columns with the rows orthogonally arranged relative to the columns. Several cells in a single row have a common source region and adjacent cells have a common drain region. Cells in a single column have separate source regions and separate drain regions. FOX regions are formed between the rows. A set of trenches with sidewalls and a bottom are formed in a semiconductor substrate with threshold implant regions formed in the sidewalls. Doped drain regions are formed near the surface of the substrate and doped source regions are formed in the base of the device below the trenches with oppositely doped channel regions therebetween. A tunnel oxide layer is formed over the substrate including the trenches aside from FOX regions. Floating gates of doped polysilicon are formed over the tunnel oxide layer in the trenches. An interelectrode dielectric layer composed of ONO covers the floating gate layer. Control gate electrodes of doped polysilicon are formed over the interelectrode dielectric layer. Spacers are formed adjacent to control gate electrode sidewalls.
Brief Description of the Drawings
[0020] The foregoing and other aspects and advantages of this invention are explained and described below with reference to the accompanying drawings, in which:
[0021] FIGS. 1A-1L show sectional elevational views of a device in accordance with this invention, taken along line 4-4′ in FIG. 3, of various stages of the manufacturing process for producing a device in accordance with this invention.
[0022] FIGS. 2A-2L show sectional elevational views of a device in accordance with this invention, taken along line 5-5′ in FIG. 3, of various stages of the manufacturing process for producing a device in accordance with this invention.
[0023] FIG. 3 shows a plan sectional view of the device of FIGS. 1L and 2L as well as FIGS. 4 and 5 taken along line 3-3′ in FIG. 4.
[0024] FIG. 4 shows a sectional view of the device of FIG. 3 taken along line 4-4′ in FIG. 3 showing the flow through the channel region between the source region and the drain regions.
[0025] FIG. 5 shows a sectional view of the device 10 of FIG. 3 taken along line 5-5′ in FIG. 3 showing the flow through the channel region between the source region and the drain regions with a control gate bridging across a column from row to row.
Description of the Preferred Embodiment
[0026] FIGS. 1A-1L show sectional elevations of a device 10 in accordance with this invention, taken along line 4-4′ in FIG. 3, of various stages of the manufacturing process for producing a device in accordance with this invention.
[0027] FIGS. 2A-2L show sectional elevations of a device 10 in accordance with this invention, taken along line 5-5′ in FIG. 3, of various stages of the manufacturing process for producing a device in accordance with this invention.
[0028] FIGS. 1A and 2A show the device 10 after the first and second steps of the process.
[0029] 1. Wafer Start
[0030] The first step is the “wafer start step” in which a silicon semiconductor substrate 11 is provided.
[0031] 2. Active Area Definition
[0032] The second step is definition of the “active area (OD) in a Pad oxide/Nitride Deposition step in which a thin pad oxide layer 12 and a silicon nitride mask NI with OD openings therethrough have been applied to substrate 11.
[0033] 3. Field Oxidation
[0034] FIGS. 1B and 2B show the device 10 after the third step in which a conventional field oxidation process has formed the FOX (Field OXide) regions 16 have been formed, as shown in FIG. 2B.
[0035] 4. Stripping Nitride Mask and Pad Oxide Layer
[0036] FIGS. 1C and 2C show the device 10 after the fourth step in which the silicon nitride mask NI has been stripped from device 10. In addition, in this step, the pad oxide layer 12 has been stripped from device 10.
[0037] 5. Trench Channel Etch
[0038] FIGS. 1D and 2D show the device 10 after the fifth step in which a photoresist trench mask PR1 has been formed over device 10 including the FOX regions 16 and the exposed surfaces of substrate 11. Mask PR1 has a set of windows W therethrough down to the top surface of substrate 11. Windows W were then used to etch trenches 18 deep into the substrate 11 to a depth of from about 4,000 Å to about 9,000 Å. Trenches 18 have a width from about 3,000 Å to about 10,000 Å across the page and a length from about 3,000 Å to about 10,000 Å extending back into the page. Vertical transistors will be formed in the trenches 18. The trenches 18 are etched by a dry process such as RIE (Reactive Ion Etching) or plasma etching.
[0039] 6. Source Connection Region Implant
[0040] FIGS. 1E and 2E show the device 10 after the sixth step in which P type dopant CI is implanted, in an anisotropic substantially vertical implant, into the base regions 19 of the trenches 18 to provide a source connection implant.
[0041] The phosphorus source connection region 19 was ion implanted into the base regions 19 of phosphorus type dopant with a dose from about 1 E 14 ions/cm2to about 1 E 15 ions/cm2at an energy from about 20 keV to about 60 keV. After annealing the concentration of phosphorus dopant in the source connection region 19 was from about 1 E 19 atoms/cm3to about 4 E 20 atoms/cm3.
[0042] 7. Sacrificial Oxide
[0043] Referring to FIGS. 1F and 2F, device 10 is shown after a SAC (Sacrificial) oxide layer SO was formed over the exposed surfaces of silicon substrate 11, aside from FOX regions 16, covering the substrate 11 and the sidewalls and bottom of the trenches 18 with a thin silicon oxide film with a thickness from about 100 Å to about 250 Å.
[0044] 8. Threshold Voltage Implant
[0045] Referring again to FIGS. 1F and 2F, following formation of the SAC layer SO, a Vth (Threshold Voltage) rotary oblique angular ion implant of boron difluoride BF2P type dopant is for the channel regions of the FET devices to be formed is implanted in the exposed surfaces of the substrate 10, especially including the sidewalls of the trenches 18. The FOX regions 16 in FIG. 2F prevent ion implantation into the surfaces the substrate 11 below them.
[0046] The sidewalls of the trenches 18 in substrate 11 were ion implanted at an oblique angle with a dose of BF2dopant from about 1 E 12 ions/cm2to about 7 E 13 ions/cm2at an energy from about 15 keV to about 45 keV. After annealing the concentration of the boron dopant in the sidewalls of the substrate 11 was from about 8 E 16 atoms/cm2to about 8 E 17 atoms/cm2. As a result, P type dopant has formed regions 24 in the substrate 11 where source regions S will be formed later with implanted N type dopant as shown in FIGS. 1G and 2G.
[0047] 9. Source/Drain Implant
[0048] Referring to FIGS. 1G and 2G, source/drain (S/D) regions S and D are formed by ion implanting N type dopant in an anisotropic substantially vertical implant into the exposed surfaces of substrate 11 aside from the FOX regions 16. Again, the FOX regions 16 in FIG. 2G prevent ion implantation into the surfaces the substrate 11 below them.
[0049] The source/drain regions S and D were ion implanted with a dose of arsenic, phosphorus or antimony N type dopant from about 5 E 14 ions/cm2to about 5 E 15 ions/cm2at an energy from about 20 keV to about 45 keV. After annealing the concentration of arsenic, phosphorus or antimony N type dopant in the source/drain regions S/D were from about 5 E 19 atoms/cm3to about 5 E 20 atoms/cm3.
[0050] The connect regions 27 are shown at the base of the trenches below the sacrificial oxide layer SO.
[0051] 10. Stripping Sacrificial Oxide Layer
[0052] Referring to FIGS. 1H and 2H, the next step is to strip the sacrificial oxide layer SO from the device 11.
[0053] 11. Tunnel Oxide
[0054] Referring again to FIGS. 1H and 2H, device 10 is shown after a tunnel oxide layer 22 was formed over the exposed surfaces of silicon substrate 11 regions 16, aside from FOX regions covering the substrate 11 and the sidewalls and bottom of the trenches 18 with a thin silicon oxide film with a thickness from about 70 Å to about 150 Å.
[0055] The connect regions 27 are shown at the base of the trenches below the tunnel oxide layer 22.
[0056] 12. Floating Polysilicon Deposition
[0057] Referring once more to FIGS. 1H and 2H, device 10 is shown after a first polysilicon layer PS1 was formed over the device 10 on substrate 11 covering the tunnel oxide layer 22 and FOX regions 16 and filling trenches 18. The first polysilicon layer PS1 has a thickness from about 1,000 Å to about 4,000 Å. The polysilicon layer PS1 is doped with a conventional dopant to provide electrical conductivity as is conventional with polysilicon metallization.
[0058] 13. Floating Polysilicon Etch
[0059] Referring to FIGS. 1I and 2I, device 10 is shown after the first polysilicon layer PS1 has been etched by RIE or plasma etching until layer PS1 is lowered down to well below the top of the trenches 18, with all of layer PS1 removed from the surface of substrate 11 and FOX regions 16. As can be seen in FIGS. 1I and 2I, the layer PS1 fills about half of the depth of trenches 18 and the new structures created by the etching are floating gates FG formed from what remains of the first polysilicon layer PS1.
[0060] 14. Intergate Dielectric Deposition
[0061] Referring once more to FIGS. 1I and 2I, device 10 is shown after formation of a dialectic layer 30 which is preferably an ONO (Oxide/Nitride/Oxide) layer. In that case layer 30 comprises thin layers of SiO/Si3N4/SiO forming a set of intergate (interpolysilicon) dielectric structures 30 with an overall thickness from about 120 Å to about 250 Å. The ONO layer 30 can be formed by the process steps as follows:
| O | Thermal oxide thickness of about 80 Å to about 150 Å | |
| 900 to 1000° C., | ||
| N | Nitride by LPCVD at 700-800° C. thickness of about | |
| 100 Å to about 150 Å, | ||
| O | thermal oxidation or CVD thickness of about 20-50 Å | |
| at about 900° C. for 10 minutes. | ||
[0062] 15. Control Polysilicon Deposition
[0063] Referring once more to FIGS. 1J and 2J, device 10 is shown after a second polysilicon layer PS2 was formed over the device 11 covering the interpolysilicon layer 30 nearly filling trenches 18 to provide a layer to be patterned into the control gate electrodes of the device 10. The second polysilicon layer PS2 has a thickness from about 1,500 Å to about 3,000 Å. The polysilicon layer PS2 is doped with a conventional dopant to provide electrical conductivity as is conventional with polysilicon metallization.
[0064] 16. Control Polysilicon Mask
[0065] Referring to FIGS. 1K and 2K, device 10 is shown after formation of control gate mask PR2.
[0066] 17. Control Polysilicon Etch
[0067] Referring to FIGS. 1K and 2K, device 10 is shown after the second polysilicon layer PS2 has been etched by RIE or plasma etching until layer PS2 has been patterned in the pattern of mask PR2 into the control gate electrodes CG.
[0068] 18. Control Polysilicon Mask
[0069] Referring to FIGS. 1L and 2L, device 10 is shown after stripping of control gate mask PR2 leaving the control gate electrodes CG exposed.
[0070] 19. Spacer Glass Deposition
[0071] Then again referring to FIGS. 1L and 2L, a spacer glass layer 34 is formed over the entire device 10 covering the drain regions D, the exposed sidewalls of the ONO layer 30 and the control gates CG. A conventional TEOS process can be employed to form the glass spacer layer. Note that the FOX region 16 is formed between the two rows of cells which have separate source regions S and separate adjacent drain regions D, as shown in FIG. 2L, but there is no FOX region 16 between the cells in a column as shown in FIG. 1L, where a common source region S is provided and a common drain D extends between adjacent cells.
[0072] 20. Spacer Etch
[0073] Finally, the spacer layer 34 is etched back to form the spacers 34 adjacent to the sidewalls of the ONO layer 20 and the control gate electrodes CG in the conventional manner.
[0074] FIG. 3 shows a plan sectional view of the device 10 of FIGS. 1L and 2L as well as FIGS. 4 and 5 taken along line 3-3′ in FIG. 4. Two horizontal rows R1 and R2 of three FET devices each are shown in three vertical columns C1, C2 and C3 with drain regions D located between the trenches indicated by the nested squares in the center square of which are the sections of the control gates CG surrounded by the ONO regions 30. Extending vertically are the portions of the control gates CG which are shown in phantom as they have been cut away by the section which looks below the surface of the device 10 with the tops of the control gates cut away to shown the ONO layers, etc. The spacers 34 are shown on the sidewalls of the control gates CG.
[0075] FIG. 4 shows a sectional view of the device 10 of FIG. 3 taken along line 4-4′ in FIG. 3 showing three cells all of which are in row 1 and respectively in columns C1-C3 with no FOX regions therebetween. FIG. 4 also shows the flow F through the channel region CH between the source region S and the drain regions D. It can be seen that there is a single buried source line S extending along between the three FET devices in row R1. There is a common parallel source line S extending along between the three FET devices in row R2.
[0076] FIG. 5 shows a sectional view of the device 10 of FIG. 3 taken along line 5-5′ in FIG. 3 showing the flow F through the channel region CH between the source region S and the drain regions D with the control gate CG bridging across the column C2 from row R2 to row R1. Note that as in FIG. 2L, the FOX region 16 in column C2 is formed between the two rows of cells which have separate source regions S and separate adjacent drain regions D.
[0077] For the operation modes, source-side injection programming is employed. FN (Fowler Nordheim) tunneling erase used and reading is also done. The operation conditions of the memory cell are listed in Table I below.
| TABLE I | ||||
|---|---|---|---|---|
| V | V | V | V | |
[0078] While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow.
Claims
Having thus described the invention, what is claimed as new and desirable to be secured by Letters Patent is as follows:
1. A vertical transistor FET memory device comprising:
an array of FET cells formed in rows and columns, with the rows being orthogonally arranged with respect to the columns, with a plurality of cells in a single row having a common source region, and with the cells in a column having separate source regions,
a set of trenches each having a trench sidewalls and a trench bottom in a semiconductor substrate,
threshold implant regions formed within said trench sidewalls,
doped drain regions near the surface of said substrate and doped source regions in the base of said device below said trenches with oppositely doped channel regions therebetween,
a tunnel oxide layer over said substrate including said trenches,
a blanket thick floating gate layer of doped polysilicon over said tunnel oxide layer filling said trenches to below the top of said trenches,
an interelectrode dielectric layer over said floating gate layer, and
a control gate layer of doped polysilicon over said interelectrode dielectric layer.
2. A device in accordance with claim 1 including a source connect implant formed in the bottoms of said trenches.
3. A device in accordance with claim 1 wherein an array of FET cells is formed in rows and columns, with the rows being orthogonally arranged with respect to the columns with the cells in a single row having a common source region and the cells in a column having separate source regions.
4. A device in accordance with claim 1 wherein:
prior to forming said threshold implant regions formed within said trench sidewalls, a source connect implant is formed in the bottoms of said trenches, and
an array of FET cells is formed in rows and columns, with the rows being orthogonally arranged with respect to the columns with the cells in a single row having a common source region and the cells in a column having separate source regions.
5. A device in accordance with claim 1 with FOX regions formed between said rows.
6. A device in accordance with claim 1 wherein:
FOX regions are formed between said rows, and
a source connect implant has been formed in the bottoms of said trenches.
7. A device in accordance with claim 1 wherein:
FOX regions are formed between said rows,
an array of FET cells is formed in rows and columns, with the rows being orthogonally arranged with respect to the columns with the cells in a single row having a common source region and the cells in a column having separate source regions.
8. A device in accordance with claim 1 wherein:
FOX regions are formed between said rows,
a source connect implant is formed in the bottoms of said trenches, and
an array of FET cells is formed in rows and columns, with the rows being orthogonally arranged with respect to the columns with the cells in a single row having a common source region and the cells in a columns column having separate source regions.
9. A vertical transistor memory device with rows and columns of FET memory cells formed in and on a semiconductor substrate which has a surface, said device comprising:
FOX regions formed between said rows in the surface of said substrate,
a set of trenches with sidewalls and a bottom in said semiconductor substrate with threshold implant regions formed within said sidewalls,
doped drain regions near the surface of said substrate and doped source regions in the base of said device below said trenches with oppositely doped channel regions therebetween,
a tunnel oxide layer over said substrate including said trenches,
a blanket thick floating gate layer of doped polysilicon over said tunnel oxide layer filling said trenches and extending above said trenches,
said floating gate layer formed below the top of said trenches,
an interelectrode dielectric layer composed of ONO over said floating gate layer and over said tunnel oxide layer,
a blanket thick control gate layer of doped polysilicon over said interelectrode dielectric layer,
said control gate layer patterned into control gate electrodes, and
spacers adjacent to the sidewalls of said control gate electrode.
10. A device in accordance with claim 9 wherein prior to forming said threshold implant regions formed within said trench sidewalls, a source connect implant was formed in the bottoms of said trenches.
11. A device in accordance with claim 9 wherein an array of FET cells is formed in rows and columns, with the rows being orthogonally arranged with respect to the columns with the cells in a single row having a common source region and the cells in a column having separate source regions.
12. A device in accordance with claim 9 wherein:
a source connect implant is formed in the bottoms of said trenches, and
an array of FET cells is formed in rows and columns, with the rows being orthogonally arranged with respect to the columns with the cells in a single row having a common source region and the cells in a column having separate source regions.
13. A device in accordance with claim 9 wherein said FOX regions which are formed between said rows separate drain regions of adjacent cells in a column, with common drain regions for adjacent cells in a row.
14. A device in accordance with claim 9 wherein a source connect implant is formed in the bottoms of said trenches.
15. A device in accordance with claim 9 wherein an array of FET cells is formed in rows and columns, with the rows being orthogonally arranged with respect to the columns with the cells in a single row having a common source region and the cells in a column having separate source regions.
16. A device in accordance with claim 9 wherein:
a source connect implant is formed in the bottoms of said trenches, and
an array of FET cells is formed in rows and columns, with the rows being orthogonally arranged with respect to the columns with the cells in a single row having a common source region and the cells in a column having separate source regions.
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