Method of forming smooth morphologies in InP-based semiconductors

[0002] This application claims priority to Provisional Patent Application Ser. No. 60/156,667, filed on Sep. 29, 1999.

[0003] The present invention is directed to an improved method of forming smooth morphologies in InP-based semiconductors.

[0004] In the fabrication of nano-scale semiconductor structures, etching is critical. For nano-scale opto-electric and optical devices, surface morphology (i.e., smoothness or lack thereof) determines, at least in part, the performance characteristics of the device; smoother surfaces minimizing optical scattering losses and improving the optical performance of the device. High selectivity (i.e., the difference in etch rate between the substrate and the masking material (how deep a semiconductor may be etched without also etching away the mask)), minimal undercut (i.e., anisotropic etching), and high throughput may all be achieved with high-density-plasma etching, a technique in which an electric field causes energetic ions to strike the surface of a semiconductor substrate at an angle perpendicular to the substrate surface

[0005] Unfortunately, etching processes that produce desired characteristics (i.e., surface smoothness, verticality, etc.) for certain types of semiconductors do not necessarily produce desired characteristics for all or different semiconductors. Thus, well known and relatively mature etching processes used to etch silicon (Si) or gallium arsenide (GaAs), for example, do not yield the same results when used to etch indium phosphide (InP). This is because different semiconductors necessitate different etching chemistries to react with the substrate atoms and are thus subject to different processing issues. For example, difficulties arise in obtaining smooth-etched surfaces in InP-based semiconductors using chlorine-based chemistry etching due to the differing volatilities in the InCl_xand the PCl_xand their corresponding different removal rates during etching. Consequently, an etched surface may be either In-rich or P-rich and thus exhibit rough surface morphology. One solution has been to use methane/hydrogen chemistries, which have been shown to produce relatively smooth InP surfaces, but at very slow etch rates, e.g., approximately 100 nm/minute. Also, CH₄/H₂processes lead to the deposition of polymers that can adversely alter the chamber conditions and thus affect process reproducibility.

[0006] The inductively coupled plasma reactive ion etching (ICP RIE) process is a relatively new dry etching technique developed during the 1990s. The principle advantage of ICP RIE, when compared with other RIE techniques, is the ability to independently control ion energy and flux density. That control, together with proper etch chemistry, can yield improved dry etching processes for InP-based semiconductors.

[0007] There thus exists a need in the art for a semiconductor etching process that overcomes the above-described shortcomings of the prior art.

[0008] The present invention is directed to a semiconductor dry etching process that provides deep, smooth, and vertical etching of InP-based materials with ICP RIE using a chlorinated plasma with the addition of hydrogen gas. To produce relatively high anisotropy with exceptionally smooth surfaces, the amount of hydrogen gas added preferably exceeds the volumetric measure of chlorinated gas in standard cubic centimeter per minute (sccm); at a ratio of greater than 1:1.

[0009] In an embodiment of the present invention, hydrogen is added to a chlorinated (i.e., Cl₂-based, BCL₃-based, SiCL₄-based, etc.) ICP RIE process. The added hydrogen reacts with phosphorous to form PH₃products. To produce smooth etched surfaces in InP-based semiconductors, the amount of hydrogen gas added must exceed the volumetric measure of chlorinated gas in sccm. Preferably, the flow rate ratio of hydrogen gas to chlorinated gas is greater than 1:1, and most preferably, the ratio is approximately 5:3 when pure-Cl₂gas is used.

[0010] The inventive process provides an improved dry etching process (e.g., ICP RIE) for InP-based semiconductor materials that yields significantly improved surface smoothness (i.e., morphology), trench depths as deep as 6 μm, and manufacturing etch rates of up to 1 μm per minute.

[0011] In a preferred embodiment, the present invention is directed to a process for etching InP-based semiconductor materials using the ICP RIE technique. The ICP RIE system has a first RF generator connected to an inductive coil capable of transforming power into a gaseous medium to generate an ionized discharge (i.e. plasma). A second RF generator is used to create an electric field across the plasma and is connected to a platen that supports an InP semiconductor sample inside the chamber of the ICP RIE system and within which the process is carried-out. The inventive process comprises heating the platen to a temperature of between approximately 130° and 400° C. Reactive source gases are introduced into the chamber having a chlorine part and a hydrogen part at a higher volumetric measure (i.e., flow rate) than the chlorine part, preferably at a flow rate ratio of greater than 1:1. The pressure within the chamber is set to less than approximately 5 mT. The power of the first RF generator is set to between approximately 200 and 700 W (3000 W full scale) to provide a relatively low flux of incident ions so that a high selectivity over the etch mask (typically oxide or nitride) can be achieved. The power of the second RF generator is set to between approximately 80 and 200 W to control the DC bias (>250 V) through which the incident ions of the plasma gas are accelerated. The plasma ions are accelerated normal to the plane of the InP semiconductor surface and the substrate is etched at a rate of between approximately 0.38 and 1 μm per minute.

[0012] The invention accordingly comprises the features of construction, combination of elements, and arrangement of parts which will be exemplified in the disclosure herein, and the scope of the invention will be indicated in the claims.

[0013] In the drawing figures, which are not to scale, and which are merely illustrative, and wherein like reference characters denote similar elements throughout the several views:

[0014] FIG. 1 is a schematic diagram of the etching chamber and various other components of an ICP RIE system;

[0015] FIG. 2 is a graph depicting a surface response analysis (SRA) of an etched InP surface morphology as a function of chlorine and hydrogen gas flow rates;

[0016] FIG. 3 is a table of parameters for the ICP RIE system when etching InP-based semiconductors using the process of the present invention;

[0017] FIG. 4 is a cross-sectional schematic of an InP-based semiconductor wafer having a waveguide formed thereon; and

[0018] FIG. 5 is a Scanning Electron Microscope (SEM) image of an InP/InGaAsP waveguide etched to a depth of approximately 2.6 μm using ICP RIE with a Cl₂/H₂/N₂/Ar plasma.

[0019] The present invention is directed to a semiconductor dry etching process that provides deep, smooth, and vertical etching of InP-based materials with ICP RIE using a chlorinated plasma with the addition of hydrogen gas. Chlorine-ions may be generated from a number of gas sources, i.e. Cl₂gas, BCl₃gas, SiCl₄gas, etc. To produce high anisotropy with exceptionally smooth surfaces, the amount of hydrogen gas added preferably exceeds the volumetric measure of chlorinated gas in standard cubic centimeter per minute (sccm); at a ratio of greater than 1:1.

[0020] Applicants have discovered an etching process for InP-based materials where the addition of hydrogen gas in an amount greater (in sccm, for example) than the amount of chlorinated gas can be applied to yield high anisotropy with exceptionally smooth, vertical surfaces (i.e., sidewalls), at etch depths up to 6 μm and at etch rates up to 1 μm per minute. Thus, InP-based optical devices may be made with high throughput using the present invention, and will exhibit improved optical properties due to the exceptionally smooth vertical surfaces.

[0021] The present invention may be carried out using an Inductively Coupled Plasma Reactive Ion Etching (ICP RIE) system, a part of which is generally designated by reference numeral 100 in FIG. 1. The ICP RIE system 100 may include parts and components in addition to those depicted in FIG. 1 (e.g., loadlock, robotics, etc.), as will be obvious to persons skilled in the art. For purposes of the present invention, the chamber 110 of the ICP RIE system 100 is the part of the system 100 within which the present invention is carried-out.

[0022] Precise amounts of each process gas (measured in standard cubic centimeters per minute (sccm)) are delivered into the chamber from a number of mass flow controllers (MFCs), designated generally as 80, through a gas source feed tube 120. Process gases may include chlorinated gas (i.e. Cl₂, BCL₃, SiCl₄, etc.) and hydrogen gas, and may also include inert gases such as argon and/or nitrogen. These gases may be introduced into the process chamber 110 in various percentages (in sccm, for example), as discussed in more detail below.

[0023] Within the chamber 110 a 2 MHz RF generator or power supply 40 is used to generate a plasma discharge 60 by applying RF power into an inductive coil 42. The power supply 40 and coil 42 configuration couples RF power into the gaseous medium (i.e., the mixture of process gases) within the chamber 110 causing ionizations and the resultant plasma density of the gaseous medium is determined by the amount of RF power supplied by the power supply 40.

[0024] The RF power supply 40 and inductive coil 42, which proximately surrounds the gaseous medium within the chamber 110, couple RF power into the gaseous medium to generate a plasma 60 (i.e. ionized gas). The power supply 40 may be used to control the plasma density and thus the ion flux (i.e., number of incident ions per unit area) during the etch process. When a dielectric etch mask is used (i.e. SiO₂or SiN_x), deep etching of InP-based semiconductors requires a relatively low flux of incident ions to minimize the degradation of the etch mask (i.e. increase selectivity). Preferably, when a dielectric etch mask is used the output power of the first RF power supply 40 is set to between approximately 200 and 700 watts, with a full-scale power of approximately 3000 watts. A 13.56 MHz RF generator or source 44 is connected to a platen 30 that serves as a cathode for the system 100 while the chamber walls 112 serve as an anode for the system 100. The platen (i.e., powered cathode) 30 creates an electric field which accelerates the positive-charged plasma ions towards the platen 30. Consequently, an InP-based substrate (i.e.,. sample or wafer) 10 placed on the platen 30 is bombarded with ions. The RF generator 44 controls the bias through which the ions are accelerated (i.e. ion energies). The output power of that RF generator 44 is set to between approximately 80 and 200 watts (full-scale power of approximately 500 watts) so as to achieve ion energies in the range of approximately 250 and 515 eV.

[0025] As is generally known, the wafer 10 may be fabricated using various semiconductor deposition techniques and methods, and may comprise various layers of semiconductor material. In accordance with the present invention, the wafer 10 is comprised of InP-based semiconductors (e.g., InP, InGaAs, InGaAsP). A dielectric material such as SiO₂or SiN_xis grown atop of the wafer 10 top surface and patterned using standard semiconductor lithographic techniques. The patterned dielectric material then serves as a mask for etching into the semiconductor material. The wafer 10 is clamped to the platen 30 and the platen 30 is be heated by a thermocouple 70, to a temperature of between 130° and 400° C. Heating the platen 30 will cause the temperature of the wafer 10 to also increase.

[0026] The pressure within the chamber 110 is preferably set to less than 5 mT, using pressure controls provided as part of the ICP RIE system 100.

[0027] The procedure for positioning a sample 10 and carrying out the method (process) of the present will now be described in detail and with continued reference to FIG. 1. As is generally known, ICP RIE systems 100 typically include a control panel (not shown) which enables setting and control of the various parameters within the chamber 110 such as, for example, chamber pressure, platen temperature, RF generator power, gas mixture for the plasma gas, and other parameters. Thus, while the following description may not include every step necessary to etch an InP wafer 10 in an ICP RIE system 100, it does include the steps essential to the present invention.

[0028] The platen 30 temperature is set by setting the thermocouple 70 control to a desired temperature. In accordance with the present invention, that temperature is between approximately 130° and 400° C. Outside of the chamber 110 (and, indeed, outside of the system 100), the InP-based sample 10 is mounted to a semi-insulating 3-inch diameter Si wafer (R>5000 Ω/cm⁻¹) (not shown) with Thermalcote II brand thermal paste (not shown). The sample 10 is then gently blown with N₂gas. The semi-insulating wafer and sample wafer 10 are placed in a loadlock (not shown) and moved into the chamber 110 by robotics or other automated means provided as part of the system 100. When bulk-processing 2″-diameter (or larger) InP-based wafers, the wafer need not be mounted to a semi-insulating Si carrier wafer but can be directly transferred into the system chamber and clamped to the platen.

[0029] Process parameters may then be input to the system 100 via an input device such as a keypad or other data entry device (not shown). Exemplary parameters are provided in FIG. 3 and discussed in more detail below.

[0030] The present invention was verified by a series of experiments in which the H₂/Cl₂gas flow ratio, and other parameters, were varied. With reference to FIG. 3, example 1 was conducted by setting the power of the first RF generator 40 to 500 W, and the power of the second generator 44 to 150 W. The power supply settings provided a DC bias for the plasma gas 60 of approximately 283 V. The temperature of the platen 30 was set to approximately 250° C., and the pressure within the chamber 110 set to 2.2 mT. The ratio of hydrogen to chlorine was 24:14 (12:7) (in sccm), and argon was added to the plasma gas 60 at a rate of 10 sccm. Those parameters yielded an etch rate of 0.769 μm per minute and selectively over the silicon dioxide mask of 6.

[0031] Example 2 was conducted by setting the power of the first RF generator 40 to 275 W, and the power of the second generator 44 to 105 W. These settings provided a DC bias for the plasma gas 60 of approximately 297 V. The temperature of the platen 30 was set to approximately 300° C., and the pressure within the chamber 110 set to 2.4 mT. The ratio of hydrogen to chlorine was 24:14 (12:7) (in sccm), and argon was added to the plasma gas 60 at a rate of 10 sccm. Those parameters yielded an etch rate of 0.388 μm per minute and selectively over the silicon dioxide mask of 10.

[0032] Example 3 was conducted by setting the power of the first RF generator 40 to 200 W, and the power of the second generator 44 to 100 W. These settings provided a DC bias for the plasma gas 60 of approximately 291 V. The temperature of the platen 30 was set to approximately 275° C., and the pressure within the chamber 110 set to 1.6 mT. The ratio of hydrogen to chlorine was 10:9 (in sccm), and argon was added to the plasma gas 60 at a rate of 10 sccm. Those parameters yielded an etch rate of 0.617 μm per minute and selectively over the silicon dioxide mask of 15.

[0033] Example 4 was conducted by setting the power of the first RF generator 40 to 200 W, and the power of the second generator 44 to 100 W. These settings provided a DC bias for the plasma gas 60 of approximately 300 V. The temperature of the platen 30 was set to approximately 250° C., and the pressure within the chamber 110 set to 2 mT. The ratio of hydrogen to chlorine was 15:12 (5:4) (in sccm), and argon was added to the plasma gas 60 at a rate of 10 sccm. Those parameters yielded an etch rate of 0.650 μm per minute and selectively over the silicon dioxide mask of 15.

[0034] An etched InP-based wafer 10 is depicted in FIG. 4. That wafer 10 includes an InP substrate 130, and a plurality of waveguides 140 etched in accordance with the present invention or using other known semiconductor etching processes or techniques. A mask 20 defines the etch pattern, as is generally known in the art. It is desirable to etch the wafer 10 so that the sidewalls 142 of the waveguide 140 are as smooth as possible. It is also desirable to eliminate the formation of sporadic cones 150 on the substrate floor 132, which also adversely affect the optical characteristics of the wafer 10 and any optical device made therefrom.

[0035] The improved surface morphology (i.e., smoothness) is apparent from the surface response analysis depicted in FIG. 2 that indicates the surface smoothness possible with the present invention. In that figure, etched surfaces are rated between 0 and 5, with extremely smooth surfaces being rated 5. Surfaces that are very smooth but occasionally exhibit sporadic cone formations 150 (see, e.g., FIG. 4) on the substrate floor 132 are rated 4, while smooth surfaces that consistently show sporadic cone formations 150 on the substrate floor 132 are rated 3. Surfaces rated 1 and 2 may have dense cone formations, and 0 rated surfaces have very rough morphologies. Thus, by providing a volumetric flow of hydrogen gas greater than the volumetric flow of chlorinated gas, 4 or 5 rated surfaces may be achieved. In addition, with proper selection and control of the other etching parameters (e.g., RF generator voltage, temperature, pressure), increased etch rates and deeper etch depths may be obtained without sacrifice to the superior surface morphology provided by the present invention.

[0036] The improved surface morphology provided by the present invention is further apparent from the SEM image of FIG. 5. That figure shows an InP/InGaAsP waveguide 140 etched to a depth of approximately 2.6 μm using a Cl₂/H₂/N₂/Ar plasma. The root-mean-square (RMS) roughness of the sidewalls 142 and floor 132 is less than approximately 5 nm.

[0037] Thus, while there have been shown and described and pointed out fundamental novel features of the invention as applied to preferred embodiments thereof, it will be understood that various omissions and substitutions and changes in the form and details of the disclosed invention may be made by those skilled in the art without departing from the spirit of the invention. It is the intention, therefore, to be limited only as indicated by the scope of the claims appended hereto.

[0038] It will thus be seen that the objects set forth above, among those made apparent from the preceding description, are efficiently attained and, since certain changes may be made in the above construction without departing from the spirit and scope of the invention, it is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

[0039] It is also to be understood that the following claims are intended to cover all of the generic and specific features of the invention herein described and all statements of the scope of the invention which, as a matter of language, might be said to fall therebetween.