Method of fabricating shallow trench isolation

[0002] 1. Field of the Invention

[0003] The invention relates to integrated circuit fabrication technology and, in particular, to a method of fabricating STI (shallow trench isolation) that can prevent corner erosion of the STI, thus improving the performance of a semiconductor device.

[0004] 2. Description of the Related Art

[0005] Formed by filling insulating materials, such as silicon oxide (SiO₂), into the trench in the semiconductor substrate using HDPCVD (high-density plasma-chemical vapor deposition), the STI (shallow trench isolation) has gradually taken the place of conventional LOCOS (Local-Oxidation of Silicon).

[0006] Since HDPCVD has the advantage of good gap-filling capability, insulating materials filling the trench can be planarized. However, due to the effect of plasma during the trench-filling process, accompanying processes such as bombardment etching, sputtering, and deposition may damage the exposed semiconductor substrate. To solve this problem, a shallow trench isolation manufacturing method has been proposed. For instance, U.S. Pat. No. 6,146,974 for “Method of fabricating shallow trench isolation (STI)” discloses a method of fabricating STI, in which a first HDPCVD is performed to form a conformal oxide layer on the liner oxide layer without applying bias to the substrate. Then, a second HDPCVD is performed on the conformal oxide layer to form an oxide layer that fills the trench and covers the conformal oxide layer. After the second HDPCVD step, CMP (chemical mechanical polishing) is performed to planarize the oxide layer.

[0007] However, to remove silicon oxide formed by natural oxidation from the hard mask, before peeling the hard mask including silicon nitride, HF etchant performs deglazing. Section views FIG. 1 to FIG. 3 are referenced hereinbelow to explain the fabrication process of the shallow trench isolation in the related art.

[0008] As shown in FIG. 1, a hard mask HM constituting a liner silicon nitride layer 14 and a liner silicon oxide layer 12 is used to etch a semiconductor substrate 10 to form a trench 16. 18 is a thermal oxide film formed by thermal oxidation, 20 is a liner nitride film, and 22 is the silicon oxide layer formed by HDPCVD (no bias application) with the flow ratio of O₂to SiH₄being about 2˜4:1. 24 is the trench-filling silicon oxide layer formed by HDPCVD (with bias application) with the flow ratio of O₂to SiH₄being about 2˜4:1. The upper surface of the silicon oxide layer 22 is lower than the trench-filling silicon oxide layer 24. This is because during deglazing, the etching rate of the silicon oxide layer 22 (for example, about 690 angstroms per minute) is higher than that of the trench-filling silicon oxide layer 24 (for example, about 300 angstroms per minute). A recess 25 is formed between the liner nitride film 20 and the trench-filling silicon oxide layer 24, and is stopped at the corner of the liner nitride film 20.

[0009] As shown in FIG. 2, etchants such as phosphoric acid are used to remove the liner silicon nitride layer 14 from the hard mask HM. The liner nitride film 20 is etched to form a small channel 26, and leaves a portion 20a.

[0010] As shown in FIG. 3, etchants such as HF acid are used to remove the liner silicon oxide layer 12 of the hard mask HM. At this time, enchants etch the thermal oxide film 18 via the small channel 26. Thus, a recess 28 is formed at the corner of the shallow trench isolation, and the oxide denoted by reference number 18ais left. This affects the performance of the MOS transistors subsequently formed.

[0011] In view of the above, an objective of the invention is to provide a method of fabricating a shallow trench isolation, which can avoid the formation of recesses at the corner of the shallow trench, thus enhancing the performance of the subsequently formed MOS.

[0012] To achieve this objective, the method of fabricating a shallow trench isolation according to the invention includes the following steps.

[0013] A semiconductor substrate is provided, a liner silicon oxide layer is formed thereon, and a liner silicon nitride layer is formed on the liner silicon oxide layer. Then, the liner silicon nitride layer and the liner silicon oxide layer are used as a hard mask to etch a semiconductor substrate to form a shallow trench.

[0014] Then, after a thermal oxide film is formed on the inner wall of the shallow trench, a silicon rich oxide layer covering the surface of the thermal oxide film is formed by HDPCVD (high density plasma-chemical vapor deposition) with no bias application. The thickness of the silicon rich oxide may be about 50˜150 angstrom. SiH₄and O₂may be used as reaction gases, and the ratio of the flow rate of O₂to SiH₄may be about 1:1 to 1:2.

[0015] A silicon oxide layer filling the shallow trench is then formed by HDPCVD with bias application. SiH₄and O₂may be used as reaction gases, and the ratio of the flow rate of O₂and SiH₄may be about 1:1 to 1:2.

[0016] The layers above the hard mask are then removed for planarization by CMP with the liner silicon nitride layer as a stop layer. Then, deglazing is performed to remove a portion of the silicon oxide layer, a portion of the silicon rich oxide, and a portion of the thermal oxide film.

[0017] After removing the liner silicon nitride layer to expose the liner silicon oxide layer, the liner silicon oxide layer, a portion of the silicon rich oxide, a portion of the thermal oxide layer, and a portion of the silicon oxide layer are removed to expose the semiconductor substrate. Then, a sacrifice oxide film is formed on the surface of the semiconductor substrate to avoid the corner erosion of the shallow trench isolation. The sacrifice oxide film may be formed by thermal oxidation, and may have a thickness about 50˜100 angstrom. A portion of the sacrifice oxide film is then removed using HF as the etchant, and a portion of the silicon rich oxide is reserved to avoid the corner erosion of the shallow trench isolation.

[0018] FIGS. 1 to 3 are sectional views showing the fabrication process of the shallow trench isolation in the prior art

[0019] FIGS. 4 to 10 are sectional views showing the fabrication process of the shallow trench isolation according to the embodiments of the invention.

[0020] The fabrication process of the shallow trench isolation according to an embodiment of the invention will be described with reference to sectional views shown in FIG. 4 to FIG. 10.

[0021] Refer to FIG. 4. An anisotropic etching is performed to form a shallow trench 106 in a semiconductor substrate 100 using the hard mask HM including a liner silicon oxide layer 102 and a liner silicon nitride layer 104 as a shield. Then, a thermal oxide film 103 having a thickness of about 100˜200 angstroms is formed on the surface of the shallow trench 106 by thermal oxidation. A no-bias-applied HDPCVD process with a flow ratio of O₂to SiH₄of about 1:1 to 1:2 is then performed to form a silicon rich oxide 105 on the surface of the thermal oxide film 103. The thickness of the silicon rich oxide 105 is about 50˜150 angstrom, and the etching rate thereof is about 100˜200 angstroms per minute. Then, HDPCVD continues with bias application with a flow ratio of O₂to SiH₄of about 1:2 to form a trench-filling silicon oxide layer 110 on the surface of the silicon rich oxide 105. The etching rate of the silicon oxide layer 110 in a 5% HF etchant is about 450˜500 angstroms per minute.

[0022] As shown in FIG. 5, by a CMP process using the liner silicon nitride 104 as a stop layer, the layers above the hard mask HM are then removed except for the silicon oxide layer 110a, the silicon rich oxide 105a, and the thermal oxide film 103a.

[0023] Refer to FIG. 6. Deglazing removing portions of the silicon oxide layer 110a, the silicon rich oxide 105a, and the thermal oxide film 103ais then performed to form a silicon oxide layer 110b, a silicon rich oxide 105b, and a thermal oxide film 103b.Since the ratio of the etching rates of the silicon oxide layer 110aand the silicon rich oxide 105ais about 1.5˜3:1, the top surface of the silicon rich oxide 105bis higher than that of the silicon oxide layer 110b,as the structure shown in FIG. 6.

[0024] As shown in FIG. 7, the liner silicon nitride layer 104 of the hard mask HM is then removed to expose the liner silicon oxide layer 102.

[0025] As shown in FIG. 8, the liner silicon oxide layer 102 is then removed. Portions of the silicon rich oxide 105b,the thermal oxide film 103b, and the silicon oxide layer 110bare also removed to form a silicon rich oxide 105c,a thermal oxide film 103c,and the silicon oxide layer 110c.The semiconductor substrate 100 is thus exposed.

[0026] As shown in FIG. 9, a thermal oxidation process is then performed to form a sacrifice oxide film having a thickness about 50˜150 angstroms on the surface of the semiconductor substrate 100.

[0027] As shown in FIG. 10, part of the sacrifice oxide film 130 is then removed to complete the fabrication process of the shallow trench isolation.

[0028] One characteristic of the invention is that by adjusting the reaction gases, the silicon rich oxide is formed by HDPCVD with no bias application. The trench-filling silicon oxide layer is then formed by HDPCVD continuously with bias application.

[0029] The fabrication process according to the invention can avoid the formation of the recess at the corner of the shallow trench isolation, thus improving the performance of the subsequently formed MOS.

[0030] While the invention has been described with reference to a preferred embodiment, this description is not intended to be construed in a limiting sense. Various modifications of the embodiment will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications.