Single-ended to differential and differential to single-ended conversion using a common mode shunt

[0002] The present application is based on U.S. Provisional Patent Application entitled “Singe-Ended to Differential and Differential to Single-Ended Conversion Using A Common Mode Shunt”, Ser. No. 60/250,598, filed Nov. 30, 2000, which is hereby incorporated by reference in its entirety. The present application is related to U.S. patent application entitled “Quadrature Oscillator With Phase Error Correction”, Ser. No. 09/747,163, filed Dec. 21, 2000, which is hereby incorporated by reference in its entirety.

[0003] The present invention relates to electronic signal conversion, and more specifically, to the conversion of single-ended signals to differential signals and differential signals to single-ended signals using a common mode shunt.

[0004] The advantages of differential circuits are well known especially when incorporated into RF integrated circuits. Often the input and/or output signal needs to be single-ended. The use of differential circuits in this case requires the use of some single-ended to differential conversion. The differential transistor pair is a circuit often used to convert single-ended inputs to differential signals. This circuit does not work well if the current source biasing the differential pair does not have a high impedance at high frequencies. A balanced/unbalanced (BALUN) impedance matching network is a type of high frequency transformer that can be used for differential/single-ended conversions. The BALUN, however, is moderately expensive and bulky. Various transmission line combiners are also known.

[0005] A single-ended to differential converter in accordance with an embodiment of the present invention includes a common mode shunt having a common mode junction and a load element. The common mode shunt includes first and second reactive elements each having first ends coupled together at the common mode junction. The second end of the first reactive element receives a single-ended input signal referenced to a reference signal. The second ends of both of the first and second reactive elements develop first and second polarities, respectively, of a differential output signal. The common mode shunt further includes a third reactive element having a first end coupled to the common mode junction and a second end referenced to the reference signal. The load element has a first end coupled to the second end of the second reactive element and a second end referenced to the reference signal.

[0006] The reference signal may be ground or any other suitable common signal serving as a voltage reference for the single-ended input signal. In one embodiment, for example, the load element and the third reactive elements are both coupled to ground. An input source provides the single-ended input signal to the second end of the first reactive element. In one embodiment, the input source includes a series-coupled input impedance element. The load element and the series-coupled input impedance element may be resistors having approximately the same resistance. The first and second reactive elements of the common mode shunt may have approximately the same impedance. In a particular embodiment, the first and second reactive elements are inductors and the third reactive element is a capacitor. In this embodiment, the inductors may each have approximately the same inductance. In the same or alternative embodiment, the first and second reactive elements have an impedance of approximately Z, and the third reactive element has an impedance of approximately −0.5Z. This is easily achieved using inductive and capacitive elements.

[0007] A differential to single-ended converter in accordance with an embodiment of the present invention also includes a common mode shunt and a load element. In fact, the configuration may be substantially identical, except that the second ends of the first and second reactive elements receive first and second polarities, respectively, of a differential input signal and the second end of the second reactive element develops a single-ended output signal.

[0008] Again, the reference signal may be ground. The first and second reactive elements of the common mode shunt may have approximately the same impedance. The first and second reactive elements may be inductors and the third reactive element may be a capacitor. The inductors may each have approximately the same inductance. The differential input signal may be current-based polarity signals, and may be developed by a differential pair of transistors. A fourth reactive element having an impedance of approximately −2Z may be coupled between the second ends of the first and second reactive elements, where the first and second reactive elements each have an impedance of approximately Z.

[0009] A better understanding of the present invention(s) can be obtained when the following detailed description of embodiment(s) of the invention(s) is considered in conjunction with the following drawings, in which:

[0010] FIG. 1 is a block diagram of an exemplary common mode shunt implemented according to an embodiment of the present invention.

[0011] FIG. 2 is a block diagram of a single-ended to differential converter network using the common mode shunt of FIG. 1 coupled to a load element.

[0012] FIG. 3 is a block diagram of an exemplary differential to single-ended power combiner implemented according an embodiment of the present invention using the common mode shunt of FIG. 1.

[0013] FIG. 4 is a schematic diagram of an oscillator circuit employing a single-ended to differential converter according to an embodiment of the present invention configured as a common mode shunt using inductive and capacitive reactive components.

[0014] FIG. 1 is a block diagram of an exemplary common mode shunt 100 implemented according to an embodiment of the present invention. The common mode shunt 100 includes three reactive elements 101, 102 and 103 with impedances Z₁, Z₂and Z₂, respectively. The impedances of elements 102 and 103 are approximately the same. The reactive elements 101-103 may each be single reactive elements or combinations of reactive elements. Examples of reactive elements include capacitors, inductors and variations or derivatives thereof, such as transformers or the like. The element 101 has one end coupled to a ground reference signal and its other end coupled to a voltage terminal V_A(having voltage V_A). It is noted that “ground” serves a common reference signal where it is understood that any reference signal other than ground may be used. The other two elements 102, 103 each have one end connected to the V_Aterminal. The element 102 has its other end coupled to a voltage terminal V₁(having voltage V₁) and the element 103 has its other end coupled to a voltage terminal V₂(having voltage V₂). A current I₁is defined flowing from the V₁terminal to the V_Aterminal through the element 102 and a current I₂is defined flowing from the V₂terminal to the V_Aterminal through the element 103. The currents I₁and I₂both flow through the element 101. The relationships between the voltages and currents are further defined in the following equations 1, 2 and 3:

[0015] V_A=(I₁+I₂)Z₁  (EQ 1)

[0016] V₁=I₁Z₂+V_A=I₁Z₂+(I₁+I₂)Z₁  (EQ 2)

[0017] V₂=I₂Z₂+V_A=I₂Z₂+(I₁+I₂)Z₁  (EQ 3)

[0018] Equations 2 and 3, when added together, define a common mode voltage V_CMthat is twice the common mode (i.e. average voltage) of the voltages V₁and V₂as illustrated by the following equation 4:

[0019] V₁+V₂=I₁Z₂+I₂Z₂+2(I₁+I₂)Z₁=(I₁+I₂)(Z₂+2Z₁)=2V_CM→V_CM≡(V₁+V₂)/2  (EQ 4)

[0020] where the forward slash “/” denotes division. The common mode voltage V_CMis zero even if the sum of the currents I₁and I₂is not zero as long as the common mode impedance is zero as illustrated by following equation 5:

[0021] V₁+V₂=0→Z₂+2Z₁=0  (EQ 5)

[0022] For example, if Z₁is an inductor with inductance L₁and Z₂is a capacitor with capacitance C₂, then at some frequency (ω) their common mode impedance would be zero as illustrated by the following equation 6:

[0023] Z₁=jωL₁Z₂=−j/ωC₂jω2L₁−j/ωC₂=0→ω²=1/2L₁C₂  (EQ 6)

[0024] An exemplary embodiment for single-ended to differential conversion at a frequency of 5 gigahertz (GHz) is L₁=approximately 1 nanohenry (nH) and C₂=approximately 0.5 picofarads (pF). The only way that the common mode voltage can be zero is that the two terminal voltages V₁and V₂are differential, i.e. having approximately the same magnitude but opposite sign as illustrated by the following equation 7:

[0025] V₁+V₂=0→V₂=−V₁  (EQ 7)

[0026] At an operating frequency (jω), the common mode shunt 100 establishes a pair of voltages at the V₁and V₂terminals that are equal in magnitude and 180° out of phase, independent of the terminal currents I₁and I₂. If the common mode shunt 100 is connected between the bases of a differential pair, such as a differential pair of bipolar junction transistors (BJTs), then the differential pair can be driven from one side without impressing a common mode voltage on the current source/sink biasing the common emitter/source node. It is desired that the differential pair have a high common mode impedance as seen from the common emitters back to the source at the operating frequency.

[0027] FIG. 2 is a block diagram of a single-ended to differential converter network 200 using the common mode shunt 100 coupled to a load element 104 with impedance Z_L. The converter network 200 is driven at the V₁terminal (with input impedance Z_IN) and the load element 104 is coupled between the V₂terminal and ground. A load current I_Lis defined as flowing from the V₂terminal to ground through load element 104.

[0028] Subtracting equation 3 from equation 2 yields the following equations 8 and 9:

[0029] V₁−V₂=2V₁=I₁Z₂−I₂Z₂=(I₁−I₂)Z₂  (EQ 8)

[0030] I_L=−I₂=V₂/Z_L=−V₁/Z_L  (EQ 9)

[0031] The following equations 10 and 11 illustrate substituting the load current relationship for I₂and solving for I₁to define the input impedance Z_IN:

[0032] 2V₁=(I₁−V₁/Z_L)Z₂→I₁=2V₁/Z₂+V₁/Z_L  (EQ 10)

[0033] Z_IN=V₁/I₁=V₁/(2V₁/Z₂+V₁/Z_L)=Z_L(Z₂/2)/(Z_L+Z₂/2)=Z_L∥(Z₂/2)  (EQ 11)

[0034] In this manner, the input impedance Z_INis the parallel combination of the load impedance Z_Land half of the impedance Z₂of the element 103. In another embodiment, a matching element of −0.5Z₂is connected between the input terminal V₁and the output terminal V₂to achieve a similar effect.

[0035] FIG. 3 is a block diagram of an exemplary differential to single-ended power combiner 300 implemented according to an embodiment of the present invention using the common mode shunt 100. It is often desirable to combine the output currents from a differential circuit and apply the combined output currents to a load. The two currents are ideally equal but 180° out of phase with respect to each other, such as the collector/drain currents from a differential transistor pair. The power combiner 300 includes the common mode shunt 100 coupled to the load element 104 in a similar manner as described for the converter network 200. Furthermore, the power combiner 300 includes a first current source 105 coupled between terminals 106 and V₁with a current I_IN1flowing from the V₁terminal to a terminal 106 and a second current source 107 coupled between terminals 108 and V₂with a current I_IN2flowing from the terminal 108 to the V₂terminal. The current sources 105 and 107 collectively represent the output of a differential pair since each transistor of the differential pair has relatively high output impedance.

[0036] For example, a pair of bipolar junction transistors (BJTs) Q1 and Q2 forming a differential pair 109 are shown coupled to the differential to single-ended power combiner 300. The BJTs Q1 and Q2 have their emitters coupled together and to one end of a current source 110, having its other end coupled to ground. The collectors of the BJTs Q1 and Q2 are coupled to terminals 106 and 108 to illustrate the coupling to the differential to single-ended power combiner 300.

[0037] In this manner, the current sources 105, 107 representing the output of a differential pair are coupled to both sides of the common mode shunt 100, whereas the load element 104 is coupled to only one side, such as the V₂terminal as shown. The following equation 12 illustrates the relationship of currents I₁and I₂with respect to the input currents I_IN1and I_IN2and the load current I_L:

[0038] I₁=−I_IN1I₂=I_IN2−I_L  (EQ 12)

[0039] Substituting equation 12 into equation 8 provides the relationships illustrated in the following equations 13, 14 and 15:

[0040] 2V₁=[−I_IN1−(I_IN2−I_L)]Z₂=Z₂(V₂/Z_L)−(I_IN1+I_IN2)Z₂  (EQ 13)

[0041] (I_IN1+I_IN2)Z₂=Z₂(V₂/Z_L)+2V₂→V₂=[Z_L(Z₂/2)/(Z₂/2+Z_L)](I_IN1+I_IN2)=((Z₂/2)∥Z_L)(I_IN1+I_IN2)  (EQ 14)

[0042] I_L=V₂/Z_L=[(Z₂/2)/(Z₂/2+Z_L)](I_IN1+I_IN2)  (EQ 15)

[0043] Since both terminal voltages V₁and V₂are approximately equal in magnitude and out of phase, when the source currents I_IN1and I_IN2are also equal in magnitude and out of phase, the effective impedance as seen by each source of the differential pair is the same. It is noted that equation 15 shows that both sources contribute equally to the load current I_L. It is also noted that the addition of suitable matching components can scale the ratio of load current I_Lto source current I_IN1, I_IN2. For example, in an alternative embodiment, a matching element 111 of −2Z₂is shown with dashed lines coupled between the two terminals V₁and V₂making the load current I_Lequal to the sum of the two source currents I_IN1and I_IN2.

[0044] Again, it is noted that the common mode shunt 100 employed for the exemplary single-ended to differential converter network 200 or the exemplary differential to single-ended power combiner 300 is configured using reactive components, such as inductive or capacitive components or the like. For example, the elements 102 and 103 may be inductive elements while the element 101 is a capacitive element, or the elements 102 and 103 may be capacitive elements while the element 101 is an inductive element.

[0045] FIG. 4 is a schematic diagram of an oscillator circuit 401 employing a single-ended to differential converter 403 configured as a common mode shunt using inductive and capacitive reactive components. An oscillator 405 asserts a single-ended sinusoidal local oscillator (LO) signal to one end of an input resistor RI, which has its other end coupled to an input/output (I/O) terminal 407 of the converter 403. The oscillator 405 and the input resistor RI form an RF source. The converter 403 includes a first inductor L1 coupled between the I/O terminal 407 and a common mode junction 409, a second inductor L2 coupled between the common mode junction 409 and another output terminal 411, and a capacitor C coupled between the common mode junction 409 and ground. A load resistor RL is coupled to the output terminal 411 and ground. The output terminals 407, 411 develop a differential LO signal with separate polarity signals DLO+ and DLO−, respectively, as shown.

[0046] The I/O terminal 407 of the converter 403 is driven by the RF source, the capacitor C provides a common mode return to ground via the common mode junction 409, and the load resistor RL functions as a reference for the differential signal at RF. In one embodiment, the inductances of the inductors L1 and L2 are approximately the same. The resistors RI and RL may provide a reasonable conjugate match that converts the single-ended LO signal to the differential signals DLO+ and DLO− by shunting a common mode portion of the differential signal through the common mode junction 409, which functions as the RF return back to the RF source. In one embodiment, the resistors RI and RL are impedance matching resistors having the same resistive value.

[0047] It is noted that the inductors L1 and L2 and the capacitor C of the converter 403 may be implemented using separate physical devices, or may be implemented using parasitic elements that may be inherently present on a printed circuit board (PCB) or integrated circuit (IC) or the like. For example, either or both of the inductors L1, L2 may be implemented using parasitic inductance, or the capacitor C may be implemented using parasitic capacitance, if available on an IC package rather than using physical devices. The use of inherent or parasitic elements saves cost and valuable IC space. The configuration of the converter 403 has an inherent advantage in that if DC bias is desired or necessary, it may be applied at the common mode junction 409. It is noted, however, that DC bias is not a requirement of the present invention. An alternative embodiment is contemplated in which the inductors L1, L2 are replaced with capacitors C1, C2, respectively and in which the capacitor C is replaced by an inductor. Again, parasitic values may be used for any or all of the elements if available and if desired. Such configuration potentially saves time and space since only one inductor (inductors usually being larger and more expensive than capacitors) is used. Such configuration, however, has the disadvantage in that if DC bias is desired or necessary, separate DC biases may need to be applied at the terminals 407 and 411.

[0048] Although a system and method according to the present invention has been described in connection with one or more embodiments, it is not intended to be limited to the specific form set forth herein, but on the contrary, it is intended to cover such alternatives, modifications, and equivalents, as can be reasonably included within the spirit and scope of the invention as defined by the appended claims.