Apparatus and method of mirroring a voltage to a different reference voltage point

[0002] This invention relates generally to voltage mirroring circuits, and in particular, to an apparatus and method of mirroring a voltage to one or more different reference voltage points.

[0003] Many integrated circuits incorporate a voltage reference circuit, such as a bandgap circuit, to generate a highly stable reference voltage. The reference voltage is typically used by one or more circuits and/or devices to perform their intended functions. The highly stable reference voltage facilitates these circuits and/or devices to perform their intended function within specification even with temperature, supply voltage, and/or process variations.

[0004] When an integrated circuit needs a plurality of different highly stable reference voltages, a plurality of reference voltage circuits, such as bandgap circuits, can be provided to generate the required reference voltages. However, incorporating a plurality of reference voltage circuits into an integrated circuit would unduly consume integrated circuit space, power, and increase the cost and complexity of the integrated circuit.

[0005] FIG. 1 illustrates a schematic diagram of an exemplary voltage mirroring circuit in accordance with an embodiment of the invention;

[0006] FIG. 2A illustrates a schematic diagram of another exemplary voltage mirroring circuit in accordance with an embodiment of the invention;

[0007] FIG. 2B illustrates a schematic diagram of another exemplary voltage mirroring circuit in accordance with an embodiment of the invention;

[0008] FIG. 3 illustrates a schematic diagram of an exemplary multiple-output voltage mirroring circuit in accordance with an embodiment of the invention;

[0009] FIG. 4 illustrates a schematic diagram of another exemplary multiple-output voltage mirroring circuit in accordance with an embodiment of the invention;

[0010] FIG. 5 illustrates a schematic diagram of an exemplary voltage mirroring circuit with cascoding control in accordance with an embodiment of the invention;

[0011] FIG. 6 illustrates a schematic diagram of an exemplary multiple-output voltage mirroring circuit with cascoding control in accordance with an embodiment of the invention; and

[0012] FIG. 7 illustrates a schematic diagram of another exemplary voltage mirroring circuit in accordance with an embodiment of the invention.

[0013] FIG. 1 illustrates a schematic diagram of an exemplary voltage mirroring circuit 100 in accordance with an embodiment of the invention. The voltage mirroring circuit 100 comprises an operational amplifier 102, an n-channel field effect transistor (FET) N1, a current-setting resistor R, and a load resistor αR. The operational amplifier 102 includes a positive input to receive a reference voltage V_REF, a negative input coupled to the source of the FET N1 and an end of the current-setting resistor R, and an output coupled to the gate of the FET N1. The other end of the current-setting resistor R can be coupled to ground potential. The load resistor αR is coupled between the power supply voltage rail V_DDand the drain of the FET N1.

[0014] In operation, the operational amplifier 102 sets the gate voltage V_GATEof the FET N1 such that the feedback voltage V_FBapplied to the negative input of the operational amplifier 102 is substantially equal to the reference voltage V_REFapplied to the positive input of the operational amplifier 102 (i.e. mirroring the reference voltage V_REFonto the feedback voltage V_FB). Thus, the following relationship substantially holds:

[0015] V_FB=V_REF  Eq. 1

[0016] Since the feedback voltage V_FBis across the current-setting resistor R, the current I through the current-setting resistor R is given substantially by the following relationship:

[0017] I=V_FB/R=V_REF/R  Eq. 2

[0018] The current I also flows through the channel of the FET N1 and through the load resistor αR. Thus, the output voltage V_Oof the voltage mirroring circuit 100, taken off the drain of the FET N1, is given substantially by the following relationship:

[0019] V_O=V_DD−IαR=V_DD−αV_REF  Eq. 3

[0020] As equation 3 illustrates, the voltage mirroring circuit 100 has generated an output voltage V_Othat derives from the reference V_REF. The output voltage V_Ovaries as a function of α, which is the ratio of the resistance of the load resistor αR to the resistance of the current-setting resistor R. The output voltage V_Obeing a function of a resistor ratio makes it less susceptible to process errors.

[0021] With regard to sufficient headroom for the voltage mirroring circuit 100 to output the desired output voltage V_O, the supply voltage V_DDneeds to accommodate the voltage drop αV_REFacross the load resistor αR, the voltage drop V_N1across the FET N1, and the voltage drop V_REFacross the current-sensing resistor R. Thus, the following relationship substantially holds:

[0022] (1+α) V_REF+V_N1<V_DD  Eq. 4

[0023] Within limits, V_REFcan be divided down to use less headroom and parameter α can be rescaled to obtain the same desired output voltage V_Oin accordance with the relationship stated in equation 4.

[0024] FIG. 2A illustrates a schematic diagram of another exemplary voltage mirroring circuit 200 in accordance with an embodiment of the invention. The voltage mirroring circuit 200 is similar to voltage mirroring circuit 100 in that it comprises an operational amplifier 202, an n-channel field effect transistor (FET) N1, a current-setting resistor R, and a load resistor αR. The operational amplifier 202 includes a positive input to receive a reference voltage V_REF, a negative input coupled to the source of the FET N1 and an end of the current-setting resistor R, and an output coupled to the gate of the FET N1. The other end of the current-setting resistor R can be connected to ground potential. The load resistor αR is connected between the power supply voltage rail V_DDand the drain of the FET N1.

[0025] The voltage mirroring circuit 200 differs from the voltage mirroring circuit 100 in that it further comprises a first p-channel FET P1 having a source coupled to the power supply rail V_DDand a drain coupled to an end of the load resistor αR. The voltage mirroring circuit 200 further comprises a second p-channel FET P2 having a source coupled to the power supply rail V_DDand a drain coupled to the gates of the first and second p-channel FETs P1-2. Additionally, the voltage mirroring circuit 200 comprises a second n-channel FET N1 having a drain coupled to the drain of the second p-channel FET P2, a source coupled to an end of a resistor R2, and a gate coupled to the gate of the first n-channel FET N1. The other end of the resistor R2 can be connected to ground potential.

[0026] The voltage mirroring circuit 200 operates similarly as voltage mirroring circuit 100 in that the operational amplifier 202 drives the first n-channel FET N1 to force the feedback voltage V_FBto be substantially the same as the reference voltage V_REF(see equation 1). Accordingly, the current I through the current-setting resistor R is V_REF/R (see equation 2). This current I also flows through the load resistor αR. Therefore, the voltage drop (V_X-V_Y) across the load resistor αR is given substantially by the following equation:

[0027] V_X−V_Y=IαR=(V_REF/R) αR=αV_REF  Eq. 5

[0028] In the case of voltage mirroring circuit 200, the addition of the first p-channel FET P1 between the load resistor αR and the power supply rail V_DDmakes the voltages V_Xand V_Yon either side of the load resistor αR substantially float with respect to the power supply voltage V_DD. To ensure that the voltages V_Xand V_Yfloat with respect to the power supply voltage V_DD, the drain current of the first p-channel FET P1 should be substantially the same as the current I through the load resistor αR.

[0029] Therefore to maintain the drain current of FET P1 substantially the same as current 1, the voltage mirroring circuit 200 includes a current control circuit comprising the second p-channel FET P2, the second n-channel FET N2, and the second resistor R2. The first and second n-channel FETs N1-2 are substantially matched as are the resistances of resistors R and R2. Therefore, the current through the second resistor R2 is substantially the same as the current I through the current-setting resistor R (i.e. by current mirroring). The current through the second resistor R2 also flows through the second p-channel FET P2. The first and second p-channel FETs P1-2 are substantially matched. Since the gates of FETs P1-2 are connected in common, the drain current through the first p-channel FET P1 is substantially the same as the current through the second p-channel FET P2, which in turn, is substantially the same as the current I through the current-setting resistor R. Again, this ensures that the voltages V_Xand V_Ysubstantially float with respect to the power supply voltage V_DD.

[0030] FIG. 2B illustrates a schematic diagram of an exemplary voltage mirroring circuit 200′ in accordance with an embodiment of the invention. The voltage mirroring circuit 200′ is similar to voltage mirroring circuit 200 except that the current control circuit is designed to operate with a current I/N a factor of N lower than the current I through the current setting resistor R. This allows the voltage mirroring circuit 200′ to operate more power efficiently. In this regard, the second n-channel FET N2 is sized to operate with a current density a factor of N below the current density of the first n-channel FET N1. In order the gate-to-source voltage of the n-channel FETs N1-2 to be substantially the same, the resistor R2 is N times greater than the current setting resistor R, (i.e. R*N). Therefore, the current through resistor R2 is approximately I/N, which also flows through the second p-channel FET P2. The second p-channel FET P2 is also sized to operate with a current density a factor of N below the current density of the first p-channel FET P1. Thus, a current of I/N through the second p-channel FET P2 results substantially in a current I through the first p-channel FET P1.

[0031] With regard to sufficient headroom for the voltage mirroring circuits 200 and 200′ to output the desired output voltage V_X−V_Y, a the supply voltage V_DDneeds to accommodate the voltage drop V_P1across the FET P1, the voltage drop αV_REFacross the load resistor αR, the voltage drop V_N1across the FET N1, and the voltage drop V_REFacross the current-sensing resistor R. Thus, the following relationship substantially holds:

[0032] (1α) V_REF+V_N1+V_P1<V_DD  Eq. 6

[0033] Within limits, V_REFcan be divided down to use less headroom and parameter α can be rescaled to obtain the same desired output voltage V_X−V_Yin accordance with the relationship stated in equation 6.

[0034] FIG. 3 illustrates a schematic diagram of an exemplary multiple-output voltage mirroring circuit 300 in accordance with an embodiment of the invention. The multiple-output voltage mirroring circuit 300 generates a plurality of output voltages derived from a common reference voltage V_REF. The voltage mirroring circuit 300 comprises an operational amplifier 302, a plurality of n-channel field effect transistors (FETs) N1-4, a plurality of source-biasing transistors R_M1-4, a current-setting resistor R/4, and a plurality of load resistors αR, βR, χR, and δR. The operational amplifier 302 includes a positive input to receive a reference voltage V_REF, a negative input coupled to an end of the current-setting resistor R/4, and an output coupled to the respective gates of FETs N1-4. The other end of the current-setting resistor R can be connected to ground potential. The source-biasing resistors R_M1-4are coupled between the current-setting resistor R and the respective sources of the FETs N1-4. The load resistors αR and βR are connected between a first power supply voltage rail V_DD1and the respective drains of FETs N1-2, and load resistors χR, and δR are coupled between a second power supply voltage rail V_DD2and the respective drains of FETs N3-4. It shall be noted that the source-biasing resistors R_M1-4are optional. They are used to better ensure that the currents are equal through the respective FETs N1-4. If the matching of FETs N1-4 is sufficient for an application, the source-biasing resistors R_M1-4are not needed.

[0035] In operation, the operational amplifier 302 drives the plurality of FETs N1-4 to force the feedback voltage V_FBto be substantially equal to the reference voltage V_REF(see equation 1). The current I through the current-setting resistor R/4 is substantially given by the following relationship:

[0036] I=4*V_REF/R  Eq. 7

[0037] In this exemplary embodiment, the FETs N1-4 are substantially matched and the source-biasing resistors R_M1-4are substantially matched. Therefore, the drain currents I_1-4of the FETs N1-4 are substantially the same and given substantially by the following relationship:

[0038] I₁=I₂=I₃=I₄=I/4=V_REF/R  Eq. 8

[0039] The drain currents I_1-4of FETs N1-4 flow respectively through load resistors αR, βR, χR, and δR. Therefore, the output voltages V_O1-4of the multiple-output voltage mirroring circuit 300 are given substantially by the following equations:

[0040] V_O1=V_DD1−I₁*αR=V_DD1−V_REF/R*αR=V_DD1−αV_REF  Eq. 9a

[0041] V_O2=V_DD1−I₂*βR=V_DD1−V_REF/R*βR=V_DD1−βV_REF  Eq. 9b

[0042] V_O3=V_DD2−I₃*χR=V_DD2−V_REF/R*χR=V_DD2−χV_REF  Eq. 9c

[0043] V_O4=V_DD2−I₄*δR=V_DD2−V_REF/R*δR=V_DD2−δV_REF  Eq. 9d

[0044] With regard to sufficient headroom for the voltage mirroring circuit 300 to output the desired output voltages V_O1-4, the supply voltages V_DD1-2need to accommodate the respective voltage drops αV_REF, βV_REF, χV_REF, and δV_REFacross the respective load resistors αR, βR, χR, and δR, the voltage drops V_N1-4across the respective FETs N1-4, the voltage drops V_M1-4across the respective source-biasing resistors R_M1-4, and the voltage drop V_REFacross the current-sensing resistor R/4. Thus, the following relationships substantially hold:

[0045] (1+α)V_REF+V_N1+V_M1<V_DD1  Eq. 10a

[0046] (1+β)V_REF+V_N2+V_M2<V_DD1  Eq. 10b

[0047] (1+χ)V_REF+V_N3+V_M3<V_DD2  Eq. 10c

[0048] (1+δ)V_REF+V_N4+V_M4<V_DD2  Eq. 10d

[0049] Within limits, V_REFcan be divided down to use less headroom and parameters α, β, χ, and δ can be rescaled to obtain the same desired output voltages V_O1-4in accordance with the relationships stated in equations 10a-d.

[0050] FIG. 4 illustrates a schematic diagram of another exemplary multiple-output voltage mirroring circuit 400 in accordance with an embodiment of the invention. The multiple-output voltage mirroring circuit 400 generates a plurality of output voltages derived from a common reference voltage V_REF. The voltage mirroring circuit 400 comprises an operational amplifier 402, a plurality of n-channel field effect transistors (FETs) N1-4, a plurality of current-equalizing resistors R2-4 including current-setting resistor R1, and a plurality of load resistors αR, βR, χR, and δR. The operational amplifier 402 includes a positive input to receive a reference voltage V_REF, a negative input coupled to an end of the current-setting resistor R₁, and an output coupled to the respective gates of FETs N1-4. The current-setting resistor R1 and the current-equalizing resistors R2-4 are coupled respectively between the sources of the FETs N1-4 and ground potential. The load resistors αR and βR are coupled between a first power supply voltage rail V_DD1and the respective drains of FETs N1-2, and load resistors χR, and δR are coupled between a second power supply voltage rail V_DD2and the respective drains of FETs N3-4.

[0051] In operation, the operational amplifier 402 drives FET N1 to force the feedback voltage V_FBto be substantially equal to the reference voltage V_REF(see equation 1). The current I₁through the current-setting resistor R₁is substantially given by the following relationship:

[0052] I₁=V_REF/R  Eq. 11

[0053] In this exemplary embodiment, the FETs N1-4 are substantially matched and the current-setting resistor R1 is substantially matched to the current-equalizing resistor R2-4. This makes the gate-to-source voltages of the FETs N1-4 to be substantially the same (i.e. current mirroring), thereby making the drain currents I_1-4of the FETs N1-4 given substantially by the following relationship:

[0054] I₁=I₂=I₃=I₄=V_REE/R  Eq. 12

[0055] The drain currents I_1-4of FETs N1-4 flow respectively through load resistors αR, βR, χR, and δR. Therefore, the output voltages V_O1-4of the multiple-output voltage mirroring circuit 400 are given substantially by the following equations:

[0056] V_O1=V_DD1−I₁*αR=V_DD1−V_REF/R*αR=V_DD1−αV_REF  Eq. 13a

[0057] V_O2=V_DD1=I₂*βR=V_DD1−V_REF/R*βR=V_DD1−βV_REF  Eq. 13b

[0058] V_O3=V_DD2−I₃*χR=V_DD2−V_REF/R*χR=V_DD2−χVREF  Eq. 13c

[0059] V_O4=V_DD2−I₄*δR=V_DD2−V_REF/R*δR=V_DD2−δV_REF  Eq. 13d

[0060] With regard to sufficient headroom for the voltage mirroring circuit 400 to output the desired output voltages V_O1-4, the supply voltages V_DD1-2need to accommodate the respective voltage drops αV_REF, βV_REF, χV_REF, and δV_REFacross the respective load resistors αR, βR, χR, and δR, the voltage drops V_N1-4across the respective FETs N1-4, and the voltage drops V_REFacross the respective resistors R_1-4. Thus, the following relationships substantially hold:

[0061] (1+α)V_REF+V_N1<V_DD1  Eq. 14a

[0062] (1+β)V_REF+V_N2<V_DD1  Eq. 14b

[0063] (1+χ)V_REF+V_N3<V_DD2  Eq. 14c

[0064] (1+δ)V_REF+V_N4<V_DD2  Eq. 14d

[0065] Within limits, V_REFcan be divided down to use less headroom and parameters α, β, χ, and δ can be rescaled to obtain the same desired output voltages V_O1-4in accordance with the relationships stated in equations 14a-d.

[0066] FIG. 5 illustrates a schematic diagram of an exemplary voltage mirroring circuit 500 with cascading control in accordance with an embodiment of the invention. The voltage mirroring circuit 500 operates similarly as to voltage mirroring circuit 100 in that it generates an output voltage V_Othat is derived from a reference voltage V_REF. The voltage mirroring circuit 500 comprises an operational amplifier 502, a first n-channel field effect transistor (FET) N1, a second n-channel field effect transistor (FET) N2, a current-setting resistor R, and a load resistive resistor αR. The operational amplifier 502 includes a positive input to receive a reference voltage V_REF, a negative input coupled to the source of the FET N1, an output coupled to the gate of the FET N1, and a cascode biasing output V_CAScoupled to the gate of the second FET N3. The current-setting resistor R is coupled between the source of the FET N1 and to a ground potential. The source of the second FET N3 is coupled to the drain of the first FET N1. The load resistor αR is coupled between the power supply voltage rail V_DDand the drain of the FET N3.

[0067] In operation, the operational amplifier 502 sets the gate voltage V_GATEof the FET N1 such that the feedback voltage V_FBapplied to the negative input of the operational amplifier 502 is substantially equal to the reference voltage V_REFapplied to the positive input of the operational amplifier 502 (See equation 1). Since the feedback voltage V_FBis across the current-setting resistor R, the current I through the current-setting resistor R is approximately V_REF/R (See equation 2). The current I also flows through the FETs N1 and N3 as well as through the load resistor αR. Thus, the output voltage V_Oof the voltage mirroring circuit 500, taken off the drain of the FET N3, is substantially V_DD−αV_REF(See equation 3).

[0068] In this embodiment, the cascoding FET N3 is provided to ensure that the drain-to-source voltage (V_DS) of FET N1 is maintained substantially constant. This substantially increases the output impedance of the voltage mirroring circuit 500, thereby making the circuit 500 substantially more stable with variation in the output load of the circuit 500. In order to properly maintain V_DSof FET N1 substantially constant, the cascode voltage V_CASapplied to the gate of FET N3 (assuming N3 is substantially equal in size to N1) is given by the following relationship:

[0069] V_CAS≧V_GATE+V_DS(sat)N1  Eq. 15

[0070] where V_GATEis the voltage applied to the gate of FET N1 and V_DS(sat)N1 is the saturation voltage of FET N1 at current I. The cascode voltage V_CASshould not be too large or the headroom of the voltage mirror will be affected. The cascode voltage V_CASmay be generated by the operational amplifier 502 as shown or by some other device or circuit.

[0071] With regard to sufficient headroom for the voltage mirroring circuit 500 to output the desired output voltage V_O, the supply voltage V_DDneeds to accommodate the voltage drop αV_REFacross the load resistor αR, the voltage drop V_N3across the FET N3, the voltage drop V_N1across the FET N1, and the voltage drop V_REFacross the current-sensing resistor R. Thus, the following relationships substantially hold:

[0072] (1+α)V_REF+V_N1+V_N3<V_DD  Eq. 16a

[0073] or

[0074] αV_REF+V_CAS+V_N3(sat)<V_DD  Eq. 16b

[0075] Within limits, V_REFcan be divided down to use less headroom and parameter α can be rescaled to obtain the same desired output voltage V_Oin accordance with the relationships stated in equations 16a-b.

[0076] FIG. 6 illustrates a schematic diagram of an exemplary multiple output voltage mirroring circuit 600 with cascoding control in accordance with an embodiment of the invention. The multiple-output voltage mirroring circuit 600 operates similarly to voltage mirroring circuit 300 in that it generates a plurality of output voltages derived from a common reference voltage V_REF. The voltage mirroring circuit 600 comprises an operational amplifier 602, a plurality of n-channel field effect transistors (FETs) N11-14, a plurality of cascoding FETs N31-34, a plurality of source-biasing transistors R_M1-4, a current-setting resistor R/4, and a plurality of load resistors αR, βR, χR, and δR.

[0077] The operational amplifier 602 includes a positive input to receive a reference voltage V_REF, a negative input coupled to an end of the current-setting resistor R/4, an output coupled to the respective gates of FETs N11-14, and a cascode biasing output V_CAScoupled to the gates of the cascoding FETs N31-34. The other end of the current-setting resistor R/4 may be coupled to ground potential. The source-biasing resistors R_M1-4are coupled between the current-setting resistor R/4 and the respective sources of the FETs N11-14. The sources of the cascading FETs N31-34 are coupled to the respective drains of the FETs N11-N14. The load resistors αR and βR are coupled between a first power supply voltage rail V_DD1and the respective drains of FETs N31-32, and load resistors χR, and δR are coupled between a second power supply voltage rail V_DD2and the respective drains of FETs N33-34.

[0078] In operation, the operational amplifier 602 drives the plurality of FETs N11-14 to force the feedback voltage V_FBto be substantially equal to the reference voltage V_REF(see equation 1). The current I through the current-setting resistor R/4 is 4*V_REF/R (see equation 7). In this exemplary embodiment, the FETs N11-14 are substantially matched and the source-biasing resistors R_M1-4are substantially matched. Therefore, the drain currents I_1-4of the FETs N11-14 are substantially equal to V_REF/R (see equation 8). The drain currents I_1-4of FETs N11-14 flow respectively through load resistors αR, βR, χR, and δR. Therefore, the output voltages V_O1-4of the multiple-output voltage mirroring circuit 600 are given substantially by equations 9a-d.

[0079] In this embodiment, the cascading FETs N31-34 are provided to ensure that the respective drain-to-source voltage (V_DS1-4) of FET N11-14 are maintained substantially constant. This substantially increases the respective output impedances of the voltage mirroring circuit 600, thereby making the circuit 600 substantially more stable with variation in the output loads of the circuit 600. In order to properly maintain the respective V_DS1-4of FET N11-14 substantially constant, the cascode voltage V_CASapplied to the gates of FET N31-34 should be as stated in equation 16a or 16b.

[0080] With regard to sufficient headroom for the voltage mirroring circuit 600 to output the desired output voltages V_O1-4, the supply voltages V_DD1-2need to accommodate the respective voltage drops αV_REF, βV_REF, χV_REF, and δV_REFacross the respective load resistors αR, βR, χR, and δR, the voltage drops V_N31-34across the respective FETs N31-34, the voltage drops V_N11-14across the respective FETs N11-14, the voltage drops V_M1-4across the respective source-biasing resistors R_M1-4, and the voltage drop V_REFacross the current-sensing resistor R/4. Thus, the following relationships substantially hold:

[0081] (1+α)V_REF+V_N31+V_N11+V_M1<V_DD1  Eq. 17a

[0082] (1+β)V_REF+V_N32+V_N12+V_M2<V_DD1  Eq. 17b

[0083] (1+χ)V_REF+V_N33+V_N13+V_M3<V_DD2  Eq. 17c

[0084] (1+δ)V_REF+V_N34+V_N14+V_M4<V_DD2  Eq. 17d

[0085] or

[0086] αV_REF+V_CAS+V_N31(sat)<V_DD  Eq. 17e

[0087] βV_REF+V_CAS+V_N32(sat)<V_DD  Eq. 17f

[0088] χV_REF+V_CAS+V_N33(sat)<V_DD  Eq. 17g

[0089] δV_REF+V_CAS+V_N34(sat)<V_DD  Eq. 17h

[0090] Within limits, V_REFcan be divided down to use less headroom and parameters α, β, χ, and δ can be rescaled to obtain the same desired output voltages V_O1-4in accordance with the relationships stated in equations 17a-h.

[0091] In the above exemplary embodiments, the reference voltage V_REFand the current-setting resistor were referenced from the same voltage potential. That is, one end of the current-setting resistor was connected to ground potential and the reference voltage V_REFis that much above ground potential. This need not be the case, as is explained by the following exemplary embodiment.

[0092] FIG. 7 illustrates a schematic diagram of another exemplary voltage mirroring circuit 700 in accordance with an embodiment of the invention. The voltage mirroring circuit 700 comprises an operational amplifier 702, a unity-gain amplifier 704, an n-channel FET N1, a current-setting resistor R, a load resistor αR, a reference voltage source V_REF, and an offset voltage source V_ROFF. The operational amplifier 702 includes a positive input coupled to the reference voltage source V_REF, a negative input coupled to the source of the FET N1 and an end of the current-setting resistor R, and an output coupled to the gate of the FET N1. The other end of the current-setting resistor R is coupled to the output of the unity gain amplifier 704, which in turn, has an input coupled to the offset voltage source V_ROFF. Both the reference voltage source V_REFand the offset voltage source V_ROFFare referenced from ground potential.

[0093] In operation, the operational amplifier 702 sets the gate voltage V_GATEof the FET N1 such the feedback voltage V_FBapplied to the negative input of the operational amplifier 702 is substantially equal to the reference voltage V_REFapplied to the positive input of the operational amplifier 702 (see equation 1). Accordingly, the current I through the current-setting resistor R is equal to the voltage drop (V_REF−V_ROFF) over the resistance R. Thus, the following relationship substantially holds:

[0094] I=(V_REF−V_ROFF)/R  Eq. 18

[0095] The current I also flows through the channel of the FET N1 and through the load resistor αR. Thus, the output voltage V_Oof the voltage mirroring circuit 700, taken off the drain of the FET N1, is given substantially by the following relationship:

[0096] V_O=V_DD−((V_REF−V_ROFF)/R*αR)=V_DD−α(V_REF−V_ROFF)  Eq. 19

[0097] As equation 19 illustrates, the voltage mirroring circuit 700 generates an output voltage VO that derives from a difference between reference voltage V_REFand an offset voltage V_ROFF. Thus, the voltage mirroring circuit 700 can be used as a comparator or a differential amplifier. The voltage V_ROFFcan also be made time-variable. In this case, the output voltage V_Owould be modulated V_ROFF(t) and ratioed α.

[0098] Although the exemplary embodiments described above used field effect transistors (FETs), it shall be understood that they can be implemented in bipolar technology. Also the channel doping types of the FETs can be interchanged (i.e. an n-channel transistor can be interchanged with a p-channel transistor, and vice-versa). The resistors can be interchanged with any type of resistive elements.

[0099] In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.