Method and apparatus to prefetch sequential pages in a multi-stream environment

[0002] The present invention relates to a method and apparatus for determining information that is to be prefetched in a multi-stream environment

[0003] Modern storage adapters and controllers typically have some cache memory to capture temporal locality, which is the property that if a page is referenced recently, it is likely to be referenced again in the near future. However, certain data streams also exhibit spatial locality. That is, when a page is referenced, the next few pages are likely to be referenced soon. Sequential prefetch is a well-known mechanism to capture spatial locality, which has been done in single-stream environments such as file system and database software systems. A single-stream environment is an environment in which logical information is available to identify potential sequential streams of reference. For example, in a file system, the references to a file are likely to be sequential in nature.

[0004] Problems arise when implementing prefetch in a multi-stream storage environment. In a multi-stream environment, each stream is independently referencing storage locations, resulting in a reference stream presented to the storage device that is an aggregate of the individual streams. The aggregate stream will likely not possess significant spatial locality, even though each individual stream may. A further problem arises in that the prefetch scheme cannot use too much memory, because some storage adapters have limited memory.

[0005] A need arises for a technique which can detect sequential streams from among the aggregate reference stream and yet requires relatively little memory to operate.

[0006] The present invention is a system and method for determining information that is to be prefetched in a multi-stream environment which can detect sequential streams from among the aggregate reference stream and yet requires relatively little memory to operate. It is uniquely adapted for use in a multi-stream environment, in which multiple data accessing streams are performing sequential accesses to information independently of each other. The present invention detects patterns of sequential accesses from among the jumble of accesses that the aggregate access stream presents to the storage system.

[0007] In accordance with the method of the present invention, a reference address referencing stored information is received. A matching run is found. A count corresponding to the run is updated. If the count exceeds a predetermined threshold, an amount of information to prefetch is determined. If a predetermined fraction of the determined amount of information to prefetch must still be retrieved, the determined amount of information is retrieved. A matching run may be found by searching a stack comprising a plurality of entries to find an entry corresponding to the reference address. Each of the plurality of entries may be associated with a maximum accessed address, a forward range, and a backward range, and the searching step may comprise searching the plurality of stack entries in one direction starting at an end of the stack and determining whether the reference address is between (maximum accessed address−backward range) and (maximum accessed address+forward range) for each stack entry until a matching stack entry is found.

[0008] The method may further comprise rearranging the plurality of stack entries according to a replacement policy. The replacement policy may be a first-in, first-out replacement policy. Alternatively, other replacement schemes may be used. The plurality of stack entries may further be rearranged so as to make the referenced information eligible for immediate replacement.

[0009] An amount of information to prefetch may be determined based on the count corresponding to the run and on a size of the prefetch buffer. The count may be updated for each reference address matching the run or for each unique reference address matching the run.

[0010] The details of the present invention, both as to its structure and operation, can best be understood by referring to the accompanying drawings, in which like reference numbers and designations refer to like elements.

[0011] FIG. 1 is an exemplary block diagram of a storage system, according to the present invention.

[0012] FIG. 2 is a more detailed block diagram of a prefetch buffer shown in FIG. 1.

[0013] FIG. 3 is a more detailed block diagram of a sequential detector shown in FIG. 1.

[0014] FIG. 4 is an example of information used by the sequential detector shown in FIG. 1.

[0015] FIG. 5 is an exemplary flow diagram of the operation of the sequential detector shown in FIG. 1.

[0016] FIG. 6 is an exemplary flow diagram of the operation of the prefetch buffer shown in FIG. 1.

[0017] The present invention is system and method for determining information that is to be prefetched in a multi-stream environment which can detect sequential streams from among the aggregate reference stream and yet requires relatively little memory to operate. It is uniquely adapted for use in a multi-stream environment, in which multiple data accessing streams are performing sequential accesses to information independently of each other. The present invention detects patterns of sequential accesses from among the jumble of accesses that the aggregate access stream presents to the storage system.

[0018] An exemplary block diagram of a storage system 100, according to the present invention, is shown in FIG. 1. System 100 includes storage media 102, read channel 104, read cache 106, write channel 108, write buffer 110, prefetch buffer 112, sequential detector 114 and host interface 116. Storage media 102 stores information and may output signals representing that information. Storage media 102 is typically a magnetic medium, such as hard or floppy disk or tape, or may be another type of medium. For example, storage media 102 may be an optical medium, such as optical disk or holographic storage, or an electronic medium such as random-access memory (RAM), read-only memory (ROM), etc. Read channel 104 is circuitry that converts the signal from storage media 104 into digital data signals representing information. Read cache 106 is memory, typically electronic memory, which temporarily stores information that has been read from storage media 102 before the information is transmitted to host system 118 via host interface 116. Host interface 116 interfaces with host system 118 in order to transmit information read from storage media 102 to host system 118 and to receive information from host system 118 for writing to storage media 102. Write buffer 110 is memory, typically electronic memory, which temporarily stores information that has been received from host system 118 via host interface 116 before the information is written to storage media 102. Write channel 108 is circuitry that converts the digital data signal representing information stored in write buffer 110 to signals used by storage media 102 to store information. Prefetch buffer 112 is memory, typically electronic memory, which stores the information that has been prefetched from storage media 102. Sequential detector 114 determines when sequential prefetch is to be started, when sequential prefetch is to be stopped, the amount of information to prefetch and the information that is to be kept in prefetch buffer 112.

[0019] Prefetch buffer 112 is shown in more detail in FIG. 2. Prefetch buffer 112 includes a memory 202 and a control block 204. Memory 202 stores information read from storage media 102, while control block 204 controls the storage, output, and replacement of information in memory 202. Typically, information stored in memory 202 is organized in pages, with the unit of storage, output, or replacement being one page. FIG. 2 shows representative pages 204A, 204B, 204C and 204Z for the memory 202. Control block 204 controls the replacement of pages in memory 202 based on several parameters, including the memory size and its replacement policy. Control block 204 accepts control signals from sequential detector 114, which determines when information is to be prefetched and the amount of information to be prefetched.

[0020] In a preferred embodiment, the memory size and replacement policy are defined as follows: The size of memory 202 is 256 pages of 4 kilobytes each, which yields a memory size of 1 megabyte. The pages in memory 202 are replaced in a first-in, first-out (FIFO) replacement scheme, as controlled by control block 204. When a page is referenced, control block 204 places the page at the end of the FIFO, which makes the page eligible for replacement immediately. This arrangement is advantageous when the adapter memory size is smaller than host memory size.

[0021] Although, in FIGS. 1 and 2, prefetch buffer 112 is shown as separate from read cache 106, one of skill in the art would recognize that memory 202 may be implemented in combination with read cache 106. For clarity, the prefetch buffer is described separately from the read cache.

[0022] Sequential detector 114 is shown in more detail in FIG. 3. Sequential detector 114 detects sequences of accesses that are termed “runs”, which are used to group pages that are accessed. Sequential detector 114 includes a range comparator 302, a stack 304, run counters 306A-N, and threshold detector 308

[0023] Stack 304 includes a plurality of stack entries 310A-N and a control block 312. In a preferred embodiment, stack 304 includes 16 entries. When an address is referenced, the reference address is input to the stack control block 312, which searches down the stack to find the first matching run.

[0024] In order to find the matching run, range comparator 302 compares the input reference address 314 with parameters associated with each entry in stack 304. In a preferred embodiment, three parameters are considered: maximum accessed address, backward range, and forward range. If a reference address 314 falls between (maximum accessed address−backward range) and (maximum accessed address+forward range), address 314 belongs to the corresponding run. The backward and forward ranges are useful in order to capture access patterns that are not consecutively or strictly sequential. If the reference address is bigger than the maximum accessed address, the maximum accessed address associated with that run is updated accordingly.

[0025] Each run counter 306A-N is associated with an entry in stack 304. In a preferred embodiment, each counter is incremented each time an access that is part of the run corresponding to the associated stack entry occurs. In another embodiment, the counter is incremented each time a fresh or new page is accessed in the run. Threshold detector 308 detects when a counter has exceeded a predetermined threshold value, in which case, the run is determined to be a sequential run.

[0026] An example of information used by sequential detector 114 is shown in FIG. 4. Each entry in stack 304, for example entry 402 of FIG. 4, has associated with it a maximum access address 404, a forward range 406, a backward range 408, and a run counter 410. Maximum accessed address 404 is the address of the page having the highest address that has been addressed in the run corresponding to stack entry 402. Forward range 406 and backward range 408 specify a range of addresses around maximum accessed address 404 which will be considered part of the run. Run counter 410 stores the number of accesses that have occurred to the corresponding run.

[0027] An exemplary flow diagram of the operation of sequential detector 114 is shown in FIG. 5. In step 502, a reference address is received as a result of stored information being referenced. In step 504, the stack is searched to find a matching run. In a preferred embodiment, the matching run is found by searching the stack entries downwards and determining whether the reference address falls between (maximum accessed address−backward range) and (maximum accessed address+forward range) for each stack entry until a matching entry is found. Thus, the first matching entry in the stack will be found. In step 506, it is determined whether a matching run is found. If not, then in step 508, the entry at the bottom of the stack, which corresponds to the run that has spent the longest time in the stack without being accessed of any in the stack, is deleted. A new stack entry, corresponding to a new run including the reference address is added to the top of the stack, where the top of the stack is the end that is searched first in step 504. Information relating to the run, such as maximum accessed address, forward range, and backward range are stored and the run counter is incremented.

[0028] If, in step 508, a matching run is found, then in step 510, the entry corresponding to the matching run is moved to the top of the stack and the corresponding run counter is incremented. Although in this preferred embodiment, a least-recently-used (LRU) replacement policy is used, as described, one of skill in the art would recognize that the present invention contemplates other replacement policies as well. In one embodiment of the present invention, a run counter is incremented each time a reference is made to an address in the run. In another embodiment of the present invention, a run counter is incremented each time a unique reference is made to an address in the run.

[0029] In step 512, the value stored in the run counter is compared with a predetermined threshold. In step 514, in is determined whether the value in the run counter exceeds the predetermined threshold. If so, the run is determined to be a sequential run and, in step 516, a prefetch amount is determined based on the run counter value, prefetch buffer size, and other system parameters. In step 518, the cache and prefetch buffer are checked to determine the number of pages, of those that are to be prefetched, that are already in the cache or prefetch buffer. Those pages that are already in the cache or prefetch buffer need not be prefetched again, as they are already available without accessing the storage media. Those pages that are not already in the cache or prefetch buffer do need to be prefetched. In step 520, a fraction is generated which represents the proportion of pages do need to be prefetched to the total amount that is to be prefetched. If the fraction that still must be prefetched exceeds a predetermined fraction, then in step 522 the determined prefetch amount is retrieved from the storage media and placed in the prefetch buffer, where it will be quickly available for access by the host system.

[0030] An exemplary flow diagram of the operation of prefetch buffer 112 is shown in FIG. 6. In step 602, the sequential detector transmits a signal to prefetch buffer control block 204 to prefetch a quantity of information. In step 604, control block 204 retrieves the information from the storage media and stores the information in memory 202, organized into pages. In addition, pages in memory 202 may be replaced based on a first-in, first-out (FIFO) replacement scheme. In step 606, a page in memory 202 is referenced and control block 204 places the page at the end of the FIFO, which makes the page eligible for replacement immediately. This arrangement is advantageous when the adapter memory size is smaller than host memory size.

[0031] One of ordinary skill in the art would recognize that the present invention may be implemented using a variety of techniques. For example, the present invention may be implemented using discrete or integrated electronic circuitry, state machines, programmed special-purpose processors, programmed general-purpose processors, software, firmware, and combinations of these and other techniques. Likewise it is important to note that while the present invention has been described in the context of a fully functioning data processing system, those of ordinary skill in the art will appreciate that the processes of the present invention are capable of being distributed in the form of a computer readable medium of instructions and a variety of forms and that the present invention applies equally regardless of the particular type of signal bearing media actually used to carry out the distribution. Examples of computer readable media include recordable-type media such as floppy disc, a hard disk drive, RAM, and CD-ROM's, as well as transmission-type media, such as digital and analog communications links.

[0032] Although specific embodiments of the present invention have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments, but only by the scope of the appended claims.