Management of resets for interdependent dual small computer standard interface (SCSI) bus controller

[0002] The present invention concerns communication between devices within a computing system and pertains particularly to management of resets for power failure and to hot swap devices connected through Small Computer Standard Interface (SCSI) buses to a dual SCSI bus controller.

[0003] In one category of network architectures, network devices are connected to a common communication bus. When one of the network devices desires to initiate a transfer of data over the bus, the network device will attempt to gain control of the bus. Once the network device has control of the bus, the transfer of data may be performed.

[0004] For example, the Small Computer Standard Interface (SCSI) is an input/output (I/O) interface connection used for personal computers. SCSI was originated as a disk memory interface and became a universal high speed I/O protocol. In communication bus systems which operate in accordance with the SCSI protocol, SCSI devices connected to a communication bus have a fixed network access priority. In the SCSI bus protocol, contention resolution is accomplished by granting bus control to the SCSI device which has the highest network access priority among the SCSI devices which, during an arbitration time period, request control of the communication bus.

[0005] Hardware implementation of a communication bus which uses the SCSI protocol is generally done using a 50 conductor flat ribbon or round bundle cable of characteristic impedance of 100 ohm. The nominal distance is six meters in single ended mode and 25 meters in differential mode. For more information on the SCSI protocol, see the American National Standard for SCSI-2, available as Document X3.131-199X from Global Engineering Documents, 2805 McGaw, Irvine, Calif. 92714.

[0006] It is necessary to perform a reset of a SCSI bus upon start-up, after a power failure, to remove devices from the SCSI bus and to add devices from the SCSI bus. However, when there are multiple controllers for a single SCSI bus, this requires coordination to determine which controller will oversee the SCSI bus reset.

[0007] In accordance with the preferred embodiment of the present invention, a device includes a first SCSI bus, a second SCSI bus, a first bus controller slot, a second bus controller slot and a bus controller in one of the first bus controller slot and the second bus controller slot. The bus controller includes reset circuitry for generating a SCSI bus reset signal. The SCSI bus reset signal being used to reset the first SCSI bus when the bus controller is in the first bus controller slot and the first SCSI bus is isolated from the second SCSI bus. The SCSI bus reset signal being used to reset the second SCSI bus when the bus controller is in the second bus controller slot and the first SCSI bus is isolated from the second SCSI bus. The SCSI bus reset signal is used to reset both the first SCSI bus and the second SCSI bus when the first SCSI bus and the second SCSI bus are bridged and one of the following conditions is met: the bus controller is in the first bus controller slot, or the bus controller is in the second bus controller slot and the first bus controller slot is empty.

[0008] For example, the device is a just a bunch of disks (JBOD) storage device. In the preferred embodiment, a first backplane connector connects the bus controller to the first SCSI bus. A second backplane connector connects the bus controller to the second SCSI bus. An isolator circuit is capable of electrically isolating the first backplane connector from the second backplane connector and is capable for connecting the first backplane connector to the second backplane connector. When the isolator circuit connects the first backplane connector to the second backplane connector this bridges the first SCSI bus and the second SCSI bus. When the bus controller is in the second bus controller slot and another bus controller is in the first bus controller, the second backplane connector isolator circuit isolates the first backplane connector from the second backplane connector. Additionally in the preferred embodiment, a first frontplane connector allows connection of the bus controller to a first host. A second frontplane connector allows connection of the bus controller to a second host.

[0009] The present invention provides for efficient reset of SCSI buses for power failure and for hot swapping of devices on SCSI networks.

[0010] FIG. 1 is a simplified block diagram showing two bus controller cards used to control ten SCSI disk drives connected on two individual SCSI busses in accordance with a preferred embodiment of the present invention.

[0011] FIG. 2 shows high level logic flow used to generate a SCSI bus reset in accordance with a preferred embodiment of the present invention.

[0012] FIG. 3 shows logic used to implement a delay circuit in accordance with a preferred embodiment of the present invention.

[0013] FIG. 4 shows logic used to generate an overall SCSI bus insert/removal signal in accordance with a preferred embodiment of the present invention.

[0014] FIG. 5 shows logic used to generate a SCSI bus reset signal in accordance with a preferred embodiment of the present invention.

[0015] FIG. 1 is a simplified block diagram of a Just a Bunch of Disks (JBOD) enclosure that houses up to ten SCSI disk drives on two individual SCSI buses with five disk slots apiece. For example, to an even SCSI bus 19 is connected a disk drive 11, a disk drive 12, a disk drive 13, a disk drive 14 and a disk drive 15. A disk drive 31, a disk drive 32, a disk drive 33, a disk drive 34 and a disk drive 35 are connected to an odd SCSI bus 39.

[0016] A bus controller card (BCC) 18 in a slot A of the JBOD enclosure is connected to even SCSI bus 19 through a backplane connector 23. Bus controller 18 is connected to odd SCSI bus 39 through a backplane connector 27. Bus controller card 18 through a frontplane connector 21 interfaces with a host 16 (external to the JBOD enclosure). Bus controller card 18 through a frontplane connector 17 interfaces with a host 17 (external to the JBOD enclosure). Host 16 and host 17 are connected to bus controller card 18 in SCSI differential mode. A voltage differential mode to single ended mode (LVD to SE) converter 22 is used to convert SCSI signals from differential mode to single ended mode. A single ended node SCSI Enclosure Services (SES) chip 24 stubs off of the bus between LVD to SE converter 22 and a single ended to single ended (SE to SE) isolator 26. SES 24 and SE to SE isolator 26 allow bus controller card 18 to be configured to access odd SCSI bus 39 and thus access all disk drives on both busses. This allows greater flexibility in configuring the JBOD enclosure, allows hot swapping of failing cards and allows a single card solution for a bridged SCSI Bus implementation. Reset circuitry 28 is used by BCC 18 to generate SCSI bus resets.

[0017] A bus controller card (BCC) 38 in a slot B of the JBOD enclosure is connected to odd SCSI bus 39 through a backplane connector 43. Bus controller 38 is connected to even SCSI bus 19 through a backplane connector 47. Bus controller card 38 through a frontplane connector 41 interfaces with a host 36 (external to the JBOD enclosure). Bus controller card 38 through a frontplane connector 37 interfaces with a host 37 (external to the JBOD enclosure). Host 36 and host 37 are connected to bus controller card 38 in SCSI differential mode. A voltage differential mode to single ended mode (LVD to SE) converter 42 is used to convert SCSI signals from differential mode to single ended mode. A single ended node SCSI Enclosure Services (SES) chip 44 stubs off of the bus between LVD to SE converter 42 and a single ended to single ended (SE to SE) isolator 46. SES 44 and SE to SE isolator 46 allow bus controller card 38 to be configured to access even SCSI bus 19 and thus access all disk drives on both busses. However, in the preferred embodiment, in full bus mode SE to SE isolator 26 provides connection (bridging) between even SCSI bus 19 and odd SCSI bus 39 and isolator 46 is disabled. In split bus mode both SE to SE isolator 26 and SE to SE isolator 46 are disabled. Reset circuitry 48 is used by BCC 38 to generate SCSI bus resets.

[0018] In order to avoid data corruption, even SCSI bus 19 and odd SCSI bus 39 are reset by the JBOD enclosure in two instances, provided the pertinent circuitry is enabled. The first instance in which even SCSI bus 19 and odd SCSI bus 39 are reset by the JBOD enclosure is whenever a disk drive is inserted or removed from even SCSI bus 19 or odd SCSI bus 39. The second instance in which even SCSI bus 19 and odd SCSI bus 39 are reset by the JBOD enclosure is whenever AC Power is removed from the JBOD enclosure.

[0019] Enabling the resets allows the JBOD enclosure to operate independently. Disabling the resets allows the JBOD enclosure to operate behind an array controller.

[0020] Reset circuitry that controls SCSI bus resets for all the disk drives must take into account that there are two bus controller cards. Also the reset circuitry must take into account the configuration of bus controller card 18 and bus controller card 38 as to whether each BCC is in bridged or split bus mode. The reset circuitry must allow control to be passed from one BCC to the other when a BCC is inserted or removed from the JBOD enclosure. Also, the hot swap and AC power fail conditions drive the Reset circuit separately.

[0021] Table 1 below illustrates how bus controller card 18 (in slot A of the JBOD enclosure) and bus controller card 39 (in slot B of the JBOD enclosure) reset signals depending on bus configuration.

[0022] FIG. 2 shows high level logic flow for the reset circuitry within each BCC that is used to generate a SCSI bus reset in accordance with a preferred embodiment of the present invention. The reset circuitry includes a delay circuit 51, an insert/removal circuit 52, a primary controller identification state machine 53, a hot plug SCSI reset state machine 54 and power fail combinatorial circuitry 55 connected as shown.

[0023] Delay circuit 51 receives a ten bit mated 2 slot x signal 49 and produces a ten bit single clock delayed mated 2 slot x signal 50 and a ten bit double clock delayed mated 2 slot x signal 56. Insert removal circuit 52 receives ten bit single clock delayed mated 2 slot x signal 50 and ten bit double clock delayed mated 2 slot x signal 56 and produces an even SCSI Bus insert/removal signal 57, an odd SCSI bus insert/removal circuit signal 58 and an overall SCSI bus insert/removal signal 59.

[0024] Primary controller identification state machine 53 receives a card slot identifier signal 64, a card detection signal 65 and a state machine clock 73. Primary controller identification state machine 53 produces a primary controller signal 63.

[0025] Hot plug SCSI reset state machine 54 receives even SCSI Bus insert/removal signal 57, odd SCSI bus insert/removal circuit signal 58, overall SCSI bus insert/removal signal 59, primary controller signal 63, an enable SCSI bus bridge signal 64, a host swap SCSI bus reset enable 65 and state machine clock 73. Hot plug SCSI reset state machine 54 produces a hot swap SCSI bus reset signal 67.

[0026] Power fail combinatorial circuitry 55 receives hot swap SCSI bus reset signal 67, a power failure SCSI bus reset enable signal 68, a power supply A valid signal 69, a power supply B valid signal 70, a power supply A fault signal 71, a power supply B fault signal 72 and state machine clock 73. Power fail combinatorial circuitry 55 produces a (Not) SCSI bus reset signal 74.

[0027] Table 2 below gives signal definitions for each of the signals shown in FIG. 2.

[0028] FIG. 3 shows logic used to implement a delay circuit 51 shown in FIG. 2. Ten bit mated 2 slot x signal 49 is shown to include a mated 2 slot 0 signal 100, a mated 2 slot 1 signal 101, a mated 2 slot 2 signal 102, a mated 2 slot 3 signal 103, a mated 2 slot 4 signal 104, a mated 2 slot 5 signal 105, a mated 2 slot 6 signal 106, a mated 2 slot 7 signal 107, a mated 2 slot 8 signal 108 and a mated 2 slot 9 signal 109.

[0029] Single Clock Delayed Mated 2 Slot X signal 50 is shown to include a double clock delayed mated 2 slot 0 signal 120, a double clock delayed mated 2 slot 1 signal 121, a double clock delayed mated 2 slot 2 signal 122, a double clock delayed mated 2 slot 3 signal 123, a double clock delayed mated 2 slot 4 signal 124, a double clock delayed mated 2 slot 5 signal 125, a double clock delayed mated 2 slot 6 signal 126, a double clock delayed mated 2 slot 7 signal 127, a double clock delayed mated 2 slot 8 signal 128 and a double clock delayed mated 2 slot 9 signal 129.

[0030] Double Clock Delayed Mated 2 Slot X signal 56 is shown to include a single clock delayed mated 2 slot 0 signal 110, a single clock delayed mated 2 slot 1 signal 111, a single clock delayed mated 2 slot 2 signal 112, a single clock delayed mated 2 slot 3 signal 113, a single clock delayed mated 2 slot 4 signal 114, a single clock delayed mated 2 slot 5 signal 115, a single clock delayed mated 2 slot 6 signal 116, a single clock delayed mated 2 slot 7 signal 117, a single clock delayed mated 2 slot 8 signal 118 and a single clock delayed mated 2 slot 9 signal 119.

[0031] A register 92 receives mated 2 slot 0 signal 100, mated 2 slot 1 signal 101, mated 2 slot 2 signal 102, mated 2 slot 3 signal 103, mated 2 slot 4 signal 104, mated 2 slot 5 signal 105, mated 2 slot 6 signal 106, mated 2 slot 7 signal 107, mated 2 slot 8 signal 108, mated 2 slot 9 signal 109 and state machine clock 73 and produces single clock delayed mated 2 slot 0 signal 110, single clock delayed mated 2 slot 1 signal 111, single clock delayed mated 2 slot 2 signal 112, single clock delayed mated 2 slot 3 signal 113, single clock delayed mated 2 slot 4 signal 114, single clock delayed mated 2 slot 5 signal 115, single clock delayed mated 2 slot 6 signal 116, single clock delayed mated 2 slot 7 signal 117, single clock delayed mated 2 slot 8 signal 118 and single clock delayed mated 2 slot 9 signal 119.

[0032] A register 93 receives single clock delayed mated 2 slot 0 signal 110, single clock delayed mated 2 slot 1 signal 111, single clock delayed mated 2 slot 2 signal 112, single clock delayed mated 2 slot 3 signal 113, single clock delayed mated 2 slot 4 signal 114, single clock delayed mated 2 slot 5 signal 115, single clock delayed mated 2 slot 6 signal 116, single clock delayed mated 2 slot 7 signal 117, single clock delayed mated 2 slot 8 signal 118, single clock delayed mated 2 slot 9 signal 119. and state machine clock 73 and produces double clock delayed mated 2 slot 0 signal 120, double clock delayed mated 2 slot 1 signal 121, double clock delayed mated 2 slot 2 signal 122, double clock delayed mated 2 slot 3 signal 123, double clock delayed mated 2 slot 4 signal 124, double clock delayed mated 2 slot 5 signal 125, double clock delayed mated 2 slot 6 signal 126, double clock delayed mated 2 slot 7 signal 127, double clock delayed mated 2 slot 8 signal 128 and double clock delayed mated 2 slot 9 signal 129.

[0033] FIG. 4 shows logic used to implement insert/removal circuit 52. A logic XOR gate 130 performs a logic XOR operation on single clock delayed mated 2 slot 0 signal 110 and double clock delayed mated 2 slot 0 signal 120. A logic XOR gate 131 performs a logic XOR operation on single clock delayed mated 2 slot 0 signal 111 and double clock delayed mated 2 slot 0 signal 121. A logic XOR gate 132 performs a logic XOR operation on single clock delayed mated 2 slot 0 signal 112 and double clock delayed mated 2 slot 0 signal 122. A logic XOR gate 133 performs a logic XOR operation on single clock delayed mated 2 slot 0 signal 113 and double clock delayed mated 2 slot 0 signal 123. A logic XOR gate 134 performs a logic XOR operation on single clock delayed mated 2 slot 0 signal 114 and double clock delayed mated 2 slot 0 signal 124.

[0034] A logic OR gate 140 performs a logic OR on the output of logic XOR gate 130, logic XOR gate 131, logic XOR gate 132, logic XOR gate 133, logic XOR gate 134 to produce even SCSI Bus insert/removal signal 57.

[0035] A logic XOR gate 135 performs a logic XOR operation on single clock delayed mated 2 slot 0 signal 115 and double clock delayed mated 2 slot 0 signal 125. A logic XOR gate 136 performs a logic XOR operation on single clock delayed mated 2 slot 0 signal 116 and double clock delayed mated 2 slot 0 signal 126. A logic XOR gate 137 performs a logic XOR operation on single clock delayed mated 2 slot 0 signal 117 and double clock delayed mated 2 slot 0 signal 127. A logic XOR gate 138 performs a logic XOR operation on single clock delayed mated 2 slot 0 signal 118 and double clock delayed mated 2 slot 0 signal 128. A logic XOR gate 139 performs a logic XOR operation on single clock delayed mated 2 slot 0 signal 119 and double clock delayed mated 2 slot 0 signal 129.

[0036] A logic OR gate 141 performs a logic OR on the output of logic XOR gate 135, logic XOR gate 136, logic XOR gate 137, logic XOR gate 138, logic XOR gate 139 to produce odd SCSI Bus insert/removal signal 58.

[0037] A logic OR gate 142 performs a logic OR on even SCSI Bus insert/removal signal 57 and odd SCSI Bus insert/removal signal 58. A logic AND gate 143 performs a logic AND on the output of logic OR gate 142 and a mask signal 144 to produce overall SCSI bus insert/removal signal 59. Mask signal 144 is used to mask overall SCSI bus insert/removal signal 59 in the clock cycles immediately filing a system reset.

[0038] Mask signal 144 is generated using a flip-flop (FF) 81, a flip-flop 82, a flip-flop 83 and a logic NOT gate 144 connected as shown. A VCC power signal 101 is placed on a input of flip-flop 81. A system reset 99 signal clears to zero the values stored by FF 81, FF 82 and FF 83. State machine clock 73 is used to clock FF 81, FF 82 and FF 83.

[0039] FIG. 5 shows logic used to implement power fail combinatorial circuitry 55. A logic NOR gate 151, a logic AND gate 152, a logic NOR gate 153, a logic AND gate 154, a logic NOR gate 155 and a flip-flop 156 are connected as shown in order to generate (Not) SCSI bus reset signal 74 from hot swap SCSI bus reset signal 67, a power failure SCSI bus reset enable signal 68, a power supply A valid signal 69, a power supply B valid signal 70, a power supply A fault signal 71, a power supply B fault signal 72 and state machine clock 73.

[0040] The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.