Method to neutralize fixed charges in high K dielectric

[0002] The invention relates to the general field of integrated circuits with particular reference to FET gates and methods to operate them at lower voltages.

[0003] As part of the general development of integrated circuits there has been a steady drop in operating voltages. This has included a corresponding drop in the gate voltages used with Field Effect Transistor (FET) devices. FIG. 1 is a schematic illustration of an FET gate. Shown there is silicon substrate 11 on whose upper surface is a gate pedestal made up of silicon dioxide layer 15 and gate electrode 12. The above-mentioned reduction in gate voltage has meant that the thickness of the gate dielectric 15 has had to be similarly reduced. For traditional gate insulation made of silicon dioxide, this has meant gate dielectric thicknesses less about 15 Angstroms. When thicknesses get this low, dielectric leakage and premature breakdown become major problems.

[0004] To circumvent problems of this type, the FET art has begun using dielectrics having higher dielectric constants than silicon oxide. Since the charge density at the dielectric-silicon interface is proportional to the dielectric constant, thicker gate insulation can, in principle, then be used without otherwise affecting performance.

[0005] Among the dielectrics being considered as replacements for silicon oxide we include aluminum oxide and zirconium oxide. It has turned out that these materials, as normally deposited (e.g. by CVD (chemical vapor deposition)) result in devices with very poor high frequency performance whose cause has been identified as due to trapped charges in the dielectric.

[0006] The present invention describes how such charge can be permanently neutralized without introducing major changes into the overall device fabrication process. The principle on which the present invention is based is the observation that nitridation of a silicon oxide layer causes a shift of the flat band voltage to more negative values, as illustrated in FIG. 2 (where curve 21 is for NMOS devices and curve 22 is for PMOS devices). The flat band voltage is the minimum that is observed in a plot of capacitance as a function of voltage and the shift to more negative voltages is an indication that trapped positive charge has been introduced into the dielectric layer.

[0007] A routine search of the prior art was performed with the following references of interest being found:

[0008] In U.S. Pat. No. 6,251,761, Rodder et al. show a high K gate dielectric. A nitridation process is then used to convert the upper portion of the dielectric to a nitride. This is followed by an optional anneal. U.S. Pat. No. 3,978,577(Bhattacharyya et al.) shows an Aluminum oxide gate dielectric. U.S. Pat. No. 6,251,729(Montree et al.) shows an aluminum oxide inter-gate dielectric while U.S. Pat. No. 6,048,769(Chau) and U.S. Pat. No. 6,228,721(Yu) show related processes.

[0009] It has been an object of at least one embodiment of the present invention to provide an FET gate capable of operating at low voltages and having a minimum of trapped charge in the dielectric portion.

[0010] Another object of at least one embodiment of the present invention has been to provide a process for manufacturing said FET gate.

[0011] Still another object of at least one embodiment of the present invention has been that said process be fully compatible with current semiconductor device manufacturing practices.

[0012] These objects have been achieved by employing a high K dielectric such as aluminum or zirconium oxide. As deposited, this layer has a high density of trapped charge which is then neutralized by impregnating it with between about 5 and 10 atomic percent of nitrogen. Several methods for introducing the nitrogen are described. These include diffusion from an overlay of silicon nitride, diffusion from a gas source, remote plasma nitridation, and decoupled plasma nitridation.

[0013] FIG. 1 illustrates an FET gate structure of the prior art.

[0014] FIG. 2 is a plot of flat band voltage as a function of nitridation time.

[0015] FIG. 3 illustrates the layers needed for one embodiment of the present invention.

[0016] FIG. 4 shows an FET gate formed from the structure of FIG. 3.

[0017] FIG. 5 schematically illustrates a nitridation process.

[0018] FIG. 6 illustrates an FET gate according to the teachings of the present invention.

[0019] As discussed above, earlier work has indicated that a nitridation process leads to the introduction of positive charge (nitrogen ions) into the dielectric. Based on indications that the poor performance of high K dielectrics was due to the presence of trapped negative charge (oxygen ions) an improvement in said performance as a result of nitridation could reasonably be anticipated. The present invention discloses several processes for the effective implementation of such nitridation.

[0020] In its most general form, the present invention teaches that, for dielectrics such as aluminum oxide, zirconium oxide, and zirconium doped aluminum oxide (between about 60 and 80 atomic percent zirconium) the introduction of between about 5 and 10 atomic percent of nitrogen into such a dielectric will reduce the areal density of trapped charge therein to less than about 10¹¹to 10¹²c/cm².

[0021] We now describe several processes for the effective introduction of the nitrogen into these three (and other similar) dielectrics:

[0022] 1^stprocess: Beginning with silicon substrate 11, as seen in FIG. 3, high K dielectric layer 35 is first deposited to a thickness between about 50 and 100 Angstroms. This is followed by the deposition, to a thickness between about 5 and 20 Angstroms, of silicon nitride layer 32 onto high K dielectric layer 35. Next, the structure is subjected to a heat treatment whereby nitrogen ions from layer 32 diffuse into layer 35 where they serve to neutralize excess trapped negative charge. The heating process is performed at a temperature of between about 900 and 1,100° C. for between about 0.5 and 2 minutes in an atmosphere of nitrogen.

[0023] Once the heat treatment has been completed, a layer of gate electrode material 12 is deposited onto silicon nitride layer 32 and, as seen in FIG. 4, layers 35, 32, and 12 are patterned and etched to form a gate structure. Possible materials for the gate electrode include polysilicon, titanium nitride, and aluminum, with polysilicon being preferred.

[0024] 2^ndprocess: Beginning with silicon substrate 11, as seen in FIG. 5, high K dielectric layer 55 is first deposited to a thickness between about 50 and 100 Angstroms. This is followed by nitridation from the gas phase 53 (as opposed the solid phase used for the 1^stprocess). This results in impregnating the layer of high K dielectric with nitrogen to a concentration between about 5 and 10 atomic percent. Then a layer of gate electrode material 12 is deposited onto the nitrogen-impregnated layer 55, following which layers 12 and 55 are patterned and etched to form a gate structure as before.

[0025] Nitridation from the gas phase may be effected by any one of the following methods:

[0026] (i) By heating for between about 0.5 and 2 minutes at a temperature between about 900 and 1,000° C., optionally in an atmosphere of one or more of the following gases—ammonia, nitrous oxide, and nitric oxide.

[0027] (ii) By using remote plasma nitridation for between about 0.5 and 4 minutes at a temperature between about 400 and 1,000° C. in an atmosphere of one or more of the following gases—ammonia, nitrogen, nitrous oxide, and nitric oxide. Our preferred method of performing remote plasma nitridation has been at 550° C. for about 1 minute in nitrogen.

[0028] (iii) By using decoupled plasma nitridation for between about 0.1 and 2 minutes at a temperature between about 25 and 100° C. in an atmosphere of one or more of the following gases—ammonia, nitrogen, nitrous oxide, and nitric oxide. Our preferred method of performing decoupled plasma nitridation has been at 25° C. for about 30 seconds in nitrogen.