Self-driven synchronous rectification scheme

[0002] The present invention relates to DC-DC converters and, more particularly, to a self-driven, synchronous rectification scheme for a DC-DC power converter.

[0003] There is an ever-increasing demand in the power electronics market for low voltage and high current DC-DC converters. As output voltage is desired to be 3.3V or lower, even a state-of-the-art schottky diode with a forward voltage drop of 0.3V has an unacceptable amount of power loss.

[0004] Because of this, synchronous rectifier circuits are often used to improve the efficiency of DC-DC converters. Generally, there are two types of synchronous rectifier circuits, self-driven and externally driven. Since the self-driven mode is usually less complex, less costly and more reliable, it is preferred for use with most low voltage DC-DC converter applications.

[0005] FIG. 1(A) illustrates a conventional self-driven synchronous rectification, asymmetrical, zero voltage switching (ZVS) half-bridge (HB) topology which is only generally suitable for applications where the output voltage is in the range of from about 3.3V to 6V. Referring to FIG. 1B, the gate-drive voltages V_gs3and V_gs4of synchronous rectifiers (SRs) S₃and S₄, respectively, are as follows: (1) $\begin{array}{cc}{V}_{\mathrm{gs3}}=\frac{2N_s}{N_p}D{V}_{\mathrm{in}}=\frac{2}{N}D{V}_{\mathrm{in}}=\frac{V_o}{1-D}\left(t_0\le t\le t_1\right)& \left(1\right)\\ V_{\mathrm{gs4}}=\frac{2N_s}{N_p}\left(1-D\right)V_{in}=\frac{2\left(1-D\right)}{N}{V}_{in}=\frac{V_o}{D}\left(t_1\le t\le t_2\right)& \left(2\right)\end{array}$

[0006] wherein, V_inis the input voltage; V_ois the output voltage; D is the steady-state duty cycle; N_pis the number of primary winding turns of the transformer; N_sis the number of secondary turns of the transformer; and N is the turn ratio of the transformer. The turn ratio of the transformer TR is calculated by dividing the number of primary windings by the number of secondary windings (i.e. N=N_p/N_s).

[0007] FIG. 1(B) illustrates the switching waveform occurring in the converter illustrated in FIG. 1(A). As shown in FIG. 1(B), the gate-drive voltage V_gs4of S₄is always higher than the gate-drive voltage V_gs3of S₃if D is less than 50%. If we assume that the minimum steady-state duty cycle D at heavy load is 30%, then V_gs3is about 1.4V, and V_gs4is about 3.3V. Since most synchronous rectifiers (including logic level devices) only work well with the gate-drive voltage between about 4V and 20V, the circuit shown in FIG. 1(A) only works well when the output voltage V₀is between 2.9V to 6V. If the output voltage is below 2.9V, S₃would be under driven. If the output voltage were above 6V, then S₄would be over driven. In either case the synchronous rectifiers are easily rendered inoperative.

[0008] FIG. 2(A) shows a circuit diagram of an asymmetrical ZVS HB converter incorporating the self-driven synchronous rectifier circuit of the invention disclosed in U.S. patent application Ser. No. 09/932,398, filed Aug. 17, 2001, the entire disclosure of which is incorporated by reference herein. The self-driven synchronous rectifier circuit of FIG. 2(A) includes two power switches S₁and S₂; a transformer Tr having a primary winding N_p, a secondary winding N_sand an auxiliary winding N_a; two secondary synchronous rectifiers S₃and S₄; two diodes D₁and D₂; and two zener diodes ZD₁and ZD₂.

[0009] In the circuit of FIG. 2(A), when S₃conducts, the gate-drive voltage of S₄is clamped by D₁. Also, when S₄conducts, the gate-drive voltage of S₃is clamped by D₂. In other words, D₁and D₂prevent S₃and S₄from conducting at the same time. ZD₁and ZD₂operate to restrain the gate over voltage of S₃and S₄, respectively. Because of this circuit configuration, the self-driven synchronous rectifier circuit operates normally at various output voltages, such as low output voltages of 2.9V or lower and/or high output voltages above 6V.

[0010] FIG. 2(B) illustrates the switching waveform of the converter shown in FIG. 2(A). V_gs1and V_gs2represent the gate voltage waveforms of the two power switches S₁and S₂. V_pis the primary voltage waveform of transformer Tr. V_Nais the voltage waveform of the auxiliary winding. V_gs3and V_gs4represent the gate voltage waveforms of the two synchronous rectifiers S₃and S₄. V_gs3and V_gs4are calculated as follows: $\begin{array}{cc}{V}_{\mathrm{gs3}}=\frac{N_a}{N_p}D{V}_{in}\left(t_0\le t\le t_1\right)& \left(3\right)\\ V_{\mathrm{gs4}}=\frac{N_a}{N_p}\left(1-D\right)V_{in}\left(t_1\le t\le t_2\right)& \left(4\right)\end{array}$

[0011] wherein, D is the on-time of switch S1 in percent duty cycle; 1-D is the on-time of switch S₂in percent duty cycle; N_pis the number of primary winding turns of transformer Tr; N_ais the number of auxiliary winding turns of the transformer Tr; and V_inis the input voltage.

[0012] Comparing equations (3) and (4) above with equations (1) and (2), it can be seen, the gate voltage of self-driven synchronous rectifiers S₃and S₄may be adjusted by selecting the number of auxiliary winding turns N_aof transformer Tr. This selection of the auxiliary number of winding turns N_aensures a reasonable gate-drive voltage for the synchronous rectifiers S₃and S₄even when the output voltage is lower than 2.9V or higher than 6V.

[0013] Conventionally, the demand for self-driven synchronous rectifier is satisfied by the second scheme. But as logic integrated circuits have migrated to lower working voltages, it is expected that the next generation of integrated circuits will require power supplies with voltage in the 1-2V range. This will confront the second self-driven scheme with great challenges. As shown in FIG. 2(A), in practical application the circuit has a premise:

[0014] 2N_s≧N_a  (5)

[0015] A very low output voltage, namely 1.5V or less, would require a reduction in the number of turns of the winding N_s. However, a reduction in the number of turns of the winding N_awould not ensure a reasonable gate drive voltage for the synchronous rectifiers. On the other hand, if the number of turns of the winding N_aare made substantially greater than the number of turns of the winding N_s, i.e., if 2N_s≦N_athe winding N_awill short through the loop of N_a, D₁, S₄and ZD₁(or the loop of N_a, D₂, 2N_s, S₃and ZD₂). If this occurs, the self-driven circuit shown in FIG. 2(A) will not work.

[0016] This invention discloses a novel self-driven scheme that overcomes the above-mentioned drawbacks of the prior art self-driven schemes.

[0017] A self-driven synchronous rectifier circuit in accordance with one aspect of the present invention includes an input circuit including a transformer having a primary winding for receiving a voltage, a secondary winding and an auxiliary winding. First and second synchronous rectifiers connected to the secondary winding of the transformer and responsive to the signal across the auxiliary winding are provided for selectively and alternatively turning the synchronous rectifiers ON and OFF. A first clamping circuit is provided for clamping the second synchronous rectifier when the first synchronous rectifier is turned ON and a second clamping circuit is provided for clamping the first synchronous rectifier when the second synchronous rectifier is turned ON. The first clamping circuit includes a first switching device operative to disable the first clamping circuit when the second clamping circuit is operative, and the second clamping circuit includes a second switching device operative to disable the second clamping circuit when the first clamping circuit is operative.

[0018] In accordance with another aspect, the self-driven synchronous rectification circuit of the present invention includes two power switches S₁and S₂; a transformer Tr having a primary winding N_p, a secondary winding N_sand an auxiliary winding N_a; two secondary synchronous rectifiers S₃and S₄; two diodes D₁and D₂; and two zener diodes ZD₁and ZD₂; and two switching transistors Q₁and Q₂.

[0019] In the circuit of the present invention, when S₃conducts, the gate-drive voltage of S₄is clamped by D₁and Q₁. Also, when S₄conducts, the gate-drive voltage of S₃is clamped by D₂and Q₂. In other words, D₁, Q₁and Q₂prevent S₃and S₄from conducting at the same time. ZD₁and ZD₂restrain the gate over voltage of S₃and S₄, respectively.

[0020] Further, when the gate drive voltage of S₄is clamped by D₁and Q₁, Q₂disables D₂and when the gate drive voltage of S₃is clamped by D₂and Q₂, Q₁disables D₁.

[0021] Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings, wherein:

[0022] FIG. 1(A) is a circuit diagram of conventional self-driven synchronous rectification, asymmetrical ZVS HB converter;

[0023] FIG. 1(B) illustrates the switching waveform occurring in the converter illustrated in FIG. 1(A);

[0024] FIG. 2(A) is a circuit diagram of another asymmetrical ZVS HB converter which incorporates a self-driven synchronous rectifier circuit;

[0025] FIG. 2(B) illustrates the switching waveform occurring in the converter of FIG. 2(A);

[0026] FIG. 3 is a circuit diagram showing the self-driven synchronous rectifier circuit of the present invention applied to a forward converter;

[0027] FIG. 4 is a circuit diagram showing the self-driven synchronous rectifier circuit of the present invention applied to a full-bridge converter;

[0028] FIG. 5 illustrates an application of the novel self-driven synchronous rectification circuit to forward-flyback converter;

[0029] FIG. 6(A) illustrates an application of the novel self-driven synchronous rectifier circuit to symmetrical HB converter and FIG. 6(B) shows the gate drive waveforms.

[0030] FIG. 7 illustrates an application of the novel self-driven synchronous rectifier circuit to fall bridge converter.

[0031] FIG. 3 is a circuit diagram of an asymmetrical ZVS HB converter incorporating a novel self-driven synchronous rectifier circuit in accordance with the present invention. It adds two transistors, Q₁and Q₂, two capacitors, C₁and C₂, and two resistors, R₁and R₂, to the circuit of FIG. 2(A). The main waveforms of the converter are the same as shown in FIG. 2(B). The gate voltages of the two SRs, S₃and S₄, are also the same as equation (3) and (4). As with the circuit of FIG. 2(A), the number of auxiliary winding turns N_aof the transformer Tr ensure that the synchronous rectifiers S₃and S₄are supplied with an adequate gate-drive voltage. The selection of the number of auxiliary winding turns for use is determined according to the output voltage required. Such a determination will be evident to one of ordinary skill in the art, and will depend upon, for example, the wire size chosen and the inductance required of the winding.

[0032] The principle of operation is described as follows. During [t₀, t₁], S₂is ON and S₁is OFF, so Q₂is OFF and the loop of N_a, D₂, 2N_s, S₃and ZD₂is cut OFF. So while 2N_s≦N_a, the short circuiting of winding N_ais prevented. Since the primary voltage of transformer is DV_in, the voltage of auxiliary winding, namely the gate-drive voltage of S₃, is. When Q₁is ON, the gate-drive voltage of S₄is clamped to zero through D₁, Q₁and S₃. At time t₁, S₂is turned OFF and S₁is turned ON (FIG. 2B). The voltage of the primary winding of transformer N_preverses, so do the voltages on the secondary winding N, and auxiliary winding N_a. Then Q₁is turned OFF and the loop of N_a, D₁, 2N_s, S₄and ZD₁is cut OFF. During this interval, the gate-drive voltage of $S_4\mathrm{is}\frac{N_a}{N_p}\left(1-D\right)V_{in},$

[0033] and since Q₂is on, the gate-drive voltage of S₃is clamped to zero through D₂, Q₂and S₄. C₁and C₂is to accelerate the conduction of Q₁and Q₂and the function of ZD₁and ZD₂is to restrain the gate over voltage of S₃and S₄, respectively. D₁, Q₁and D₂, Q₂also prevent S₃and S₄from conducting at the same time. Additionally, Q₁functions to open the loop containing D₁during the periods when D₁is not acting to clamp the gate drive voltage of S₃, and Q₂functions to open the loop containing D₂during the periods when D₂is not acting to clamp the gate drive voltage of S₄. In this novel self-driven scheme, the output voltage has no relationship to the drive voltage of S₃and S₄.

[0034] The principles of the invention may be applied to a wide variety of DC-DC converters.

[0035] For example, FIGS. 4, 5, 6(A), 6(B) and 7 show the application of the principles of the invention to a fall-bridge converter, a forward-flyback converter, a symmetrical (HB) half-bridge converter and to another full-bridge converter.

[0036] In all cases, D₁, Q₁, D₂and Q₂prevent S₃and S₄from conducting at the same time, Q₁functions to open the loop containing D₁when D₁is D₂not acting to clamp S₄, and Q₂functions to open the loop containing D₂is not acting to clamp the gate drive voltage of S₄.

[0037] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.