LED display panel having a memory cell for each pixel element

[0002] (a) Field of the Invention

[0003] The present invention relates to a light emitting diode (LED) display panel having a memory cell for each pixel and, more particularly, to a LED display panel for use as a graphic display panel of a personal computer system.

[0004] (b) Description of the Related Art

[0005] A conventional graphic display panel of a personal computer system is generally provided with an associated VRAM. A graphic controller in the graphic display panel reads image data directly from the VRAM, converts the same to display data in a display format and writes the display data to each pixel element at a high speed, the image data being supplied from a processor of the computer system prior to the read operation by the graphic controller.

[0006] The graphic controller iteratively reads the image data from the VRAM to allow the display data in each pixel to coincide with a corresponding one of the latest image data supplied from the processor. This iterative read-out of the image data by the graphic controller reduces the work time of the controller for the graphic operation on the display panel, thereby reducing the speed of the graphics.

[0007] In addition, a sufficient standard is not provided for a flat display panel such as a LED display panel or a liquid crystal panel. The design for a graphic controller used for a display panel is generally changed depending on the design for the display panel, and accordingly, the cost of the graphic controller rises, which in turn raises the cost of the graphic display panel.

[0008] In view of the above, it is an object of the present invention to provide a LED display panel fabricated at a low cost, having a reduced occupied area and capable of operating at a higher speed.

[0009] The present invention provides a LED display panel comprising: a pixel array including a plurality of pixel elements arranged in a matrix along a row direction and a column direction, a plurality of word lines each disposed for a corresponding row of the pixel elements, and a bit line each disposed for a corresponding column of the pixel elements, each of the pixel elements having a LED and an associated memory cell,; an address port for receiving an address signal including a row address and a column address; a row address decoder for receiving the row address from the address port to specify one of the word lines; a column address decoder for receiving the column address from the address port to specify one of the bit lines; and a buffer for writing image data through the specified bit line to one of the memory cells corresponding to the specified word line, an output of the memory cell controlling the associated LED.

[0010] In accordance with the LED display panel of the present invention, a higher-speed operation, reduction in the occupied area and the fabrication cost can be obtained because a video RAM is not provided separately from the LED display panel and refreshment operation by a video controller of the LED display panel is not needed.

[0011] The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.

[0012] FIG. 1 is a block diagram of a LED display panel according to an embodiment of the present invention;

[0013] FIG. 2 is a block diagram of the arrangement of pixel elements of the LED display panel of FIG. 1; and

[0014] FIG. 3 is a block diagram of each pixel element shown in FIG. 2.

[0015] Referring to FIG. 1, a LED display panel according to an embodiment of the present invention has a display panel implemented by a pixel array 11 including an array of pixel elements for displaying image data on the display panel, a driver section 12 for controlling the array of the pixel elements, and an input/output buffer 13 for writing/reading data to/from the array of pixel elements.

[0016] Referring to FIG. 2, the LED display panel includes a plurality of (M×N) pixel elements 21 arranged in a matrix along a row (horizontal) direction and a column (vertical) direction, a plurality of (M) word lines 22 each corresponding to a row of the pixel elements 21, a plurality of (N) bit lines 23 each corresponding to a column of the pixel elements 21.

[0017] Back to FIG. 1, the driver section 12 includes an address port 14 for receiving address signals and address control signals, a row address decoder 15 for receiving row address signals of the address signals from the address port 14 to activate one of the word lines 22, a column decoder 16 for receiving the column address signals of the address signals to activate one of the bit lines 23.

[0018] The input/output buffer 13 receives a control signal for selecting a write mode or a read mode of the input buffer 13. The input/output buffer transmits an input image data from the processor to the pixel array 11 after conversion of the image data to display data in a display format during the write mode. The input/output buffer transmits display data from the pixel array 11 to the processor after conversion of the display data to image data in a computer format during the read mode. The read mode is generally used for storing the image data used for displaying the image in a data file.

[0019] Referring to FIG. 3, each pixel element 21 has a memory cell 31 for storing display data therein, a MOS transistor 32 having a gate controlled by an output line 33 of the memory cell 31, and a LED 34 controlled by the MOS transistor 32 for emitting light based on the data stored in the memory cell 31. Each write data is supplied through a bit line 23, which is specified by a column address, to the memory cell 31 corresponding to the specified bit line 23 and a word line 22 selected by the row address. The memory cell 31 may be a DRAM cell, SRAM cell, FRAM (ferroelectric RAM) cell or PROM cell.

[0020] If a DRAM cell is used as the memory cell 31, a page write operation may be used, similarly to an ordinary DRAM, by consecutively selecting bit lines 23 while selecting a single word line 22. If a SRAM cell is used as the memory cell 31, the LED display panel operates at a higher speed. If a FRAM cell is used as the memory cell 31, the display data is maintained on the LED display panel after the LED display panel is switched off. This allows the display data on the display panel to be stored in a data file outside the display panel. If a PROM cell is used as the memory cell 31, the LED display panel is preferably used for advertisement, wherein the data stored in the PROM is changed or modified for adapting the display data to a new version of the advertisement. If the LED display panel of the embodiment is to be used for displaying color images, different LEDs are used in combination for displaying three primary colors in each spot.

[0021] In operation of the LED display panel, a processor delivers an ordinary VRAM address signal to the address port 14, which transfers a row address to the row address decoder 15 and a column address to the column address decoder 16, thereby selecting a word line 22 and a bit line 23 corresponding to a specified pixel element 21. Input write data is delivered through the input/output buffer 13 and the selected bit line 23 to the memory cell 31 of the specified pixel element 21, which stores the write data therein. If the input write data is “1”, the memory cell 31 activates the MOS transistor 32 to allow the corresponding LED 34 to emit light. If the write data is “0”, the memory cell 31 inactivates the MOS transistor 32 to allow the corresponding LED 34 to turn off. A read operation from the LED display panel is conducted by specifying a pixel element 21, similarly to the write operation, and controlling the input/output buffer 13 to operate in a read mode by selecting a read mode.

[0022] In the above embodiment, refreshment of display data in each pixel element 21 is not necessary because each LED 34 is associated with a corresponding memory cell 31 storing display data in the pixel element 21. In addition, since the LED display panel has a VRAM function and a display function in each pixel element 21, the video controller and the address decoder in the conventional LED display panel can be unified. Further, the LED display panel of the present embodiment can operate at a higher speed.

[0023] Since the above embodiment is described only for examples, the present invention is not limited to the above embodiment and various modifications or alterations can be easily made therefrom by those skilled in the art without departing from the scope of the present invention.