US 6,563,223 B2Grant
Interconnection component for facilitating testing of packaged integrated circuits
Issue Date:2003-05-13
•26 Claims
•4 Drawing Sheets
Abstract
Apparatus and methods of testing and assembling fine ball grid array (FBGA) packages having circuit-bearing interconnect components. In one embodiment, a circuit-bearing interconnect component includes a substrate having a plurality of first conductive members disposed therethrough, a plurality of conductive traces coupled to the first conductive members and extending away from the first conductive members to a distal portion of the substrate, and a plurality of second conductive members disposed on the distal portion and coupled to the conductive traces. The substrate may be rigid or flexible. The first conducting members are located within an engagement area that is adapted to be engageable with a semiconductor component having a plurality of conductive bumps wherein each conductive bump engages one of the first conductive members. The first conductive members may include conductively-plated via or conductive pins. In an alternate embodiment, an apparatus further includes a semiconductor component having a plurality of conductive bumps disposed thereon. The circuit-bearing interconnect component may permit efficient, accurate, and reliable testing of the semiconductor component when the semiconductor component is attached to a semiconductor device, such as a printed circuit board.
Metadata
Assignee
- Micron Technology, Inc.
Inventor
- Stacy L. Freeman
Application Information
Application Number:US 10/013,090
Filing Date:2001-12-07
Priority Date:2000-08-22
Art Unit:7
Classifications
IPC:
H01L 2348
Field of Search:
257696257701257712257726257727257778
Patent Drawings (4 sheets)
Description
Cross-Reference to Related Application
[0002] This application is a divisional of pending U.S. patent application Ser. No. 09/644,196, filed Aug. 22, 2000.
Technical Field
[0003] The present invention relates to apparatus and methods of testing and assembling semiconductor packages, and more specifically, to testing and assembling fine ball grid array (FBGA) packages having circuit-bearing interconnect components.
Background of the Invention
[0004] As the trend toward decreasing the size of microelectronic packages continues, challenges associated with packaging and testing semiconductor devices are continuously encountered. Fine ball grid array (FBGA) semiconductor packages, for example, offer reduced package volumes and desirable performance characteristics. Testing of FBGA semiconductor packages, however, may be difficult, and the difficulty may increase as the size of the FBGA package decreases.
[0005] FIG. 1 is a cross-sectional elevational view of a typical FBGA package 10. The FBGA package 10 includes a bumped die 12 having a plurality of bond pads 14 formed thereon. An electrically conductive ball or bump 16 (typically composed of solder or a gold alloy) is formed on each bond pad 14, and is attached to associated contact pad 18 formed on a substrate 20, such as a test carrier or a printed circuit board. A conductive trace 22 is formed on the surface of the substrate 20 and is attached to one of the contact pads 18. The conductive traces 22 typically fan out from the bumped die 12 and may be connected to other electronic components or to test equipment. FBGA packages of the type shown in FIG. 1 are more fully described, for example, in U.S. Pat. Nos. 5,663,106 and 5,777,379 to Karavakis et al, and in U.S. Pat. No. 5,821,608 to DiStefano et al, which patents are incorporated herein by reference.
[0006] As mentioned above, for testing of the FBGA package 10, the substrate 20 may be a test carrier that temporarily engages the conductive bumps 16 of the bumped die 12. Suitable test carriers for testing unpackaged die 12 are described, for example, in U.S. Pat. No. 5,519,332 to Wood et al, incorporated herein by reference. Generally, such carriers are suitable for use with automated equipment and assembling procedures utilized in high-volume semiconductor manufacturing. Design considerations of such test carriers include the carrier's ability to transmit and receive electrical signals over a wide temperature range, thermal management characteristics, power and signal distribution characteristics, cost and reusability.
[0007] Testing of the bumped die 12 generally includes four levels of testing. A first or “standard probe” level includes the standard tests for gross functionality of die circuitry. A second or “speed probe” level includes testing the speed performance of the die for the fastest speed grades. A third or “burn-in die” level involves thermal cycling tests intended to drive contaminants into the active circuitry and to detect early failures. And a fourth or “known good die (KGD)” level includes testing to provide a reliability suitable for final products.
[0008] To ensure proper transmission of the test signals and output signals, the conductive bumps 16 may be temporarily connected with the contact pads 18 of the substrate 20 by reflowing the bumps, thereby soldering the bumps to the contact pads. After the testing is complete, the conductive bumps 16 may be reflowed to disconnect the bumps from the contact pads 18. After testing, the bumped die 12 is usually placed in operation by attaching the bumped die 12 to a printed circuit board or some another semiconductor component Again, the conductive bumps 16 are placed in the contact with the contact pads 18 of the printed circuit board, and are reflowed to bond the conductive bumps 16 to the contact pads 18, thereby attaching the bumped die 12 to the printed circuit board.
[0009] Connecting and disconnecting the conductive bumps 16 from the contact pads 18, however, involves time-consuming processes and may damage the conductive bumps 16 or the contact pads 18. Also, even though a bumped die 12 tests successfully using the test carrier, the final connection between the conductive bumps 16 of the bumped die 12 and the contact pads 18 of the printed circuit board may not always be good. Therefore, it is usually desirable to conduct additional testing of the bumped die 12 after it has been assembled with the printed circuit board in the final FBGA package 10.
[0010] Currently, conductive bumps 16 may range in height h (FIG. 1) from 0.75 mm down to 0.15 mm depending upon the die or semiconductor component. Typical “pitch” or spacing between adjacent conductive bumps 16 may range from 0.65 mm down to 0.13 mm (130 micron) or less. Furthermore, a semiconductor die or memory chip may have several hundred conductive bumps. Due to the extremely small sizes of the conductive bumps, the spacing between bumps, and the large number of bumps in typical FBGA packages, testing of such packages presents extreme challenges. For example, when the conductive bumps 16 of the bumped die 12 are attached to the contact pads 18 of the substrate 20, it is often not possible to measure a test signal at (or near) each of the conductive bumps 16 to determine the performance of a particular circuit or connection within the bumped die 12. This is especially true for those conductive bumps 16 which are not along the edges of the FBGA package 10. As the trend toward reducing the size of FBGA packages continues, the difficulties associated with testing such packages will continue to increase.
Summary of the Invention
[0011] The present invention is directed to apparatus and methods of testing and assembling fine ball grid array (FBGA) packages having circuit bearing interconnect components. In one aspect, a circuit-bearing interconnect component includes a substrate having a plurality of first conductive members disposed therethrough, a plurality of conductive traces coupled to the first conductive members and extending away from the first conductive members to a distal portion of the substrate, and a plurality of second conductive members disposed on the distal portion and coupled to the conductive traces. The substrate may be rigid or flexible. The first conducting members are located within an engagement area that is adapted to be engageable with a semiconductor component having a plurality of conductive bumps wherein each conductive bump engages one of the first conductive members. The first conductive members may include conductively-plated via or conductive pins. The circuit-bearing interconnect component may advantageously permit efficient, accurate, and reliable testing of the semiconductor component when the semiconductor component is attached to a semiconductor device, such as a printed circuit board.
[0012] In an alternate aspect, a semiconductor package includes a semiconductor component having a plurality of conductive bumps disposed thereon, a substrate including a plurality of first conductive members disposed within an engagement area, each first conductive member being attached to one of the conductive bumps and extending through a thickness of the substrate, the substrate further having at least one distal portion extending away from the engagement area, a plurality of conductive traces each having a first end electrically coupled with one of the first conductive members and a second end extending away from the one first conductive member and onto the at least one distal portion, and a plurality of second conductive members disposed on the at least one distal portion, each second conductive member being coupled to one of the conductive traces.
Brief Description of the Drawings
[0013] FIG. 1 is a side cross-sectional view of an FBGA package in accordance with the prior art.
[0014] FIG. 2 is a side cross-sectional view of a semiconductor package having a bumped die engaged with a circuit-bearing interconnect component in accordance with an embodiment of the invention.
[0015] FIG. 3 is an upper plan view of an embodiment of a circuit-bearing interconnect component of FIG. 2 having a flexible substrate.
[0016] FIG. 4 is an upper plan view of a semiconductor assembly having a plurality of semiconductor components attached to a printed circuit board and including a plurality of circuit-bearing interconnect components in accordance with an alternate embodiment of the invention.
[0017] FIG. 5 is a side cross-sectional view of the semiconductor assembly of FIG. 4.
[0018] FIG. 6 is a side cross-sectional view of a semiconductor package having a bumped die engaged with a pair of circuit-bearing interconnect components in accordance with an alternate embodiment of the invention.
[0019] FIG. 7 is an upper plan view of embodiments of circuit-bearing interconnect components of FIG. 5 having flexible substrates.
Detailed Description of the Invention
[0020] The present invention is generally directed to apparatus and methods of apparatus and methods of testing and assembling fine ball grid array (FBGA) packages having circuit-bearing interconnect components. Many specific details of certain embodiments of the invention are set forth in the following description and in FIGS. 2-7 to provide a thorough understanding of such embodiments. One skilled in the art will understand, however, that the present invention may have additional embodiments, or that the present invention may be practiced without several of the details described in the following description.
[0021] Unless otherwise stated, the construction and operation of various components of the embodiments described below may be of conventional design. Such components will be referred to using the same names and designation numbers as were used in the preceding background discussion. For the sake of brevity, such components will not be described in further detail herein, as these components are within the understanding of those skilled in the relevant art.
[0022] FIG. 2 is a side cross-sectional view of a semiconductor package 110 having a bumped die 12 engaged with a circuit-bearing interconnect component 100 in accordance with an embodiment of the invention. The circuit-bearing interconnect component 100 includes a substrate 102 having a first surface 120 and a second surface 121. As shown in the upper plan view of FIG. 3, the substrate 102 may be a flexible substrate 102 that is shapeable into a flattened position (described more fully below). A plurality of inner vias 104 are distributed throughout an inner area 105 of the substrate 102 and disposed therethrough. The inner vias 104 are positioned within the inner area 105 such that each inner via 104 is aligned with one of the conductive bumps 16 of the bumped die 12. A layer of conductive material 106 is formed within each of the inner via 104 and forms an inner contact ring 108 at each end of the respective inner via 104. As best shown in FIG. 2, the inner contact rings 108 may project slightly beyond, and may slightly overlap, the first and second surfaces 120, 121 of the substrate 102.
[0023] In the embodiment shown in FIGS. 2 and 3, the substrate 102 further includes a pair of outer areas 112 each having a plurality of outer vias 114 disposed therethrough. A conductive layer 116 is disposed within each of the outer vias 114, each conductive layer 116 forming an outer contact ring 118 at the end of the respective outer via 114. A plurality of conductive leads (or “traces”) 122 are formed on the first surface 120 of the substrate 102. Each lead 122 has an inner end coupled to one of the inner contact rings 108, and an outer end coupled to one of the outer contact rings 118.
[0024] The substrate 102 may be composed. of any suitable insulative material that prevents electrical shorts between the various conductive components (vias, leads, etc.). For example, the substrate 102 may be a rigid material (FIG. 2), such as a thermoplastic or fiberglass material. Alternately, the substrate 102 may be composed of a flexible material (FIGS. 2 and 3). Suitable flexible materials for the substrate 102 include, for example, a flexible dielectric elastomeric or polymeric material, such as a polyimide material. In other embodiments, the substrate 102 may have both rigid and flexible portions.
[0025] Furthermore, although the conductive leads 122 are shown as being disposed on the first surface 120 of the substrate 102, the leads 122 could be disposed on the second surface 121, on both surfaces 120, 121, or could be embedded within the interior of the substrate 102.
[0026] The embodiment of the circuit-bearing interconnect component 100 shown in FIG. 3 is configured for an FBGA package having 60 conductive bumps (four rows of 15 bumps each) at a pitch of approximately 0.50 mm. Of course, a variety of alternate embodiments of circuit-bearing interconnect components may be designed to accommodate a wide variety of different bump configurations, patterns, spacing, and may accommodate semiconductor components having virtually any number of conductive bumps.
[0027] During assembly, the conductive bumps 16 of the bumped die 12 may be aligned with respective inner vias 104 of the circuit-bearing interconnect component 100. The conductive bumps 16 may then be attached to respective inner contact rings 108 on the first surface 120 of the substrate 104, such as by reflowing the conductive bumps 16, to form an electrical contact between the bumped die 12 and the circuit-bearing interconnect component 100. Similarly, the contact pads 18 of the printed circuit board 20 may be aligned with respective inner vias 104 and attached to respective inner contact rings 108 on the second surface 121 using a variety of known attachment techniques, including soldering, thermal bonding, or using a layer of conductive adhesive (not shown). Thus, each inner via 104 is electrically coupled between its associated conductive bump 16 and contact pad 18, and each outer via 114 is electrically coupled with its associated inner via 104.
[0028] It should be understood that although the circuit-bearing interconnect component 100 is shown in FIG. 2 as extending beyond opposing sides of the bumped die 12, in alternate embodiments, the component may be modified to extend outwardly from beneath the bumped die 12 in a single direction (i.e. out a single side), in two directions (FIG. 2), in three directions or in four or more directions. For example, the circuit-bearing interconnect component 100 could be split into two separate components along a dividing line 140 (FIG. 3), with each resulting circuit-bearing interconnect component extending beyond the edge of the bumped die 12 in only a single direction. Therefore, depending on the spacing of the bumped die 12 on the printed circuit board 20 in relation to other components or structures, a variety of circuit-bearing interconnect components may be conceived to meet the particular needs of the application.
[0029] The circuit-bearing interconnect component 100 advantageously allows the bumped die 12 to be tested easily and efficiently after it has been assembled with the substrate 20. Because the substrate 102 may be shaped to position the outer vias 114 proximate the back side surface of the bumped die 12, the outer vias 114 are easily accessible. As shown in FIG. 2, both the rigid and flexible substrate embodiments may be shaped to bend through an approximately 180 degree angle so that the outer vias 114 are positioned over a backside surface 130 of the bumped die 12. A test probe 150 may then be easily inserted into any desired outer via 114 for transmitting test signals to, or receiving signals from, one of the conductive leads 122 on the substrate 102 coupled to a desired conductive bump 16. In this way, using one or more test probes 150, the internal circuitry of the bumped die 12 may be selectively tested after the bumped die 12 has been coupled with the substrate 20. Alternately, electrical signals may be transmitted to the bumped die 12 using the substrate 20, and appropriate output signals from the bumped die 12 to the substrate 20 may be monitored at the conductive bumps 16 using the circuit-bearing interconnect component 100.
[0030] Another advantage afforded by the circuit-bearing interconnect component 100 is that the test signals measured using the test probe 150 inserted into the outer via 114 may be of higher quality than test signals monitored using conventional methods. Because the conductive traces 122 are relatively short, the signals measured at the outer via 114 may be stronger and less subject to interference effects. The circuit-bearing interconnect component 100 may thereby provide more accurate and reliable test results compared with conventional test methods.
[0031] In alternate embodiments, the size and spacing of the outer vias 114 may be adjusted so that as the outer areas 112 are positioned over the back side surface of the bumped die 12, the pattern of outer vias 114 matches a standard pattern, such as the pattern of inner vias 104 (or conductive bumps) within the engagement area. This aspect may allow the outer vias 114 of the circuit-bearing interconnect component 100 to be engaged with standardized test apparatus having multiple test probes (not shown), thereby permitting the bumped die 12 to be subjected to rapid, multi-functional testing using conventional, mass-production test equipment.
[0032] FIG. 4 is an upper plan view of a semiconductor assembly 210 having a plurality of semiconductor components 212 attached to a printed circuit board 200 and including a plurality of circuit-bearing interconnect components 100 in accordance with an alternate embodiment of the invention. FIG. 5 is a side cross-sectional view of the semiconductor assembly 210 of FIG. 4. In this embodiment, each semiconductor component 212 is attached to the printed circuit board 200 in the manner described above with reference to FIGS. 2 and 3. The circuit-bearing interconnect components 100 may include a rigid substrate 102, or may have a flexible substrate of the type shown in FIG. 3 As best shown in FIG. 5, however, the outer areas 112 of each circuit-bearing interconnect component 100 are not shaped or bent around the associated bumped die 212A, but rather, the substrate 102 extends upwardly and outwardly from the bumped die 212A so that the outer areas 112 and the outer vias 114 are positioned at least partially over a backside surface of an adjacent bumped die 212B.
[0033] As shown in FIG. 4, circuit-bearing interconnect components 100 advantageously allow testing of semiconductor components 212 even when the semiconductor components 212 are tightly spaced on the printed circuit board 200. The substrate 102 may be shaped so that the outer via 114 may be positioned above the backside surface 130 of an adjacent semiconductor component 212 (FIG. 4), providing easy access for one or more test probes 150 to be inserted into the outer via 114. Therefore, the above-described advantages provided by the circuit-bearing interconnect components 100 may be realized in the semiconductor assembly 210 having a plurality of tightly spaced semiconductor components 212.
[0034] FIG. 6 is a side cross-sectional view of a semiconductor package 310 having a bumped die 12A engaging a pair of circuit-bearing interconnect components 300A, 300B in accordance with an alternate embodiment of the invention. As shown in the upper plan view of FIG. 7, each of the circuit bearing interconnect components 300A, 300B may include a flexible substrate 302 shapeable into a flattened position and having an aft portion 303 and a lateral portion 305. The substrate 302 may be flexible, as shown in FIGS. 6 or 7, or rigid, as shown in FIG. 6. A plurality of conductive pins (or posts) 304 are disposed within an engagement area 307 in a pattern corresponding to the pattern of at least some of the conductive bumps 16 on the bumped die 12A. The conductive pins 304 extend through each substrate 302 from a first outer surface 320 to a second surface 321. A pointed tip 309 is disposed at each end of the conductive pins 304.
[0035] A plurality of conductive leads 322 are disposed on the first outer surface 320 of each substrate 302. Each conductive lead 322 is electrically coupled to a conductive pin 304 and extends outwardly from the engagement area 307. Some of the conductive leads 322 extend across the aft portion 303, while other conductive leads extend across the lateral portion 305. A plurality of test pads 314 are formed along outer (peripheral) edges 315 of the substrate 302. Each test pad 314 is coupled to one of the conductive leads 322.
[0036] During assembly, the conductive bumps 16 of the bumped die 12A may be aligned with the conductive pins 304 of each respective circuit-bearing interconnect component 300A, 300B. Also, the contact pads 18 of a printed circuit board 20A may be aligned with the conductive pins 304. Using a compressive force, the pointed tips 309 of the conductive pins 304 that protrude above the first and second surfaces 320, 321 may be driven into the surfaces of the conductive bumps 16 and the contact pads 18, respectively, thereby piercing a layer of oxide that may reside on the surfaces of these components and improving the electrical connection therebetween. Alternately, the pointed tips 309 may be eliminated, and the conductive bumps 16 and the contact pads 18 may be attached to the conductive pins 304 using other attachment techniques, such as by soldering, thermal bonding, or using conductive adhesive compounds. Following assembly, each conductive bump 16 of the bumped die 12A is electrically coupled with the corresponding contact pad 18 of the printed circuit board 20A by one of the conductive pins 304, and each conductive pin 304 is electrically coupled with its associated test pad 314 by one of the conductive leads 322.
[0037] The circuit-bearing interconnect components 300A, 300B having the plurality of test pads 314 distributed along lateral edges 315 of the substrate 302 further improves the ease, accuracy, and reliability of the testing process. Because the test pads 314 are distributed on the lateral edges 315, the lateral edges 315 may be inserted into a suitable socket or receptacle (not shown) for sending and receiving signals to and from the conductive bumps 16. Testing of the semiconductor package 310 may be done more rapidly than alternate methods involving applying a test probe to each test pad 314 (or outer via 114) individually. Furthermore, accuracy of the testing may be increased because the possibility of contacting the test probe with the wrong test pad 314 (or outer via 114) is reduced or eliminated. As described above, the circuit-bearing interconnect components 300A, 300B allow the bumped die 12A to be tested easily and efficiently after it has been assembled with the printed circuit board 20A.
[0038] Another advantage is that the circuit-bearing interconnect components 300A, 300B may be used to test bumped die 12A in a variety of tight spaces and packaging configurations. Because the aft portion 303 of the substrate 302 includes some of the test pads 314 while the lateral portion 305 includes the remainder of the test pads 314, the circuit-bearing interconnect components 300A, 300B provide a useful alternative to embodiments having all of the conductive leads extending away from only one side of the semiconductor component being tested. In other words, if the position of the semiconductor component within a particular package does not permit all of the test leads of the circuit-bearing component to extend from one side of the component to permit testing, alternate embodiments of circuit-bearing interconnect components having conductive leads extending from two or more sides of the component to be tested may be used.
[0039] In an alternate embodiment, the circuit-bearing interconnect component 300B includes a pair of frangible sections 400 (FIGS. 6 & 7). One of the frangible sections 400 is disposed within the aft portion 303 of the substrate 302, and the other frangible section 400 is disposed within the lateral portion 305 of the substrate 302. The frangible sections 400 are weakened, breakable sections across the aft and lateral portions 303, 305, including the conductive leads 322, that may be broken, torn apart, or otherwise parted without damaging the other components of the circuit-bearing interconnect component 300B, the bumped die 12A, or printed circuit board 20A.
[0040] It should be understood that the frangible sections 400 may be positioned at a variety of locations along the aft and lateral portions 303, 305. Also, it is not necessary that both the aft and lateral portions 303, 305 include a frangible section 400, but rather, may be included in only a single distal portion of the substrate. Of course, the frangible sections 400 may be included in either rigid or flexible substrates.
[0041] One advantage of the frangible sections 400 is that after installation and testing of the bumped die 12A using the circuit-bearing interconnect component 300B, the aft and lateral portions 303, 305 of the substrate 302 may be removed from the semiconductor package 310. This may advantageously allow the resulting package to take up less space than the semiconductor package 310 having the aft and lateral portions 303, 305 (FIGS. 2 & 6).
[0042] The detailed descriptions of the above embodiments are not exhaustive descriptions of all embodiments contemplated by the inventors to be within the scope of the invention. Indeed, persons skilled in the art will recognize that certain elements of the above-described embodiments may variously be combined or eliminated to create further embodiments, and such further embodiments fall within the scope and teachings of the invention. It will also be apparent to those of ordinary skill in the art that the above-described embodiments may be combined in whole or in part to create additional embodiments within the scope and teachings of the invention.
[0043] Thus, although specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. The teachings provided herein can be applied to other apparatus and methods of apparatus and methods of testing and assembling FBGA packages having circuit-bearing interconnect components, and not just to the embodiments described above and shown in the accompanying figures. Accordingly, the scope of the invention should be determined from the following claims.
Claims
What is claimed is:
1. A circuit-bearing interconnect component adapted to be engageable with a semiconductor component having a plurality of conductive bumps, comprising:
an electrically insulating substrate including a plurality of first conductive members disposed within a first engagement area adapted to align with and engage the plurality of conductive bumps, each first conductive member extending through a thickness of the substrate, the substrate further having at least one distal portion extending away from the engagement area;
a plurality of conductive traces each having a first end electrically coupled with one of the first conductive members and a second end extending away from the one first conductive member to the at least one distal portion; and
a plurality of second conductive members disposed on the at least one distal portion, each second conductive member being coupled to one of the conductive traces, at least some of the second conductive members being accessible when the semiconductor component is engaged with the first engagement area.
2. The circuit-bearing interconnect component according to claim 1 wherein the electrically insulating substrate comprises a flexible substrate.
3. The circuit-bearing interconnect component according to claim 2 wherein the flexible substrate is bendable such that the second conductive members are positionable adjacent a second engagement area adapted to be proximate to a backside surface of the semiconductor component.
4. The circuit-bearing interconnect component according to claim 1 wherein the electrically insulating substrate comprises a rigid substrate.
5. The circuit-bearing interconnect component according to claim 4 wherein the rigid substrate is formed such that the second conductive members are positioned adjacent a second engagement area adapted to be proximate to a backside surface of the semiconductor component.
6. The circuit-bearing interconnect component according to claim 1 wherein the substrate includes a frangible portion.
7. The circuit-bearing interconnect component according to claim 1 wherein the plurality of first conductive members comprise a plurality of vias disposed through the substrate, each via including a layer of conductive material.
8. The circuit-bearing interconnect component according to claim 1 wherein the plurality of first conductive members comprise a plurality of conductive pins disposed through the substrate.
9. The circuit-bearing interconnect component according to claim 1 wherein the plurality of first conductive members comprise a plurality of conductive pins disposed through the substrate, each conductive pin having pointed ends.
10. The circuit-bearing interconnect component according to claim 1 wherein the plurality of second conductive members comprise a plurality of vias disposed through the distal portion, each via including a layer of conductive material.
11. The circuit-bearing interconnect component according to claim 1 wherein the plurality of second conductive members comprise a plurality of test pads disposed on the distal portion proximate an outer edge thereof.
12. The circuit-bearing interconnect component according to claim 1 wherein the substrate includes a single distal portion extending away from the first engagement area.
13. The circuit-bearing interconnect component according to claim 1 wherein the at least one distal portion comprises a first distal portion and wherein the substrate further includes a second distal portion extending away from the first engagement area.
14. The circuit-bearing interconnect component according to claim 1 wherein the engagement area comprises a rectangular area and wherein the substrate has first and second distal portions that extend beyond opposing sides of the rectangular area.
15. A semiconductor package, comprising:
a semiconductor component having a plurality of conductive bumps disposed thereon;
an electrically insulating substrate including a plurality of first conductive members disposed within a first engagement area, each first conductive member being attached to one of the conductive bumps and extending through a thickness of the substrate, the substrate further having at least one distal portion extending away from the engagement area;
a plurality of conductive traces each having a first end electrically coupled with one of the first conductive members and a second end extending away from the one first conductive member to the at least one distal portion; and
a plurality of second conductive members disposed on the at least one distal portion, each second conductive member being coupled to one of the conductive traces, at least some of the second conductive members being accessible when the semiconductor component is engaged with the first engagement area.
16. The semiconductor package according to claim 15 wherein the electrically insulating substrate comprises a flexible substrate.
17. The semiconductor package according to claim 16 wherein the flexible substrate is bendable such that the second conductive members are positionable adjacent a second engagement area adapted to be proximate to a backside surface of the semiconductor component.
18. The semiconductor package according to claim 15 wherein the electrically insulating substrate comprises a rigid substrate formed such that the second conductive members are positioned adjacent a second engagement area adapted to be proximate to a backside surface of the semiconductor component.
19. The semiconductor package according to claim 15 wherein the substrate includes a frangible portion.
20. The semiconductor package according to claim 15 wherein the plurality of first conductive members comprise a plurality of vias disposed through the substrate, each via including a layer of conductive material.
21. The semiconductor package according to claim 15 wherein the plurality of first conductive members comprise a plurality of conductive pins disposed through the substrate.
22. The semiconductor package according to claim 15 wherein the plurality of first conductive members comprise a plurality of conductive pins disposed through the substrate, each conductive pin having pointed ends.
23. The semiconductor package according to claim 15 wherein the plurality of second conductive members comprise a plurality of vias disposed through the distal portion, each via including a layer of conductive material.
24. The semiconductor package according to claim 15 wherein the plurality of second conductive members comprise a plurality of test pads disposed on the distal portion proximate an outer edge thereof.
25. The semiconductor package according to claim 15 wherein the at least one distal portion comprises a first distal portion and wherein the substrate further includes a second distal portion extending away from the first engagement area.
26. The semiconductor package according to claim 15 wherein the conductive bumps are attached to a first end of each corresponding first conductive member, further comprising a second semiconductor component having a plurality of contact pads disposed thereon, each contact pad being attached to a second end of the corresponding first conductive member.
Patent Citations (20)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US5519332(A) | 1996-05-01 | Wood et al. | Applicant |
| US5629838(A) | 1997-05-01 | Knight et al. | Applicant |
| US5663106(A) | 1997-09-01 | Karavakis et al. | Applicant |
| US5734560(A) | 1998-03-01 | Kamperman et al. | Applicant |
| US5777379(A) | 1998-07-01 | Karavakis et al. | Applicant |
| US5821608(A) | 1998-10-01 | DiStefano et al. | Applicant |
| US5861666(A) | 1999-01-01 | Bellaar | Applicant |
| US5895970(A) | 1999-04-01 | Miyoshi | Examiner |
| US5971253(A) | 1999-10-01 | Gilleo et al. | Applicant |
| US6022759(A) | 2000-02-01 | Seki et al. | Applicant |
| US6048753(A) | 2000-04-01 | Farnworth et al. | Applicant |
| US6165817(A) | 2000-12-01 | Akram et al. | Applicant |
| US6166556(A) | 2000-12-01 | Wang et al. | Applicant |
| US6169329(B1) | 2001-01-01 | Farnworth et al. | Applicant |
| US6239485(B1) | 2001-05-01 | Peters et al. | Applicant |
| US6278181(B1) | 2001-08-01 | Maley | Examiner |
| US6291272(B1) | 2001-09-01 | Giri et al. | Applicant |
| US6329708(B1) | 2001-12-01 | Komiyama | Applicant |
| US6369331(B1) | 2002-04-01 | Kusano et al. | Applicant |
| US6452807(B1) | 2002-09-01 | Barrett | Applicant |