Image-rejection I/Q demodulators

[0002] This application, by this reference, hereby incorporates the following U.S. patent applications, in their entirety, all filed on Jun. 12, 2000:

[0003] “Receiver Architecture Employing Low Intermediate Frequency And Complex Filtering”, to Albert Liu, Ser. No. 09/592,016;

[0004] “Wireless Data Communications Using FIFO For Synchronization Memory”, to Sherman Lee, Vivian Y. Chou, and John H. Lin, Ser. No. 09/593,583;

[0005] “Context Switch Architecture And System”, to Sherman Lee, Vivian Y. Chou, and John H. Lin, Ser. No. 09/592,009; and

[0006] “Dynamic Field Patchable Microarchitecture”, to Sherman Lee, Vivian Y. Chou, and John H. Lin, Ser. No. 09/672,064.

[0007] The invention relates to digital communications systems and, more particularly, to a technique for the reduction in the image response characteristics of an integrated circuit receiver that incorporates I/Q demodulation.

[0008] I/Q (In-phase/Quadrature) modulators and demodulators are widely used in digital communications systems. I/Q demodulators are abundantly discussed in the technical literature. See, for example, Behzad Razavi, RF Microelectronics,Prentice Hall (1998) and John G. Proakis, Digital Communications,McGraw-Hill (1995). There exists also patent art related to the technology of I/Q modulation and demodulation: U.S. Pat. No. 5,974,306, entitled “Time-Share I/Q Mixer System With Distribution Switch Feeding In-Phase and Quadrature Polarity Inverters” to Hornak, et al.; U.S. Pat. No. 5,469,126, entitled “I/Q Modulator and I/Q Demodulator” to Murtojarvi.

[0009] Examples of system applications that incorporate and standardize I/Q modulation and demodulation include the GSM (Global System for Mobile Communications), IS-136 (TDMA), IS-95 (CDMA), and IEEE 802.11 (wireless LAN). I/Q modulation and demodulation have also been proposed for use in the Bluetooth wireless communication systems.

[0010] Bluetooth is a low-power radio technology being developed with a view to substituting a radio link for wire and cable that now connect electronic devices, such as personal computers, printers and a wide variety of handheld devices, including palm-top computers, and mobile telephones. The development of Bluetooth began in early 1998 and has been promoted by a number of telecommunications and computer industry leaders. The Bluetooth specification is intended to be open and royalty-free and is available to potential participants as a guide to the development of compatible products.

[0011] The Bluetooth system operates in the 2.4 GHz ISM (Industrial, Scientific, Medical) band, and devices equipped with Bluetooth technology are expected to be capable of exchanging data at speeds up to 720 Kbs at ranges up to 10 meters. This performance is achieved using a transmission power of 1 mw and the incorporation of frequency hopping to avoid interference. In the event that a Bluetooth-compatible receiving device detects a transmitting device within 10 meters, the receiving device will automatically modify its transmitting power to accommodate the range. The receiving device is also required to operate in a low-power mode as traffic volume becomes low, or ceases altogether.

[0012] Bluetooth devices are capable of interlinking to form piconets, each of which may have up to 256 units, with one master and seven slaves active while others idle in a standby mode. Piconets can overlap, and slaves can be shared. In addition, a form of scatternet may be established with overlapping piconets, thereby allowing data to migrate across the networks.

[0013] An example of a Bluetooth-compliant digital communications receiver that incorporates an I/Q demodulator is depicted in FIG. 1. As may be seen from FIG. 1, the receiver includes an antenna 10 that intercepts a transmitted RF signal. The signal received by antenna 10 is filtered in a RF bandpass filter (BPF) 11. BPF 11 may be fixed-tuned or tunable and will have a nominal center frequency at the anticipated RF carrier frequency. The bandwidth of BPF will be designed as appropriate to the overall receiver system design requirements and constraints. One salient purpose of BPF 11 is to effect rejection of out-of-band RF signals, that is, rejection of signals at frequencies other than the frequency of the desired RF carrier. Front-end selectivity is an important factor in minimizing the receiver's susceptibility to intermodulation and cross-modulation interference. In addition, and contextually more relevant, BPF 11 selectivity contributes to the image-rejection characteristics of the receiver.

[0014] In general, image rejection refers to the ability of the receiver to reject responses resulting from RF signals at a frequency offset from the desired RF carrier frequency by an amount equal to twice the intermediate frequency (IF) of a dual-conversion receiver. For example, if the desired RF signal is at 100 MHz, and the receiver IF is 10.7 MHz, than the receiver local oscillator (LO) will be tuned to 89.3 MHz. However, as is well known to those skilled in the art, the receiver will also exhibit a response to undesired RF signals at frequency 10.7 MHz below the LO frequency, that is 78.6 MHz. The receiver's response to the 78.6 MHz signal is referred to as the image response, because the image signal resides at a frequency opposite the LO frequency as the desired RF carrier, and offset from the LO frequency by the magnitude of the IF.

[0015] Referring still to FIG. 1, the output of BPF 11 is coupled to the input of a low-noise amplifier (LNA) 12. LNA 12 is designed to raise the level of the input RF signal sufficiently to effectively drive the receiver's mixer circuitry. In addition, LNA 12 largely determines the receiver's noise figure.

[0016] The output of LNA 12 is coupled to the receiver's mixer/demodulator functional block. The mixer/demodulator includes a quadrature demodulator, including I demodulator 13 and Q demodulator 14. As is commonplace in contemporary receiver design, the receiver incorporates a digital, frequency-synthesized LO function, performed by a voltage-controlled oscillator (VCO) 15, driven by a phase-locked loop (PLL) 16. For a comprehensive exposition of digital frequency-synthesis techniques, see William F. Egan, Frequency Synthesis by Phase Lock,John Wiley & Sons, Inc., (2000). The LO signal is coupled to an input of phase-shifter 17. In a manner well understood by artisans, phase-shifter 17 delivers an in-phase version of the LO, LO_I signal 13a,to I demodulator 13 and a quadrature (90° phase shifted) version of the LO, LO_Q signal 14a,to Q demodulator 14. The respective demodulated outputs of demodulators 13 and 14 constitute, respectively, the demodulated I and Q signals.

[0017] An ideal I/Q demodulation receiver, as described above, is theoretically capable of infinite image rejection. However, the theoretical assumption is predicated on perfectly matched I and Q channels. Because state-of-the art semiconductor device design and fabrication does not admit of perfect matching between devices, even devices on the same die, some degree of mismatch between the I and Q channels is inevitable. In fact, the mismatch between devices on a semiconductor wafer is known to be dependent on the physical size of the devices. This dependency may be predicted by the following relationships that quantify the standard deviation in threshold voltage σ_Vt, and β,σ_β, for a MOS device: ${\sigma }_{\mathrm{Vt}}=\frac{30\left(\text{millivolt}-\text{micrometer}\right)}{\sqrt{W\times L}}\text{and}$ ${\sigma }_{\beta }=\frac{0.09\left(\text{micrometer}\right)}{\sqrt{W\times L}},\text{where}$

[0018] W×L is total area occupied by the device on the semiconductor die.

[0019] As is immediately apparent from the above, deviations in critical CMOS device parameters vary inversely with to the area occupied by the device. Because lower frequencies of operation permit larger device geometries, mismatch in a receiver IF section tends to be ameliorated as the IF is reduced.

[0020] It has been empirically determined that contemporary semiconductor fabrication processes result in I channel and Q channel matching that limits image rejection to approximately 30 to 35 db. In systems implemented with CMOS technology, virtually mandatory when power consumption is a paramount design consideration, not even this level of performance is realizable. This detriment derives from the fact that CMOS devices tend to demonstrate less favorable matching characteristics. Given that a 35 db image rejection specification is considered marginal for most digital communication receiver applications, the problems confronted in a CMOS-based design are glaringly apparent.

[0021] Accordingly, what is desired is a solution that enhances the image-rejection performance of digital communication receivers that are implemented with integrated circuit technology. Although the solution is not limited in applicability of designs implemented in CMOS technology, the invention is particularly advantageous in that context.

[0022] The above and other objects, advantages and capabilities are achieved in one aspect of the invention by a communications receiver that comprises a carrier signal source; a first demodulator having a first input coupled to an output of the carrier signal source; a second demodulator having a first input coupled to an out put of the carrier signal source; a local oscillator (LO) signal source; a quadrature phase shifter having an LO input coupled to the LO signal source, an in-phase (I) output coupled to a second input of the first demodulator, and quadrature (Q) output coupled to a second input of the second demodulator; and an image/signal ratio detector having a first input coupled to an output of the first demodulator, a second input coupled to an output of the second demodulator, and an output coupled to the quadrature phase shifter for adjusting the I output of phase shifter and the Q output of phase shifter so as to adjust the image response of the communications receiver.

[0023] Another aspect of the invention is apparent in a feedback loop for controlling the image response of a communications receiver that, typically, includes a carrier signal source, a local oscillator (LO) signal source, an in-phase (I) demodulator and a quadrature (Q) demodulator. The feedback loop comprises a quadrature LO generator for providing an LO_I signal to the I demodulator and an LO_Q signal to the Q demodulator, wherein the LO_I and LO_Q signals are amplitude-controlled and phase-controlled versions of the LO signal provided by the LO signal source. The feedback loop also comprises an image/signal ratio (I/S) detector for detecting the amplitude difference and the phase difference between the respective outputs of the I demodulator and the Q demodulator and for adjusting the respective relative amplitudes and phases of the LO_I and LO_Q signals in response to the detected amplitude difference and phase difference.

[0024] The invention may also be practiced as a method for adjusting the image response of a communications receiver that includes in-phase (I) and quadrature (Q) demodulators. The method comprises the acts: synthesizing an LO signal; deriving an LO_I signal from the LO signal; deriving an LO_Q signal from the LO signal; detecting an amplitude control signal that results from an amplitude mismatch between an I channel and a Q channel of the communications receiver; detecting a phase control signal that results from a phase mismatch between the I channel and the Q channel; adjusting the relative amplitudes of the LO_I and the LO_Q signals in response to the amplitude control signal; and adjusting the relative phases of the LO_I and the LO_Q signals in response to the phase control signal, wherein the adjustments to the relative respective amplitudes and the relative respective phases of the LO_I and LO₁₃Q signals operate to compensate for mismatch between the I channel and the Q channel in a manner that reduces the image response of the receiver.

[0025] The invention is additionally embodied in a mixer for a communications receiver. The mixer comprises an I demodulation channel including an I demodulator; a Q demodulation channel including a Q demodulator; a quadrature LO generator for coupling to a source of LO signals, the quadrature LO generator for developing an LO₁₃I signal coupled to the I demodulator and an LO_Q signal coupled to the Q demodulator, wherein the LO_I and LO₁₃Q signals are adjusted in amplitude and phase in response to mismatch between the I and Q channels, wherein the quadrature LO generator comprises: a polyphase filter having an input for coupling to the source of LO signals, and having an LO_I output and an LO_Q output; an LO_I buffer having an LO_I input coupled to the LO_I output of the polyphase filter and having an LO_I output coupled to the I demodulator; and an LO_Q buffer having an LO_Q input coupled to the LO_Q output of the polyphase filter and having an LO_Q output coupled to the Q demodulator; and an I/S detector for synthesizing an amplitude control signal and a phase control signal in response to mismatch between the I and the Q channels, the I/S detector having (i) inputs coupled to outputs of the I and the Q demodulators, (ii) an output for applying an amplitude control signal to an amplitude control input of the quadrature LO generator, and (iii) an output for applying an phase control signal to a phase control input of the quadrature LO generator, the I/S detector comprising: a rotator having inputs coupled to the outputs of the I and the Q demodulators and having first and second I and Q outputs; an amplitude meter coupled to the first I and Q output of the rotator for developing the amplitude control signal; and a phase meter coupled to the second I and Q output of the rotator for developing the phase control signal.

[0026] The invention may also be perceived as a method for calibrating a communications receiver that includes (i) an I demodulation channel including an I demodulator, (ii) a Q demodulator channel including a Q demodulator, and (iii) a quadrature LO generator having an input coupled to a source of LO signals and that provides an LO_I signal to the I demodulator and an LO_Q signal to the Q demodulator. The calibration method comprises the acts: (a) during an interval during which no information is received by the communications receiver, applying an RF test tone to the inputs of the I demodulation channel and the Q demodulation channel; (b) time multiplexing a first LO signal and a second LO signal to the input of the quadrature LO generator so as to simulate the appearance of both a desired RF signal and an image signal at the input of the communications receiver; (c) detecting a signal, V_S,IM, resulting from the response of the communications receiver to the simulated image signal; (d) extracting from V_S,IMan amplitude control signal is proportional to the amplitude mismatch between the I and the Q channels and a phase control signal that is proportional to the phase mismatch between the I and the Q channels; and (e) adjusting the relative amplitudes of the LO_I and the LO_Q signals in response to the amplitude control signal and adjusting the relative phases of the LO_I and the LO_Q signals in response to the phase control signal wherein the adjustments to the relative respective amplitudes and the relative respective phases of the LO_I and LO_Q signals operate to reduce the image response of the receiver.

[0027] The subject invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art, with reference to the following Drawings, wherein:

[0028] FIG. 1 is a system block diagram of a conventional digital communications receiver predicated on I/Q demodulation.

[0029] FIG. 2 is a system block diagram of an I/Q demodulation receiver that incorporates aspects of the subject invention, including a quadrature LO generator, with amplitude and phase control provided by an I/S detector.

[0030] FIG. 3 is a block diagram of an Image/Signal Ration (I/S) Detector used in connection with the subject invention.

[0031] FIG. 4A is a block diagram of the quadrature LO generator depicted in FIG. 2, including a polyphase filter and gain-controlled LO_I and LO₁₃Q buffers.

[0032] FIG. 4B is a generalized circuit diagram of the polyphase filter.

[0033] FIG. 4C is a simplified circuit diagram illustrating an example of the manner in which the polyphase filter may be tuned (phase-controlled) with a voltage-variable capacitor.

[0034] FIG. 4D is a circuit diagram of the buffers depicted in FIG. 4A.

[0035] For a thorough understanding of the subject invention, reference is made to the following Description, including the appended Claims, in conjunction with the above described Drawings.

[0036] Referring now to FIG. 2, the subject receiver with image-rejection digital I/Q demodulator is seen to be in many respects similar to the digital I/Q demodulation receiver depicted in FIG. 1. A salient departure is the substitution of the phase shifter 17 in FIG. 1 with the quadrature LO generator 21 in the receiver of FIG. 2. In addition, and in a manner to be more completely described below, the operation of quadrature LO generator 21 is controlled by an image/signal ratio (I/S) detector 22 that applies amplitude control and phase control signals to quadrature LO generator 21 in a manner that adjusts the LO_I and LO_Q signals to the I demodulator 13 and to the Q demodulator 14 respectively, so as to reduce the image response of the receiver.

[0037] With continued reference to FIG. 2, operation of subject invention may be understood to proceed as follows. The demodulated I output from I demodulator 13 is fed into one input of I/S detector 22, and the demodulated Q output of Q demodulator 14 is fed into a second input of the I/S detector. A detailed depiction of the I/S detector is provided in FIG. 3. I/S detector 22 is seen in FIG. 3 to include a pair of A/D converters 211 and 212, respectively, at the input of the I/S detector. In practice, A/D converters 211 and 212 may both be 10-bit converters. However, A/D conversion at the input of the I/S detector is required only in systems that deliver analog outputs at demodulators 13 and 14. In systems that provide digital signals at the demodulator outputs, A/D conversion at the I/S detector input may be eliminated. The outputs of the A/D converters are coupled to the respective I and Q inputs of 90° rotator 213. Rotator 213 imparts an additional 90° phase shift between the I and the Q signals, so that at the output of the rotator, the I and Q signals are 180° out of phase. Rotator 213 provides a first pair of I and Q signals from terminals 213aand 213bto the inputs of amplitude meter 214 and provides a second pair of I and Q output signals from terminals 213cand 213dto the inputs of phase meter 215. The amplitude control output 22cof the I/S detector is applied to an amplitude control input of the quadrature LO generator 21. The phase control output 22dof the I/S detector is applied to the phase control input of quadrature LO generator. As may be anticipated, the amplitude control signal at output 22cis proportional to the relative amplitudes of the demodulated I and Q signals. Similarly, the phase control signal at output 22dis proportional to the phase difference between the demodulated I and Q signals. The amplitude control signal and the phase control signal are measures of the mismatch between the I and Q channels. The manner in which the control signals are synthesized may be acquired with continued reference to FIG. 3.

[0038] Simply, operation of I/S detector 22 is predicated on the application of a test tone, at the anticipated RF carrier frequency, to the input of the mixer of the digital receiver, that is, at the node occupied in common by the inputs of the I and Q demodulators. The LO frequency is adjusted first to run at a frequency (RF−IF), and then at a frequency (RF+IF). Consequently, IF signals are generated in a manner that is generally equivalent to the appearance of input signals at both the anticipated RF carrier frequency, and at an image frequency. Viewed alternatively, the variation in LO frequency simulates the appearance of an image signal at the input of the receiver.

[0039] The two IF signals, due to desired RF carrier and to image signal, respectively, are time duplexed and appropriately processed into a first signal that is proportional to the amplitude difference between LO_I and LO_Q, and into a second signal that is proportional to the phase difference between LO_I and LO_Q. The theoretical basis for this signal processing follows.

[0040] Assume that the RF and image signals are respectively referred to as V_RFand V_IM. Then the down-converted IF signals are V_I,RF, V_Q,RF, V_J,IM, and V_Q,IM, respectively. After down conversion, and filtering of high-frequency components, the following signals remain:

[0041] V_LO=V₂cos(ω_LOt)

[0042] V_I,RF=½V₁V₂cos(ω_IFt)

[0043] V_Q,RF=−½V₁V₂cos(ω_IFt)

[0044] V_I,IM=½V₁V₂cos(ω_IFt)

[0045] V_Q,IM=½V₁V₂cos(ω_IFt)

[0046] Ideally, subtraction of the I and Q components of the RF and IM signals results in the relationships:

[0047] V_IF,RF=V₁V₂cos(ω_IFt)

[0048] V_IF,IM=0.

[0049] The results above indicate that if the I and the Q demodulator channels are precisely matched, V_IF,IM=0. That is, the image signal will be entirely rejected.

[0050] However, as suggested above, realizable semiconductor implementations, specifically, CMOS implementations, do not enable precisely matched I and Q channels. Mismatch between the I and Q channels may be modeled mathematically as mismatch between the LO_I and the LO_Q signals 13band 14b,respectively. Accordingly:

[0051] V_LO,I=V₂cos(ω_LOt)

[0052] V_LO,Q=(V₂+ΔV₂)cos(ω_LOt+ΔΦ),

[0053] where ΔV and ΔΦ represent the amplitude mismatch and the phase mismatch, respectively, of the I and Q channels. As a result an image component will contaminate the down-converted IF signal. The summed signal corresponding to the image response is:

[0054] V_S,IM=−½V₁cos(ω_IFt)ΔV+{fraction (1/2)}V₁V₂sin(ω_IFt)ΔΦ.

[0055] It is apparent that unwanted image signal consists of two components. The first component is proportional to the amplitude mismatch between the I and Q channels; and the second component is proportional to the phase mismatch. A straightforward mathematical operation, as may be implemented in one of many commercially available DSP integrated circuit devices, may be employed to extract the amplitude error signal and the phase error signal. To wit: V_S,IMmay be multiplied by cos(ω_IFt) to extract the amplitude error signal, and by sin (ω_IFt) to extract the phase error signal.

[0056] In operation of the receiver, the amplitude control signal and the phase control signal are synthesized at intervals during which the receiver is not engaged in the reception and processing of information. For example, a Bluetooth receiver, in accordance with the subject invention, calibrates the I and Q channels during the interstitial time periods between reception of data packets. During the dormant interstitial periods, an RF test tone is applied to the input of the mixer section of the receiver, that is, to the inputs of both the I demodulator and the Q demodulator. Concurrently, disparate LO signals are applied in a time-multiplexed mode, to the input of quadrature LO generator. One of the LO signals runs at the frequency appropriate to the RF test tone so as to result in a desired IF output from the demodulators. The second LO signal is frequency offset from the appearance at the receiver input, an image signal. The response of the I and Q channels to the simulated image is then detected as described above. The amplitude control signal and the phase control signal are used to calibrate the I and Q channels against mismatch.

[0057] In addition, numerous approaches are available to undertake the signal processing inherent in the subject invention. It is understood that the requisite signal processing may be achieved in hardware, software or a combination of the two. The partitioning of these functions is largely with discretion of the receiver designer. However, inasmuch as the subject invention is intended to be realized, so far as practicable, in monolithic integrated circuit technology, it follows that use of one of the many commercially available digital signal processing (DSP) devices is advantageous. DSP devices and techniques are well known to skilled artisans. See, for example, Ralph Chassaing, Digital Signal Processing: Laboratory Experiments Using C and the TMS320C31 DSK(Wiley-Intersorence 1999). If the calibration signals, at both the RF and image, are designed to span the entire dynamic range of the A/D converter, then the achievable image rejection is equivalent to the dynamic range of the A/D converter. For a 10-bit A/D converter, 60 db image rejection is therefore obtainable.

[0058] To this point, a technique for developing both an amplitude control signal, proportional to ΔV, and a phase control signal, proportional to ΔΦ, has been fully explicated. Reiterating, the amplitude control signal appears at output 22c,and the phase control signal at output 22d,of I/S ratio detector 22. As may be seen from FIG. 2, these control signals are applied, respectively, to inputs 21aand 21bof quadrature LO generator 21, in order to control the amplitude and phase differences between LO_I, appearing at output 21d,and LO_Q, appearing at output 21e,of the quadrature LO generator. A preferred implementation of the quadrature LO generator is depicted in FIGS. 4A, 4B and 4C.

[0059] Directing attention first to FIG. 4A, the quadrature LO generator is seen to include a polyphase filter 41 having a balanced (differential) input 41acoupled to the output of the phase-locked local oscillator. The differential input to the polyphase filter consists of an LOP and an LON input. The polyphase filter has a first differential output 41ccoupled to LO_I buffer 42 and a second differential output 41dcoupled to LO₁₃Q buffer 43. The phase control output of I/S detector 22 is coupled to phase control input 41bof the polyphase filter. The amplitude control output of I/S detector 22 is coupled to amplitude control input 42bof LO_I buffer 42 and to the amplitude control input 43bof LO_Q buffer 43.

[0060] An exemplary embodiment of the polyphase filter is depicted in FIG. 4B, in which the polyphase filter may be seen to be implemented in the form of an array of tunable capacitors. The array illustrated in FIG. 4B may be defined in terms the set of circuit nodes that consist of input nodes LOP and LON, output nodes LO_IP, LO_QP, LO_IN and LO_QN, internal nodes 421, 422, 423, 424, and a reference node GND. Each of the internal nodes is coupled through an associated capacitance to a respective output node. In addition, node 421 is coupled through a capacitance to node GND, node 422 is coupled through a capacitance to node LOP, node 423 is coupled through a capacitance to node GND, and node 424 is coupled through a capacitance to node LON. Also, each of the internal nodes, 421, 422, 423 and 424, is coupled through an associated resistance to an output node. In addition, node 421 is coupled through a resistance to node LOP, node 422 is coupled through a resistance to node GND, node 423 is coupled through a resistance to node LON, an node 424 is coupled through a resistance to node GND. The values for the resistances and capacitances depicted in the polyphase filter array of FIG. 4B are determined primarily with respect to the operating frequency of the LO signal source and are easily determined by those skilled in the art. FIG. 4C depicts the manner in which a phase control voltage may be applied to a voltage-tunable capacitance, such as a varactor diode, in a manner that will vary the capacitance of the diode.

[0061] The output nodes of the polyphase filter are coupled to an LO_I buffer and to an LO_Q buffer that effect amplitude control in response to the amplitude control signal supplied by the I/S detector. Specifically, the differential LO_IP and LO_IN output of the polyphase filter are applied to the differential input of LO_I buffer 42, and the differential LO_QP and LO_QN output of the polyphase filter are coupled to the differential input of LO_Q buffer 43. For the purposes of this Description, the LO_I and LO_Q buffers may be understood to be substantially identical in form. An exemplary embodiment of such a buffer is provided in FIG. 4D.

[0062] As seen in FIG. 4D, each buffer is constructed around a matched pair of transistors, M1 and M2, arranged in a differential amplifier configuration. In each buffer, the respective differential LO_I or LO_Q input is applied to the input of the differential amplifier, at gate electrodes of M1 and M2. M1 and M2 are MOSFETS configured in a source-coupled mode. Amplitude control of the input LO_I and LO_Q signals is effected by controlling the bias current flowing in M1 and M2. In the arrangement of FIG. 4D a bank of constant-current sources 441, 442, 443 and 444 are coupled in parallel to the common sources of M1 and M2. The respective magnitudes of the currents sourced by sources 441, 442, 443 and 444 are binary weighted, so that the current of source 442 is twice the current of source 441, the current of source 443 is twice the current of 442, and so forth. As may be expected, the binary amplitude control signal from the amplitude meter of I/S detector 42 operates to selectively render the separate binary-weighted current sources conductive or non-conductive, thereby varying the gain imparted by the differential amplifier to the input LO_I or LO_Q signal. As suggested in FIG. 4D, it is deemed preferable that at least one of the current sources remain continuously conductive so that M1 and M2 are always biased with a nominal quiescent current flow. To this end, current source 444 remains continuously conductive.

[0063] Although the subject invention has been described in detail in the context of the exemplary embodiments presented above, the invention, is not to be limited to the described embodiments, but is to be afforded a scope commensurate with the appended Claims, and substantial equivalents thereof. Those having ordinary skill in the art may readily comprehend various additions, modifications and improvements to the described embodiments of the invention, and all such modifications are to be deemed within the scope of the invention.