Data encoding method, apparatus, and storage medium

[0002] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-055529, filed Feb. 28, 2001, the entire contents of which are incorporated herein by reference.

[0003] 1. Field of the Invention

[0004] This invention relates to a data encoding method, apparatus, and storage medium. The invention is relates to an apparatus which records digital data onto a storage medium, such as an optical disk, or reproduces the recorded data. The invention further relates to a data encoding method and apparatus suitable for the conversion of digital data into bit sequences to be recorded onto a storage medium, and to a storage medium on which data is to be recorded or has been recorded.

[0005] 2. Description of the Related Art

[0006] To record digital data onto an optical disk or the like, bit sequences of digital data are required to have various characteristics. The bit sequences recorded on a playback-only optical disk are expressed as bumps or pits on the reflecting surface. In a recordable magnet-optical disk, recorded bit sequences are expressed as sequences of magnetized marks. In a phase change disk, recorded bit sequences are expressed as sequences of marks with optical constants.

[0007] The disk manufacturing processes are required to be easy. The optical characteristics in reading with a laser beam are needed to be good. The characteristics in reproducing the digital data from the read-out signal must also be good. Therefore, it is necessary to convert the recording data into bit sequences that satisfy the above requirements. That is, an encoding process must be carried out.

[0008] When the recorded minimum pit length is small, if the optical characteristics deteriorate, the output of the reproduced signal decreases significantly. Thus, it is desirable that the minimum pit length should be great. Conversely, if the maximum pit length is great, the number of inversions of the reproduced signal decreases. This makes the timing for reproducing the clock unstable, making jitters in the clock larger. As a result, code errors in the reproduced signal are liable to occur. Therefore, it is desirable that the maximum pit length should be small.

[0009] It is also important that the direct-current (DC) component and low-frequency components of the recording signal are small. These signal components might affect the tracking servo that traces the track formed on the optical disk. To read the signal accurately, it is necessary to suppress those signal components. Another requirement is that the sensing window width should be wide. If the original data was converted into many bits and recording took place, phase allowance in time during sensing would become smaller, even when the pit length condition was satisfied. At the same time, the reproducing clock frequency would become higher.

[0010] One encoding method taking these conditions into account is the 8/14 encoding method disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 6-284015. The 8/14 encoding method is an encoding method of converting 8-bit data into 14-bit code.

[0011] In this method, a plurality of tables for code conversion are used and switching is done between the tables in such a manner that the value (DSV: digital sum value) accumulated, taking bit “0” as “−1” and bit “1” as “+1” in a recording bit sequence, becomes smaller. This makes it possible to suppress the direct-current component and low-frequency components sufficiently.

[0012] On the other hand, since the number of bits after the encoding increases to 14/8 times the number of bits in the original data, this makes the sensing window width smaller and increases the clock frequency at the same rate. In recent years, digital recording apparatuses have been required to have higher data transfer speeds. Increases in the data recording and reproducing speeds increase the clock frequency, which might be an obstacle to configuring a signal processing circuit.

[0013] Another encoding method has been disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 56-149152. In the encoding-method, the data is converted into a code containing as many as 1.5 times the number of bits in the data. Since the number of consecutive bits “0s” between bits “1s” is one or more and seven or less, this type of method is generally called (1, 7) RLL coding.

[0014] This method is characterized in that a signal processing circuit can be configured using a small circuit and a relatively low clock frequency. Since this method does not manage the DSV at all, as in the 8/14 method, the direct-current component and low-frequency components cannot be suppressed. Thus, in this method, the tracking performance might be affected. To avoid this phenomenon, it is necessary to insert adjustment bits in addition to the recording data to make the DSV smaller. When such adjustment bits are inserted, the number of redundant bits on the medium increases. This causes a new problem: the storage capacity of the original data decreases. There is another problem: since variable-length coding includes the conversion of 2 bits into 3 bits and the conversion of 4 bits into 6 bits, bit errors are liable to propagate.

[0015] As described above, in the conventional encoding methods, suppressing the low-frequency components permits the clock frequency to rise, whereas decreasing the clock frequency to a low level makes it impossible to suppress the low frequency components. There is still another problem: adding adjustment bits increases the number of redundant bits, which decreases the storage capacity of the original data on a storage medium.

[0016] It is an object of the present invention to provide a data encoding method and a data encoding apparatus which need not raise the recording clock frequency too much and can suppress the low-frequency components without using adjustment bits, and a storage medium.

[0017] According to an aspect of the present invention, there is provided a data encoding method of converting an L-bit data word into an αL-bit code word, comprising: dividing the L-bit data word into an M-bit data word and an N-bit data word (M≧N); converting the M-bit data word into a βM-bit code word by reference to a first conversion table; converting the N-bit data word into a γN-bit code word by reference to a second conversion table; and connecting the βM-bit code word to the γN-bit code word to convert into the αL-bit code word.

[0018] Whether to select either the first or the second conversion table is determined by a combination of the M-bit data word and the N-bit data word.

[0019] Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.

[0020] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention, and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.

[0021] FIG. 1 shows an example of an 18-bit pattern where the number of consecutive “0s” is limited to one or more and eleven or less;

[0022] FIG. 2 shows a method of converting a 12-bit data word into an 18-bit code word;

[0023] FIG. 3 shows a pattern that satisfies the condition for conversion table A used for the converting process in FIG. 2;

[0024] FIG. 4 shows a pattern that satisfies the condition for conversion table B used for the converting process in FIG. 2;

[0025] FIG. 5 shows a pattern that satisfies the condition for conversion table A-1 included in conversion table A;

[0026] FIG. 6 shows a pattern that satisfies the condition for conversion table A-2 included in conversion table A;

[0027] FIG. 7 shows a pattern that satisfies the condition for conversion table A-3 included in conversion table A;

[0028] FIG. 8 shows a pattern that satisfies the condition for conversion table A-4 included in conversion table A;

[0029] FIG. 9 shows a pattern that satisfies the condition for conversion table A-5 included in conversion table A;

[0030] FIG. 10 shows a pattern that satisfies the condition for conversion table A-6 included in conversion table A;

[0031] FIG. 11 shows a pattern that satisfies the condition for conversion table A-7 included in conversion table A;

[0032] FIG. 12 is a table listing combinations of the patterns in conversion table A and conversion table B and the number of combinations;

[0033] FIG. 13 illustrates an example of DSV control;

[0034] FIG. 14 is a table listing combinations of the patters to be removed from the conversion tables A and B;

[0035] FIG. 15 is a block diagram of a circuit for converting data words into code words;

[0036] FIGS. 16A and 16B are illustrations to help explain a method of forming a data word; and

[0037] FIG. 17 is a diagram to help explain an information medium recording/reproducing apparatus to which the present invention is applied.

[0038] Hereinafter, referring to the accompanying drawings, an embodiment of the present invention will be expelled.

[0039] The basic concept of the present invention will be explained. In this invention, the size of a data word may take various values. For the sake of an example, a detailed explanation will be given about an embodiment where the invention is applied to the 12/18 modulation method that converts a 12-bit data word into an 18-bit code word.

[0040] The original data to be encoded contains 12 bits. The number of bit patterns represented by the 12 bits is 4096. The code after encoding contains 18 bits. The number of bit patters represented by the 18 bits is 262144. Here, the encoding process corresponds to the process of allocating words between the 4096 patterns and the 262144 patterns.

[0041] The primary conditions required for the encoding method are summarized again as follows: 1) the minimum pit length must be great, 2) the maximum pit length must be small, 3) the direct-current component and low-frequency components must be less in the recording signal, 4) the sensing window width must be great, and 5) the reproducing clock frequency is low.

[0042] To meet the conditions of item 1) and item 2), consider, as the bit patterns of a code, combinations that satisfy the condition for (1, 11) RLL where the number of consecutive bits “0s” between bits “1” is limited to one or more and eleven or less.

[0043] Under the condition for a code word alone, the number of 18-bit patterns that fulfill (1, 11) RLL is 6686 in total.

[0044] FIG. 1 shows an example of the bit patterns. Since the number of patterns that satisfy the conditions exceeds the number of patterns (4096) expressed by 12 bits, the code conversion of 12 bits into 18 bits is sufficiently possible.

[0045] However, when the 18-bit codes after conversion are connected consecutively, the condition for (1, 11) RLL may not be fulfilled at the boundary between the codes. When any two codes are connected to each other, there may be combinations where bits “1s” might be consecutive at the boundary between the codes or more than 12 bits “0s” might be consecutive.

[0046] To avoid those combinations, the following restrictions are imposed on the bit patterns of FIG. 1 so that the condition for (1, 11) RLL may be fulfilled even at the junction of the codes: the bit pattern must be such that the number of consecutive bits “0s” at the head of a code is five or less and the number of consecutive bits “0s” at the end of the code is one or more and six or less.

[0047] Adding this condition decreases the number of possible codes to 3710. Therefore, even when such codes are connected, it is not easy to satisfy the condition for (1, 11) RLL.

[0048] Even if a conversion table is obtained, the direct conversion of 12-bit data into an 18-bit code requires a conversion table which has a capacity of

[0049] 4094×18 bits=73728 bits or more.

[0050] Thus, a lot of memory is needed for the conversion process.

[0051] In the embodiment, to overcome this problem, 12 bits of data are divided into two, the high-order bits and the low-order bits. At the same time, the high-order bits and the low-order bits are converted into codes using the conversion table. The codes after the conversion are connected, thereby making the conversion table smaller.

[0052] FIG. 2 is a diagram to help give a brief explanation of the converting method.

[0053] The inputted 12 bits of data are first divided into the 8 high-order bits and the 4 lower-order bits (step S1).

[0054] The 8 high-order bits are converted into a 12-bit code using conversion table A (step S2). On the other hand, the 4 low-order bits are converted into a 6-bit code using conversion table B (step S3).

[0055] The 12-bit code converted with conversion table A is connected to the 6-bit code converted with conversion table B in such a manner that the former becomes the high order and the latter becomes the low order. As a result, an 18-bit code is outputted (step S4).

[0056] Each of the conversion tables A and B includes a plurality of tables. Of these tables, the one to be used is selected, depending on the output of a table select section C. Twelve bits of data are inputted to the table select section C. According to a predetermined decode rule, the table select section C outputs conversion table select information for determining a table to be used (step S0).

[0057] That is, the table select section C controls conversion table A and conversion table B, thereby determining a code combination pattern. Codes are combined to form a code word.

[0058] The connected 18-bit code includes some selectable codes as the low-order bits. These bits are determined so as to fulfill the (1, 11) RLL rule at least at the code boundary (step S5).

[0059] Next, a method of creating a conversion table will be explained.

[0060] As candidate codes in conversion table A, codes with patterns satisfying the following rules are selected:

[0061] 1) The number of consecutive “0s” between “1s” is one or more and eleven or less.

[0062] 2) The number of consecutive “0s” at the head is 10 or less.

[0063] 3) The number of consecutive “0s” at the end is 11 or less.

[0064] The number of 12-bit patterns fulfilling the above conditions is 375.

[0065] FIG. 3 shows a part of the patterns.

[0066] On the other hand, as candidate codes in conversion table B, codes with patterns fulfilling the following rules are selected:

[0067] 1) The number of consecutive “0s” between “1s” is one or more.

[0068] 2) A pattern which ends with “1” is combined with a pattern which is the same as the former except for the end and has “0” at the end. Then, “0” at the end is replaced with “*” (indefinite). This will be explained in detail later.

[0069] There are 13 6-bit patterns that fulfill the above conditions.

[0070] FIG. 4 shows those patterns. In FIG. 4, “*” means that it is replaced with either “1” or “0” by a method explained later.

[0071] If 375 patterns in conversion table A and 13 patterns in conversion table B can be combined to form patterns, as many patterns as 375×13=4888 can be produced. Actually, however, there are combinations which do not satisfy the conditions for (1, 11) RLL at the junction of two patterns.

[0072] Thus, the conversion tables A and conversion tables B are further classified, thereby narrowing the combinations to the ones which fulfill the conditions for (1, 11) RLL.

[0073] A method of classifying the conversion tables A will be explained. The conversion tables A are classified into seven conversion tables, conversion table A-1 to conversion table A-7, according to the following condition.

[0074] Let conversion table A-1 be a pattern which fulfills the following condition among the candidates for conversion table A:

[0075] 1) The number of consecutive “0s” at the end of a pattern is one or more and five or less.

[0076] There are 212 patterns which satisfy this condition.

[0077] FIG. 5 shows part of the patterns included in conversion table A-1.

[0078] Let conversion table A-2 be a pattern which fulfills the following condition among the candidates for conversion table A:

[0079] 1) A pattern ends with “1.”

[0080] There are 143 patterns which fulfill this condition.

[0081] FIG. 6 shows part of the patterns included in conversion table A-2.

[0082] Let conversion table A-3 be a pattern which fulfills the following condition among the candidates for conversion table A:

[0083] 1) The number of consecutive “0s” at the end of a pattern is 6 or more or 7 or less.

[0084] There are 13 patterns which fulfill this condition.

[0085] FIG. 7 shows the patterns included in conversion table A-3.

[0086] Let conversion table A-4 be a pattern which satisfies the following condition among the candidates for conversion table A:

[0087] 1) The number of consecutive “0s” at the end of a pattern is 8.

[0088] There are three patterns which fulfill this condition.

[0089] FIG. 8 shows the patterns included in conversion table A-4.

[0090] Let conversion table A-5 be a pattern which satisfies the following condition among the candidates for conversion table A:

[0091] 1) The number of consecutive “0s” at the end of a pattern is 9.

[0092] There are two patterns which fulfill this condition.

[0093] FIG. 9 shows the patterns included in conversion table A-5.

[0094] Let conversion table A-6 be a pattern which satisfies the following condition among the candidates for conversion table A:

[0095] 1) The number of consecutive “0s” at the end of a pattern is 10.

[0096] There is one pattern which fulfills this condition.

[0097] FIG. 10 shows the pattern included in conversion table A-6.

[0098] Let conversion table A-7 be a pattern which satisfies the following condition among the candidates for conversion table A:

[0099] 1) The number of consecutive “0s” at the end of a pattern is 11.

[0100] There is one pattern which fulfills this condition.

[0101] FIG. 11 shows the pattern included in conversion table A-7.

[0102] Next, a method of combining the conversion tables classified from conversion table A and conversion table B will be explained by reference to FIG. 12.

[0103] The number of consecutive “0s” at the head of a pattern in conversion table B is in the range from 0 to 6 including “*.” Therefore, even when a code in conversion table B is connected to a code in conversion table A-1, the number of consecutive “0s” at the junction is in the range from 1 to 11. Thus, it is possible to combine all the patterns (or codes) shown in FIG. 4 with the patterns (or codes) in conversion table A-1. As a result, from the combinations of the patterns shown in conversion table B and the patterns shown in conversion table A-1, as many 18-bit patterns as 213×13=2756 can be produced.

[0104] In conversion table A-2, any pattern always ends with “1.” To fulfill the conditions for (1, 11) RLL, the five patterns beginning with “1” in conversion table B cannot be connected. Thus, the number of patterns (or codes) connectable with the patterns (or codes) in conversion pattern A-2 is only eight. As a result, from the eight patterns in conversion table B and the patterns shown in conversion table A-2, as many 18-bit patterns as 143×8=1144 can be produced.

[0105] Only the twelve patterns where the number of consecutive “0s” at the head of each pattern is four or less in the patterns in conversion table B can be combined with the patterns shown in conversion table A-3. As a result, as many 18-bit patterns as 13×12=156 can be produced.

[0106] Only the eleven patterns where the number of consecutive “0s” at the head of each pattern is three or less in the patterns in conversion table B can be combined with the patterns shown in conversion table A-4. As a result, as many 18-bit patterns as 13×11=33 can be produced.

[0107] Only the ten patterns where the number of consecutive “0s” at the head of each pattern is two or less in the patterns in conversion table B can be combined with the patterns shown in conversion table A-5. As a result, as many 18-bit patterns as 2×10=20 can be produced.

[0108] Only the eight patterns where the number of consecutive “0s” at the head of each pattern is one or less in the patterns in conversion table B can be combined with the patterns shown in conversion table A-6. As a result, as many 18-bit patterns as 1×8=8 can be produced.

[0109] Only the five patterns where the ones beginning with “1” of the patterns in conversion table B can be combined with the patterns shown in conversion table A-7. As a result, as many 18-bit patterns as 1×5=5 can be produced.

[0110] From the above results, the total number of 18-bit patterns in conversion table A and conversion table B which can be combined is 2756+1144+156+33+20+8+5=4122. The 4122 18-bit patterns are larger in number than the 4096 12-bit input data patterns.

[0111] Consequently, it is seen that the 12-bit data can be converted into 18-bit codes with the (1, 11) RLL characteristic. In fact, 4096 combinations are selected from the 4122 combinations of patterns, thereby forming conversion tables.

[0112] As described above, under only the condition for code words, 12 bits can be converted into 18 bits.

[0113] Next, the state of a connection between 18-bit code words will be explained.

[0114] The last two bits in the 6-bit patterns in conversion table B are either “10” or “0*.” On the other hand, in conversion table A, data exists in the rang from one to ten consecutive “0s” or “1.”

[0115] Therefore, when conversion table B ends with “10,” the number of consecutive “0s” at the boundary between codes is in the range from one to eleven, which satisfies the rule for (1, 11) RLL. On the other hand, when conversion table B ends with “0*,” either “0” or “1” can be selected for “*.” Because of this selection, either “0” or “1” can be selected so as to fulfill the rule for (1, 11) RLL.

[0116] When the first bit of conversion table A at the code junction is “1,” a selection is so made that “*” is always “0.” When the number of consecutive “0s” exceeds 11 after “*” is replaced with “0,” a selection is so made that “*” is always “1.” By making a selection in this way, the rule for (1, 11) can be satisfied.

[0117] In a case where the rule for (1, 11) RLL can be fulfilled even if “*” is replaced with “0” or “1,” either “0” or “1” may be selected.

[0118] As described above, with the data converting method in the embodiment, when a 12-bit data word is converted into an 18-bit code word, the 12-bit data word can be divided into the 8 high-order bits and the 4 low-order bits. Using the conversion tables, the 8 high-order bits are converted into 12 bits and the 4 low-order bits are converted into 6 bits. The 12 bits and the 6 bits are connected in such a manner that the former become the high-order bits and the latter become the low-order bits, thereby creating an 18-bit code.

[0119] This makes it possible to convert data words into code words using small conversion tables.

[0120] Since information about the result of the past selection is not needed in the process of selecting a conversion table, when a converted code word is restored to the original data word, errors are prevented from propagating from one code to another.

[0121] (About DC control method)

[0122] In the conversion table of FIG. 12, there may be a case where either “0” or “1” can be selected freely for “*” located at the end of conversion table B. Such a bit is called a DC control bit, which can be used for suppressing the low-frequency components included in the bit sequence of the converted code word.

[0123] Next, the method of suppressing the low-frequency components will be explained.

[0124] The bit sequence of the code word obtained using the conversion tables is subjected to ZRZI conversion. That is, the code word is inputted to the converting section. When receiving “1” in the code word, the converting section inverts either “0” or “1” presently held on the output side. During the time when “0” continues to arrive, the conversion section keeps the present output “0” or “1.” Different recording signal levels are allocated to “0” and “1” after NRZI conversion. By doing this, an actual recording signal is created.

[0125] When the value (DSV) is accumulated, taking “0” of the NRZI-converted signal as “−1” and “1” of the signal as “+1,” the DSV level presents the direct-current component that the recording signal has and the variable period of the DSV represents the low-frequency components. To suppress the direct-current component and low-frequency components of the recording signal to low levels, it is necessary to make the absolute value of the DSV smaller. Furthermore, shortening the variable period of the DSV enables the low-frequency components to be suppressed to a low level.

[0126] FIG. 13 is a diagram to help explain a method of controlling the DSV by using “*” acting as a DC control bit at the end of a pattern in conversion pattern B.

[0127] A bit sequence indicated by reference numeral 13ain FIG. 13 is a bit sequence of a code word. A bit sequence indicated by reference numeral 13bis a data sequence after NRZI conversion. A waveform indicated by reference numeral 13cis a recording signal. A case where “*” serving as a DC control bit is “=0” is shown at left of FIG. 13. A case where “*” serving as a DC control bit is “*=1” is shown at right of FIG. 13.

[0128] A waveform indicated by reference numeral 13din FIG. 13 shows the way the DSV of the left-side data sequence changes. A waveform indicated by reference numeral 13eshows the way the DSV of the right-side data sequence changes.

[0129] When only one bit in the code word (13a) is inverted from “0” to “1,” the signal (13b) after NRZI conversion is such that the polarity of the signal after the inverted bit reverses. As shown in FIG. 13, inverting a bit causes the DSV (13d, 13e) after the inverted bit to change in the opposite direction.

[0130] In the example of the code word in FIG. 13, a comparison between the DSVs (13d, 13e) shown at left and at right has shown that the absolute value of the DSV (13d) without bit inversion is smaller.

[0131] Therefore, to control the direct-current component of the code word, the DSV with the inversion of the DC control bit and the DSV without the inversion of the DC control bit are calculated. That is, it is determined in advance which is smaller, the absolute value of the DSV with “*” replaced with “0” beforehand or the absolute value of the DSV with “*” being “1.” According to the result of the determination, either “0” or “1” is selected for the position where a DC control bit “*” will actually appear next time, in such a manner that the absolute value of the DSV becomes smaller.

[0132] In the method of controlling the DC control bit, control may be performed in such a manner that the peak of the absolute value of the DSV until the appearance of the next DC control bit becomes smaller or that the polarity of the DSV is reversed.

[0133] (About the limitation on the number of consecutive detailed patterns)

[0134] In the conversion table of FIG. 12, there are 4122 combinations of code words for 4096 input data items. Therefore, there are still 26 combinations left. By suitably selecting unused 26 patterns from the 4122 patterns, the conversion table can be optimized.

[0135] Hereinafter, a selecting method for using unused pattern effectively will be explained.

[0136] The optical resolution characteristic of optical disks is such that, as the length of a pit becomes shorter, the amplitude of the reproduced signal decreases and the reliability of the recorded data is impaired. Therefore, a succession of short pits results in a decrease in the signal amplitude for a long time. Such a phenomenon is undesirable for the signal reproducing function.

[0137] By removing patters with a succession of short pits, a more suitable bit sequence can be created. In the (1, 11) RLL characteristic, the shortest pit, which is as long as 2 bits (2T), appears in the place where only one “0” is sandwiched between “1” and “1.” Thus, by removing patterns where “1” and “0” appear alternately from the conversion tables, short pits are prevented from appearing consecutively.

[0138] FIG. 14 shows the combinations of patterns practically removed from the conversion tables.

[0139] A first to a thirteenth combination of code patterns are combinations of patterns removed to limit the number of repetitions of “1” and “0” on the head side of the pattern to less than four. A fourteenth to a seventeenth combination of code patterns are combinations of patterns extracted to limit the number of repetitions of “1” and “0” on the end side of the pattern to six or less.

[0140] These 17 combinations are removed from the conversion tables. Moreover, when replacing a “*” with “1” in the conversion table causes the number of repetitions of “1” and “0” to exceed 10, a rule that the “*” never fails to be replaced with “0” is set. Setting the rule enables repetitions of “1” and “0” to be limited to 10 or less consecutive ones.

[0141] Since the combinations of the patterns to be recorded shown in FIG. 14 are smaller in number than the 26 unused patterns in the conversion table shown in FIG. 12, even if the patterns shown in FIG. 14 are removed, it is sufficiently possible to convert 12-bit data into 18-bit codes.

[0142] (About the configuration of the converting circuit)

[0143] Using FIG. 15, the converting circuit that realizes data conversion in the present invention will be explained.

[0144] The data normally inputted in bytes from an input terminal 100 is reconstructed into a data word in units of 12 bits at a data word constructing section 101.

[0145] FIG. 16A and FIG. 16B show a method of reconstructing the data. One reconstructing method is to arrange 3-byte input data items (=8×3=24 bits) one after another, thereby segmenting the data in units of 12 bits as shown in FIG. 16A. In the example of FIG. 16A, a first 8-bit unit, a second 8-bit unit, and a third 8-bit unit are arranged, with the second 8-bit unit being halved. Then, the divided first 4 bits are connected to the first 8-bit unit and the divided second 4 bits are connected to the third 8-bit unit.

[0146] In FIG. 16B, the third 8-bit unit is halved. Then, the divided first 4 bits are connected to the end of the first 8-bit unit and the divided second 4 bits are connected to the end of the second 8-bit unit.

[0147] The 8 high-order bits in the 12-bit data outputted from the data word constructing section 101 of FIG. 15 are given to a table conversion section (A) 102 and the 4 low-order bits are given to a table conversion section (B) 103. At the same time, the 12-bit data is given to a table select section 104.

[0148] The table conversion section (A) 102 includes a plurality of conversion tables for converting 8-bit data words into 12-bit code words. The table conversion section (A) 102 receives a table select signal generated at the table select section 104 and carries out pattern conversion using a suitable conversion table on the basis of the table select signal.

[0149] Similarly, the table conversion section (B) 103 includes a plurality of conversion tables for converting 4-bit data words into 6-bit code words. The table conversion section (B) 103 receives a table select signal generated at the table select section 104 and carries out pattern conversion using a suitable conversion table on the basis of the table select signal.

[0150] Part of the patterns in the conversion tables of the table conversion section (B) 103 end with DC control bits. The DC control bits can be replaced with either “0” or “1.”

[0151] On the basis of a predetermine rule, the table select section 104, according to the 12-bit input data, generates a specify signal for selecting a conversion table used in the table conversion section (A) 102 and table conversion section (B).

[0152] The code word constructing section 105 uses the 12 bits outputted from the table conversion section (A) 102 as the high-order bits and the 6 bits outputted from the table conversion section (B) 103 as the low-order bits, thereby creating a code word containing 18 bits in total.

[0153] The output of the code word constructing section 105 is supplied to a digital sum value (DSV) computing section 106. The DSV computing section 106 senses the direct-current (DC) component included in the bit sequence of a word code. When the bit sequence of the code word is subjected to NRZI conversion, the DC component can be calculated by accumulating the values, taking “0” as “−1” and “1” as “+1.” The calculated DSV value is supplied to a DC control section 107. The DC control section 107 executes a specific algorithm, and outputs, for example, information for selecting a DC control bit so that the absolute value of a DVD may become smaller.

[0154] The control information, which is inputted to a code determining section 108, is used for determining whether to replace the DC control bit included together with the code connection condition with either “0” or “1.” The determined code is outputted at an output terminal 109.

[0155] When a 12-bit data word is converted into an 18-bit code word, using directly a single conversion table makes the size of conversion table very large. However, use of the converting circuit with the configuration of FIG. 15 enables small conversion tables to be combined, which makes it possible to convert the data with the small-scale circuit.

[0156] In the embodiment, when a 12-bit data word is converted into an 18-bit code word, the 12-bit data word is divided in such a manner that the 8 high-order bits are converted into 12 bits and the 4 low-order bits are converted into 6 bits. However, the dividing method is not limited to this combination. For instance, a 12-bit data word may be divided into the 4 high-order bits and the 8 low-order bits or into the 10 high-order bits and the 2 low-order bits. Although a DC control bit is placed at the end of the low-order pattern, it is not limited to this position.

[0157] As for the number of bits in a data word and a code word and the conversion ratio of them, the present invention may be applied to other combinations. For instance, a similar method according to this invention may be applied to a case where a 16-bit data word is converted into a 24-bit code word. While in the embodiment, the created code word has the (1, 11) RLL characteristic, it may have a different characteristic. Since the optimum characteristic changes as the conversion ratio changes, the characteristic of the created code word is not limited to a particular characteristic.

[0158] In the embodiment, the bit dividing position is not limited. Even when the high-order and low-order in each conversion table are reversed and the high-order bits and the low-order bits are inverted in each conversion table, an effect equivalent to the effect of the embodiment is produced. In that case, a DC control bit appears at the first bit of the code word after the conversion.

[0159] As described above, a first main point of the present invention is as follows.

[0160] When a 12-bit data word is converted into an 18-bit code word, the 12-bit data word is divided into the 8 high-order bits and the 4 low-order bits. The 8 high-order bits are converted into 12 bits and the 4 low-order bits are converted into 6 bits, thereby creating an 18-bit code, which enables conversion using a small-scale conversion table.

[0161] Specifically, in the data encoding method of converting an L-bit data word into an αL-bit code word, the L-bit data word is divided into an M-bit data word and an N-bit data word (M≧N), the M-bit data word is converted into a βM-bit code word using a first conversion table, the N-bit data word is converted into a γN-bit code word using a second conversion table, and the βM-bit code word is connected to the γN-bit code word, with the result that the L-bit data word is converted into the αL-bit code word.

[0162] The first conversion table is further composed of a plurality of conversion tables. The second conversion table is further composed of a plurality of conversion tables. A method of selecting the first and second conversion tables is determined by a combination of an M-bit data word and an N-bit data word.

[0163] Converting an L-bit data word directly into an αL-bit code word makes the conversion table larger. However, as explained in the invention, a data word is divided into suitable sets of bits. After the divided patterns are connected using different conversion tables, the resulting patterns are combined, which enables the data to be converted using small conversion tables.

[0164] Furthermore, the present invention makes NRZI conversion easier. That is, an αL-bit code word is subjected to NRZI conversion. In NRZI conversion, the output is inverted when “1” appears, whereas the output remains unchanged when “0” appears.

[0165] In this invention, it is easy to control the digital sum value of an αL-bit code word, or perform direct-current (DC) control. To realize this, 1) one conversion table includes DC control bits; 2) the DC control bits are included in a part of the code words in a second conversion table; and 3) each DC control bit is placed at the end of a code word.

[0166] In this invention, DC control is performed by selecting either “0” or “1” for one bit in the code word. One method of selecting a DC control bit is to accumulate the value, taking “0” in an αL-bit word code as “−1” and “1” as “+1,” and select DC control bits in such a manner that the absolute value of the accumulated value becomes smaller. Another method of selecting a DC control bit is to calculate the value, taking “0” in an αL-bit word code as “−1” and “1” as “+1,” and select DC control bits in such a manner that the signs of the accumulated values are inverted one after another in αL-bit word codes. When the signs are the same, DC control bits are selected in such a manner that the absolute values become smaller.

[0167] Concentrating DC control bits into one divided conversion table (or table B) makes the select algorithm for the conversion table and DC control easier.

[0168] In this invention, the data conversion tables are characterized in that 1) a code word in the first conversion table includes at least one “1” and that 2) an αL-bit code word includes a part where at least two “0s” are consecutive.

[0169] Furthermore, the conditions for L, M, N, α, β, and γ are characterized in that 1) L bits are divided into M bits as the high-order bits and N bits as the low-order bits and αL bits are divided into βM bits as the high-order bits and γN bits as the low-order bits, where M is a multiple of 8 and α is 2 or less. In addition, βM is larger in number than the maximum number of consecutive “0s” appearing in the bit sequence after the conversion. Moreover, α, β, and γ fulfill the expression α=β=γ. Specifically, L is 12, M is 8, N is 4, and α, β, and γ are each 1.5.

[0170] The present invention is not limited to the above embodiment. In the explanation, the data to be recorded on a recording medium has been encoded. This invention, of course, may be applied to a case where the data is encoded and the encoded data is transmitted over a channel (by wireless, by wire, by light, or the like).

[0171] FIG. 17 shows a recording/reproducing disk 200 on which data is recorded by the data encoding method of the present invention and a pickup head 201 which projects a write laser beam or a read laser beam onto the information recording surface of the disk 200. A modulation/demodulation section 203 is connected to the pickup head 201. In a recording operation, the modulation/demodulation section 203 subjects the data supplied from a signal processing section 204 to 12/28 modulation by the above-described encoding method and supplies the resulting output to the pickup head 201. To demodulate the reproduced high-frequency signal outputted from the pickup head 201, the reproduced high-frequency signal is binarized to demodulate the 18-bit signal into a 12-bit signal. At this time, a converting process opposite to the aforementioned encoding process is carried out. In this converting process, the input data is just converted using a suitable table.

[0172] The signal processing section is a circuit which encodes and decodes, for example, audio data, movie video data, and still video data. The signal processing section may include a signal transmission/reception section. The optical disk has an information recording area (or data area). The data recorded in the area is the data encoded as described above.

[0173] While in the explanation, the optical disk has been used as an information medium, a semiconductor memory or a transmission line, etc., may of course, be used as the information medium.

[0174] One way of using a storage medium, such as an optical disk or a semiconductor memory, involves the user recording/reproducing content (e.g., video information, audio information, or update information) using the apparatus. The fixed information may also be recorded in advance on the storage medium manufacturing side. The fixed information includes management information for system management. Therefore, the fixed information is, of course, recorded using the encoding method of the present invention.

[0175] The above embodiment not only lowers the operating frequency of the recording/reproducing signal processing circuit but also prevents the memory capacity from being wasted on the recording medium side, and provides stable tracking.

[0176] Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.