Current limiting technique for hybrid power MOSFET circuits

[0002] 1. Field of the Invention

[0003] The present invention relates to the field of semiconductor power switches. More particularly, the present invention relates to limiting the current in a power field effect transistor being used as a switch.

[0004] 2. Related Art

[0005] Traditionally current limiting in a power switch has been done by a method called fold back current limiting. When using a FET as a power switch, the gate to source voltage (V_GS) of the FET is the control voltage that is regulated in order to limit the FET drain current to a predefined level. The disadvantage of the fold back current limiting approach is that the voltage between the drain terminal and the source terminal (V_DS) must be increased as V_GSis being reduced in order to keep the current at a predefined level. This forces the FET to enter saturation region, which is a high power-operating region. Since the device is operating in a high power region in the current limiting mode, the junction temperature of the device will rise above allowable device limits and will cause damage to the FET unless thermal protection is implemented in the circuit. In order to prevent damage to the FET, a thermal protection circuit may be used to shut down or turn off the FET when the temperature exceeds a predefined level. Such a thermal protection circuit may be designed to turn the FET back on as the device temperature falls below a predefined level.

[0006] Accordingly, what is needed is a power FET switching circuit that will overcome the disadvantages of traditional fold-back current limiting methods. More specifically, what are needed are a circuit and/or method that will ensure that the operation of a power FET switch is always below its maximum operating limits. In addition, what are also needed are a circuit and/or method that will eliminate the need for temperature sensing or thermal shutdown circuits. The present invention provides these advantages and others not specifically mentioned above but described in the sections to follow.

[0007] What are described are a power FET and a replica FET on a semiconductor chip coupled to a logic control circuit on a second semiconductor chip within a single housing. A power FET and a scaled down replica of the power FET are disposed on a semiconductor chip. The power FET is used as a switch to couple a DC power source to a load. A fraction of the power FET drain current passes through the replica FET and an external sense resistor. When the voltage across the external sense resistor exceeds a maximum value based upon the maximum allowable power FET drain current, the logic control circuit enters into a pulsed gate (PG) mode of operation. The first step in the PG mode is to switch both FETs into a nonconducting state for a predefined period of time. After this time period, a ramp voltage applied between gate and source of both FETs switches them back into a current conducting state while holding the power FET drain current below its upper limit in the presence of a high capacitance or short circuit load. If the voltage across the external resistance increases above the maximum, the PG mode of operation continues. PG mode ceases and normal operation follows when the external resistance voltage remains below the established maximum. The combination of predefined non-conducting time and maximum drain current ensures operation of the power FET below maximum power dissipation limits. In other words, embodiments of the present invention keep the FET from operating in the saturation region. The PG mode of operation eliminates the need for additional temperature and thermal control circuits.

[0008] In one embodiment of the present invention, a power MOSFET and a replica of the power MOSFET disposed on a first semiconductor chip, and a logic and control circuit disposed on a second semiconductor chip are coupled and contained within a single housing. This semiconductor switching circuit utilizes negative feedback in order to maintain a drain current in the replica MOSFET that is a constant fractional value of the drain current in the power MOSFET. The replica MOSFET drain current is conducted through an external resistance. The value of the external resistance is selected in terms of the maximum allowable power MOSFET drain current in order to establish a trip.voltage level. A voltage across the external resistance greater than the trip voltage level will cause the logic and control circuit to enter a pulse gate (PG) mode of operation. In PG mode, both MOSFETs are initially switched into and held in a non-current conducting state for a period of time. At the end of this time period, a ramp voltage is applied gate-to-source to switch both MOSFETs in a timely manner back into a current conducting state. The ramp voltage ensures the MOSFETs do not exceed maximum current limits even in the presence of an excessive capacitive load. If the voltage across the external resistance exceeds the trip voltage level as the ramp voltage is applied, both MOSFETs will again be switched off and PG mode operation will repeat. Normal operation will then be established when power MOSFET drain current is reduced and the voltage across the external resistance remains below the trip voltage level. The combination of off time and maximum power MOSFET drain current established in the PG mode thus ensures operation of the power MOSFET below maximum power dissipation limits as established according to the thermal characteristics of the package used to house the devices. Furthermore, the need for any additional temperature sensing and/or thermal control circuits are eliminated.

[0009] In another embodiment of the present invention, a power MOSFET, a second MOSFET that is a reduced scale replica of the power MOSFET, and a logic and control circuit are coupled and contained within a common housing. The drain current in the second MOSFET is a fraction of the power MOSFET drain current. The logic circuit is capable of comparing the second MOSFET drain current with a presettable maximum value and switching both MOSFETs into a current blocking state whenever the second MOSFET drain current exceeds the presettable maximum. The circuit enters a pulse gate modulation (PG) mode where initially both MOSFETs are switched into and held in a current blocking state for a period of time. At the end of this time period, a ramp voltage is applied gate-to-source to switch both MOSFETs back into a current conducting state in a timely fashion. The ramp voltage ensures the MOSFETs do not exceed maximum current limits even in the presence of a large capacitive load. If the second MOSFET drain current exceeds the presettable maximum during ramp voltage application, both MOSFETs will again be switched off and PG mode of operation will repeat. Normal operation will then ensue when drain current remains below the presettable maximum. The combination of off time and maximum power MOSFET drain current established in the PG mode thus ensures operation of the power MOSFET below maximum power dissipation limits. Furthermore, in the present embodiment, the logic and control circuit will switch both MOSFETs into a current blocking state whenever the input power source voltage falls below a predetermined and settable value.

[0010] Another embodiment of the present invention limits the drain current in a hybrid power MOSFET circuit by using negative feedback to stabilize the ratio of power MOSFET drain current to a scaled replica MOSFET drain current, establishing an upper limit on the replica MOSFET drain current in terms of the upper limit on the power MOSFET drain current, and switching both MOSFETs into a non-conducting state whenever the upper limit on the replica MOSFET drain current is exceeded. The circuit enters a pulse gate modulation (PG) mode where both MOSFETs are initially switched into and held in a non-current conducting state for a period of time. At the end of the time period, a ramp voltage developed by a voltage doubler circuit is applied gate-to-source to switch both MOSFETs back into a current conducting state in a short time period. The ramp voltage ensures the MOSFETs do not exceed maximum current limits even in the presence of a large capacitive load. If the replica MOSFET drain current exceeds the presettable maximum during ramp voltage application, both MOSFETs will again be switched into a non-current conducting state and PG mode of operation will repeat. Normal operation will then ensue as drain current falls below maximum limits. In the current conducting state, the operating point of the power MOSFET is in the linear region of its output characteristic curves. In the non-current conducting state, the operating point of the power MOSFET is held along a line indicating zero drain current as located on the output characteristic curves. Switching the power MOSFET between these two operating points using PG, ensures operation of the power MOSFET below its maximum power dissipation limits.

[0011] It is to be appreciated that other embodiments of the present invention may be implemented by using junction field effect transistors (JFET) and/or bipolar junction transistors (BJT), either alone or in combination with MOSFETS.

[0012] FIG. 1 is a plot of output characteristic curves for a typical Field Effect Transistor (FET) illustrating the linear operating region and maximum power dissipation limits for the FET.

[0013] FIG. 2 is one embodiment of a semiconductor switching circuit with over current protection according to the present invention.

[0014] FIG. 3 is one embodiment of a semiconductor switching circuit with over current protection contained within an S08 housing according to the present invention.

[0015] FIG. 4 is one embodiment of a bonding diagram for the two chips used in the semiconductor switching circuit with over current protection according to the present invention.

[0016] FIG. 5 is a circuit block diagram of the semiconductor switching circuit with over current protection according to the present invention.

[0017] FIG. 6 is a waveform of drain current in the power MOSFET under the control of pulse gate (PG) action according to the present invention.

[0018] FIGS. 7A and 7B are flow charts 700 showing operational steps executed by the logic and PG circuits according to the present invention.

[0019] In the following detailed description of the present invention, a novel current limiting technique for hybrid power MOSFET circuits, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one skilled in the art that the present invention may be practiced without these specific details. In other instances well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

[0020] FIG. 1 is a family of output characteristic curves 100 plotted as drain current (I_D) 110 versus drain to source voltage (V_DS) 120 for a typical Field Effect Transistor (FET). Each curve is for a given value of gate-to-source voltage (V_GS) 130. A dashed curve 140 shows maximum power dissipation limits for this FET. An operating point such as 170, (I_D2, V_DS2), located to the right of the maximum power dissipation curve, illustrates operation of the FET beyond its rated power dissipation limits.

[0021] One of the characteristic curves in FIG. 1 follows a path 155 between the origin 105 and an operating point 150, (I_D1, V_DS1). In a current conducting state, operating points for the FET may be located along this path, which is in the linear region of operation. It is important to note that power dissipation in the FET at any operating point along this path between the origin 105 and operating point 180 is below maximum power dissipation limits. When in a current blocking state, any operating point for the FET such as 160 must be located along the horizontal V_DSaxis 120 where I_Dapproaches zero. In a current blocking state, power dissipation in the FET also approaches zero.

[0022] FIG. 2 is one embodiment of a semiconductor switching circuit with over current protection 200 according to the present invention. In this implementation, the switching circuit is contained within a housing 210, and is used in this embodiment to couple a power source to a load. An input power source is connected between the circuit IN 220 and a common ground, GND, 235. A logic input level connected to ON-BAR 222 is used as the signal to switch the circuit on or off. An external resistor 228 connected between IN 220 and FAULT-BAR 221 provides a logic signal that goes to a low state whenever the circuit is in PG mode. A second external resistor 227 connected between GND 235 and SET 223 is used to set the current limit above which the power MOSFET is switched into a non-current conducting state. An external capacitor 226 is connected between IN 220 and the common ground 235 to filter and smooth the input power source voltage. The load consists of a parallel coupling of capacitor 237 and resistance 236 connected between OUT 230 and the common ground 235.

[0023] FIG. 3 is one embodiment 300 of a semiconductor switching circuit with over current protection contained within an S08 housing 310 according to the present invention. The eight pins on the S08 package are referred to with the same numbers used in FIG. 2. An input power source is connected between the circuit IN 220 and a common ground, GND, 235. A logic input level connected to ON-BAR 222 is used as the signal to switch the circuit on or off. FAULT-BAR 221 provides a logic signal output that goes to a low state whenever the circuit is in PG mode. SET 223 is used to connect an external resistance for setting the current limit above which the power MOSFET is switched into a non-current conducting state. OUT 230 and the common ground 235 are pins between which any load is connected.

[0024] FIG. 4 is one embodiment of a bonding diagram 400 for the two chips contained within a single housing and used in the semiconductor switching circuit with over current protection according to the present invention. The external pin numbers correspond to those used with the S08 package in FIG. 3 as previously discussed. The power MOSFET and the replica power MOSFET are disposed on the first semiconductor chip 410. The drain of the power MOSFET is coupled to OUT 230. The source of the power MOSFET is coupled to the source of the replica MOSFET that is then coupled to IN 220. The gate of the power MOSFET is coupled to the gate of the replica MOSFET 402 which is then coupled to the logic and PG semiconductor chip 420. The connection 403 between V_DDand the logic and PG chip is used by the logic circuit to detect an input voltage below an established minimum level, and switch the circuit into a shutdown mode. Connections 404 and 405 couple the MOSFET drains to the current sensing circuit on the logic and PG chip. SET 223, FAULT-BAR 221, ON-BAR 222 and GND 235 have functions as previously described and are coupled directly to the logic and PG chip accordingly.

[0025] FIG. 5 is a block diagram 500 of the semiconductor switching circuit with over current protection according to the present invention. A dashed line encloses the first semiconductor chip 501, and a second dashed line encloses the second semiconductor chip 502 forming the switching circuit. The two chips are coupled and contained within a common housing such as an S08 package. The dashed line 503 encloses an external sense resistor 530, used as a current sensor and a resistance 535 representing an external load.

[0026] The six external connections to the circuit are as discussed previously in FIGS. 2, 3 and 4, and are identified as IN 220, FAULT-BAR 221, ON-BAR 222, SET 223, OUT 230 and GND 235.

[0027] The semiconductor chip 501 consists of a power MOSFET 505 and a replica MOSFET 510 that is a scaled down version of the power MOSFET. In the present embodiment, the scale factor is one thousand to one (1000:1). The gate leads of the two MOSFETs are coupled 511, and the power MOSFET drain current will then be one thousand times greater than the replica MOSFET drain current.

[0028] A coupling 552 connects the source lead of the replica MOSFET 510 in chip 501 with the drain lead of a current sense MOSFET 520 and the positive input of a difference amplifier 522 in chip 502. A second coupling 553 connects the source lead of the power MOSFET 505 in chip 501 to the negative input of the difference amplifier 522 in chip 502. The output of the difference amplifier 522 is connected to the gate lead of the current sense MOSFET 520. These connections form a closed loop, negative feedback path that will maintain the ratio of power MOSFET drain current to replica MOSFET drain current at a constant value.

[0029] The source lead of the current sense MOSFET 520 is connected to the SET pin 223, and the current sensing resistance 530 is connected between the SET pin 223 and GND 235. A current path is thus established between IN 220, through the replica MOSFET 510, through the current sense MOSFET 520, and through the current sensing resistance 530 to GND 235. In the present embodiment, the current in this path is 1/1000 the load current passing from IN 220, through the power MOSFET 505, through OUT 230 and through the resistive load 535 to GND 235. The quotient taken as the established trip voltage level, referred to as V_REF, divided by the maximum allowable drain current in the replica MOSFET will determine a proper choice of value for the current sensing resistance 530. As power MOSFET drain current increases, the voltage at SET 223 will increase, and when the power MOSFET drain current becomes equal to its maximum allowable level, the voltage at SET 223 will equal the trip value V_REF.

[0030] The voltage level at SET 223 is coupled to the positive input of a difference amplifier 524, the negative input of which is coupled to an internally generated reference voltage 526 equal to V_REF. When the voltage level at SET 223 equals or exceeds V_REF, the output of the difference amplifier 524 that is coupled to the Logic and PG circuit 528, will cause the switching circuit to enter the PG mode of operation.

[0031] The coupling 551 connects the two coupled gate leads 511 in chip 501 to the logic and PG mode circuit 528 in chip 502. The PG mode of operation is initiated by a signal generated in the Logic and PG mode circuit 528 and applied to the two coupled gate leads 511 to switch MOSFET 505 and MOSFET 510 into current blocking states. The PG mode circuit holds both MOSFETs in a current blocking state for a given period of time, and then applies a ramp voltage to the MOSFET gates 511 to switch them back into a current conducting state. A ramp voltage is used to switch the MOSFETs into a current conducting state for a controlled time period in order to avoid exceeding MOSFET drain current limits that might be caused by a large capacitive load. One additional coupling 550 connects the input DC power source between semiconductor chip 501 and semiconductor chip 502.

[0032] Referring again to FIG. 1, the power MOSFET will have two quasi-stable operating points in the PG mode of operation. The first operating point is located along the line indicating zero drain current such as 160 when the MOSFET is in a current blocking state. The second operating point establishes an upper limit on power MOSFET drain current, and might be selected at a point close to but not greater than the drain current at operating point 160. In the PG mode of operation, the power MOSFPT is switched alternately between these two operating points. A value of maximum power MOSFET drain current is combined with PG mode switching frequency such that average power dissipated in the power MOSFET is below maximum limits.

[0033] In normal operation, the power MOSFET is in a current conducting state and a stable operating point dependent on the attached load is located such as Q₁150 (I_D1, V_DS) illustrated in FIG. 1.

[0034] FIG. 6 is a waveform 600 of drain current in the power MOSFET under the control of pulsed gate (PG) mode operation according to the present invention. The vertical axis 601 is drain current and the horizontal axis 602 is time. The maximum level of power MOSFET drain current 603 along with a typical operating level of drain current 604 below the maximum level is plotted on the vertical scale. Operation of the switching circuit begins at the origin 605, and the drain current increases in a short time period along curve segment 606 to a level 604. The power MOSFET drain current at level 604 is below the maximum limit and normal operation continues.

[0035] At point 607, an increase in drain current begins along curve segment 610 until reaching point 620. At point 620, drain current reaches the established maximum level and the circuit switches into a two-step PG mode of operation. In the first step, beginning at point 620, the power MOSFET is switched into a current blocking state for a delay time period lasting until point 621. The second step begins at this time, when a ramp voltage is applied to the gate lead of the power MOSFET to switch it back into a current conducting state over a controlled time period. The power MOSFET drain current increases along the curve segment 622. However, at point 630, the power MOSFET drain current again reaches the established maximum level and the circuit enters into a second two-step PG mode of operation between points 630 and 640. Additional two-step PG modes will continue until the load is adjusted such that the power MOSFET drain current is maintained below the maximum level.

[0036] A following two-step PG mode begins at point 650 with delay time lasting until point 651. In the second step beginning at point 651, the drain current begins to ramp up along the curve segment 652. The drain current stabilizes according to the existing load at a level 656 below maximum limits and normal operation follows.

[0037] It is to be noted that the two-step PG mode of operation can be described in terms of two time periods. The first time period is a delay time such as between points 620 and 621. The second time period is the ramp voltage time such as between points 621 and 630. Timing circuits within the logic and PG mode circuitry establish time values for delay time and ramp voltage time. The PG mode time period is the sum of the delay time added to the ramp voltage time, such as between 630 and 640. The frequency of operation in the PG mode is taken as the reciprocal of the PG mode time period.

[0038] Even though the instantaneous power dissipated in the power MOSFET may momentarily exceed maximum limits during switching transients, the PG mode of operation is designed such that the average power dissipated in the power MOSFET is below maximum limits. That is to say, a value of maximum power MOSFET drain current is combined with PG mode such that the average power dissipated in the power MOSFET is below maximum limits.

[0039] FIGS. 7A and 7B are flow charts 700 showing the steps executed by the logic and PG mode circuits according to the present invention. In step 710, the flow chart in FIG. 7A is activated upon application of external power. Step 720 compares the voltage level of the applied external power with an internally stored minimum value. If the external power voltage level is above the minimum value, the flow chart advances to step 730 where the logic and PG mode circuits are enabled. Operation then continues around the loop defined by steps 720 and 730 to provide a continuous check on the external power voltage level. This operational loop continues as long as external power is applied and the voltage level of the external power is above the minimum value. If the external power voltage level falls below the minimum value in step 720, the flow chart advances to step 740 in which the logic and PG mode circuits are disabled.

[0040] The flow chart in FIG. 7B is operational only when the logic and PG mode circuits are enabled in step 730 of the flow chart of FIG. 7A. Step 750 in FIG. 7B commences operation of this flow chart when the logic and PG mode circuits are enabled and the operational signal ON-BAR is activated. The flow chart then enters step 760 in which the power MOSFET and the replica MOSFET are both switched into current conducting states. The current in the power MOSFET increases according to the attached load, and the current in the replica MOSFET tracks accordingly. The flow chart advances to step 770 where the voltage across the external sense resistance V_SETis compared with the reference trip voltage V_REF. As long as V_SETremains less than V_REF, the power MOSFET current is known to be below maximum limits. The flow chart returns to step 760 and continues to track the load current. The loop defined by steps 760 and 770 illustrate the normal mode of operation for this switching circuit where the load current may vary, but always remains within maximum operating limits.

[0041] Continuing with the flow chart in FIG. 7B, if V_SETis found to be greater than V_REFin step 770, the flow chart will advance to step 780. The first step in the PG mode of operation is step 780, in which both the power MOSFET and the replica MOSFET are switched into a current blocking state for a time period equal to the established delay time. After the delay time has elapsed, the flow chart advances to step 790 in which a ramp voltage is applied to the gates of the power MOSFET and the replica MOSFET to switch them into a current conducting state in a preset period of time. The flow chart then advances to step 770 in which the sense voltage V_SETis compared with the reference trip voltage V_REF. As long as V_SETis found to be greater than V_REFin step 770, the circuit will remain in the PG mode of operation by advancing around the loop consisting of steps 770, 780 and 790. Whenever V_SETbecomes less than V_REFin step 770, the flow chart will return to step 760 and normal operation will continue around loop 760 and 770 as long as the power MOSFET current remains below maximum limits.

[0042] It is to be appreciated that other embodiments of the present invention may be implemented by using junction field effect transistors (JFET) and/or bipolar junction transistors (BJT), either alone or in combination with MOSFETs. In the embodiment of the present invention illustrated in FIG. 5, the MOSFETs 505, 510 and 520 are all n-channel devices. Another embodiment of the present invention may be implemented by replacing these MOSFETs with p-channel devices, in which case a charge pump could be included.

[0043] The preferred embodiment of the present invention, a novel current limiting technique for hybrid power MOSFET circuits, is thus described. While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as limited by such embodiments, but rather construed according to the below claims.