Method and apparatus of Reed-Solomon encoding-decoding

[0002] The present invention pertains to a Reed-Solomon encoding device and method and a Reed-Solomon decoding device and method for use as error correction codes of recording media and digital transmission.

[0003] Reed-Solomon codes (hereinafter referred to as RS codes) have high encoding efficiency and are very effective in eliminating burst errors. Consequently, they are mainly used as outside codes of recording media and digital transmission. Also, with advancements in IC technology, it has become possible to fabricate encoding/decoding ICs as single chips corresponding to codes with a relatively high correction power for 8-byte or higher correction. As a result, its application range has expanded rapidly.

[0004] RS codes are characterized by a very high degree of design flexibility pertaining to the forming method of encoding. For example, even for a Galois field GF(2^m) that is frequently used in RS codes, usually, as a condition of its field formation polynomial, the period should be 2m−1. Consequently, there exist various types. In addition, there is a wide range for selecting the roots of the code forming polynomial that realizes the same correction power. That is, if the root of the field formation polynomial is α, then as a condition for realizing a correction of t bytes, the root of the code forming polynomial can be selected from a group of at least 2t consecutive powers of α, that is, (α^b, α^b+1, α^b+2, . . . α^b+2t−1). Here, b may be any integer. Consequently, there exists a significant number of different RS codes for the same t-byte correction.

[0005] From the standpoint of system development, such design flexibility is desirable. However, from the standpoint of standardization, this is undesirable. The requirement for correction power, etc., usually dictates the need for a Galois field GF(2⁸) with 2⁸elements. However, there are various other parameters. The code length and correction power, of course, depend on the specific requirements. Among the trivial differences, the greatest influence is the difference in the field formation polynomial. For example, if RS encoding/decoding devices are formed to correspond to two systems and the field formation polynomials are different, then the multipliers of their Galois fields will also be different. Consequently, compatibility is impossible. In particular, when efforts are made to correspond to that which has a higher correction power, the proportion of the multiplier of the aforementioned Galois field in the circuit scale becomes larger. In the prior art, one must prepare multipliers of Galois fields corresponding to the two systems. This leads to an increase in the cost of the device.

[0006] In practice, even in the same digital transmission field, the field formation polynomial used in satellite communications and those used in satellite broadcasting are different. This is mainly because standardization is difficult due to differences in jurisdiction between the communication field and the broadcasting field. Also, when the aforementioned standards were set up, there was little need for a common field formation polynomial.

[0007] In recent years, however, during discussions regarding the unification of communication and broadcasting, the aforementioned need became clearer. However, it is very hard to make changes to realize complete standardization. Also, for the RS codes adopted for recording media, manufacturers usually lead the development, and in few cases is the same field formation polynomial adopted for recording media developed by different manufacturers.

[0008] FIG. 11 is a schematic diagram illustrating a conventional RS encoding/decoding device handling two or more RS codes, that is, for handling RS_acode, RS_bcode, . . . RS_xcode. It has multipliers (10a)-(10x) of Galois fields GF_a(2^m), GF_b(2^m), . . . GF_x(2^m) corresponding to field formation polynomials, respectively, and multiplication coefficient memory units (11a)-(11x) that store a collection of multiplication coefficients of Galois fields {α_a[l]}, {β_b[l]}, . . . {χ_x[k]}, corresponding to the code forming polynomials, respectively. The conventional RS encoding/decoding device also has inverse element arithmetic circuits 12a-12xcorresponding to the codes for division.

[0009] In the following, in order to simplify the explanation, conventional RS encoding/decoding device 1 that handles two RS codes, that is, RS_acode and RS_bcode will be used. Here, for both RS_acode and RS_bcode, the correction power corresponds to a correction of t bytes.

[0010] FIG. 12 is a diagram illustrating surplus arithmetic circuit 202 that forms conventional RS encoding/decoding device 1. In surplus arithmetic circuit 202, collection of multiplication coefficients of Galois fields {α_ao[i]}, i=0-L is contained in said collection of multiplication coefficients of Galois fields {α_a[i]}, and collection of multiplication coefficients of Galois fields {β_be[j]}, j=0-L is contained in said collection of multiplication coefficients of Galois fields {β_b[j]}. Here, L is 2t−1 or 2t (same in the following).

[0011] As shown in FIG. 12, surplus arithmetic circuit 202 of the polynomial has multipliers 203-0˜203-L, multipliers 208-0˜208-L, switches 204-0˜204-L, registers 205-0˜205-L, adders 206-1˜206-L, and adder 207.

[0012] Switches 204-0˜204-L select multipliers 203-0˜203-L in the case of RS_aencoding and multipliers 208-0˜208-L in the case of RS_bencoding.

[0013] Usually, RS decoding device is composed of syndrome arithmetic circuit, error location polynomial and evaluation polynomial arithmetic circuit, error location detecting circuit, evaluation value detecting circuit, and correction execution circuit. Of those, for said error location polynomial arithmetic circuit and evaluation polynomial arithmetic circuit, the known methods include the Euclidean algorithm method and the Barlekamp-Massey method.

[0014] FIG. 13 is a diagram illustrating a conventional constitutional example of syndrome arithmetic circuit 209 corresponding to said two RS codes. Here, the collection of multiplication coefficients of Galois fields {α_as[i]}, i=0-L is contained in said {α_a[i]}, and the collection of multiplication coefficients of Galois fields {β_bs[j]}, j=0-L is contained in said {β_b[j]}.

[0015] As shown in FIG. 13, syndrome arithmetic circuit 209 has multipliers 213-0˜213-L, switches 214-0˜214-L, registers 215-0˜215-L, adders 216-0˜216-L, and multipliers 217-0˜217-L.

[0016] Switches 214-0˜214-L select multipliers 213-0˜213-L in the case of RS_aencoding and multipliers 217-0˜217-L in the case of RS_bencoding.

[0017] FIG. 14 is a diagram illustrating an example of the conventional constitution of polynomial division circuit 221, one of the major elements of the error location polynomial and evaluation polynomial arithmetic circuit, corresponding to said two RS codes.

[0018] As shown in FIG. 14, polynomial division circuit 221 has switches 222-0˜222-L, multipliers 223-0˜223-L, multipliers 228-0˜228-L, registers 225-0˜225-L, registers 224-0˜224-L, adders 226-0˜226-L, registers 227, 229, inverse element arithmetic circuits 231, 232, multipliers 230, 231, and switch 234.

[0019] Switches 222-0˜222-L select multipliers 223-0˜223-L in the case of RS_aencoding and multipliers 228-0˜228-L in the case of RS_bencoding. Also, switch 234 selects multiplier 230 in the case of RS_aencoding and multiplier 231 in the case of RS_bencoding.

[0020] FIG. 15 is a diagram illustrating an example of the conventional constitution of polynomial multiplier 241, a major element of error location polynomial and evaluation polynomial arithmetic circuit, corresponding to said two RS codes.

[0021] As shown in FIG. 15, polynomial multiplier 241 has multipliers 243-0˜243-L, multipliers 248-0˜248-L, switches 242-0˜242-L, registers 245-0˜245-L, adders 246-1˜246-L, and registers 247-0˜247-L.

[0022] Switches 242-0˜242-L select multipliers 243-0˜243-L in the case of RS_aencoding and multipliers 248-0˜248-L in the case of RS_bencoding.

[0023] FIG. 16 is a diagram illustrating an example of the conventional constitution of error location detecting circuit 251 corresponding to said two RS codes.

[0024] As shown in FIG. 16, error location detecting circuit 251 has multipliers 252-0˜252-n, multipliers 258-0˜258-n, switches 252-0˜252-n, registers 255-0˜255-n, adders 256-1˜256-n0, and detecting circuit 257.

[0025] Switches 252-0˜252-n select multipliers 252-0˜252-n in the case of RS_aencoding and multipliers 258-0˜258-n in the case of RS_bencoding.

[0026] Here, the collection of multiplication coefficients of Galois fields {α_ac[i]}, i=0˜n=t is contained in said {α_a[i]}, and the collection of multiplication coefficients of Galois fields {β_bc[j]}, j=0˜n=t is contained in said {β_b[j]}. When erasure-and-error correction is carried out, one has I=0˜n=2t, j=0˜n=2t.

[0027] FIG. 17 is a diagram illustrating an example of the conventional constitution of evaluation value detecting circuit 261 corresponding to said two RS codes.

[0028] As shown in FIG. 17, evaluation value detecting circuit 261 has multipliers 262-0˜262-(n−1), multipliers 267-0˜267-(n−1), switches 262-0˜262-(n−1), registers 265-0˜265-(n−1), and adders 266-1˜266-(n−1).

[0029] Switches 262-0˜262-(n−1) select multipliers 262-0˜262-(n−1) in the case of RS_aencoding and multipliers 267-0˜267-(n−1) in the case of RS_bencoding.

[0030] Here, the collection of multiplication coefficients of Galois fields {α_av[i]}, i=0˜n−1 is contained in said {α_a[i]}, and the collection of multiplication coefficients of Galois fields {β_bv[j]}, j=0˜n−1 is contained in said {β_b[j]}.

[0031] In this way, in the conventional constitution of RS encoding/decoding device for handling two or more RS codes, it is necessary to have multipliers and inverse element arithmetic circuits corresponding to the respective field formation polynomials, and to be able to switch between them.

[0032] Also, in the aforementioned constitution, when changes takes place in the Galois field of the encoding target data and decoding target data, it is necessary to change the hardware constitution. As a result, it is impossible to handle diverse types of Galois field data encoding/decoding in a flexible way, which is undesirable.

[0033] The purpose of the present invention is to solve the aforementioned problems of the conventional methods by providing a Reed-Solomon encoding device and method that can reduce the scale of the device and can decrease the cost of the device.

[0034] Another purpose of the present invention is to provide a Reed-Solomon encoding device and method that can perform diversified Galois field data encoding in a flexible way.

[0035] Yet another purpose of the present invention is to provide a Reed-Solomon decoding method and device that can reduce the scale and cost of the device.

[0036] Yet another purpose of the present invention is to provide a Reed-Solomon decoding device and method that can perform diversified Galois field data decoding in a flexible way.

[0037] In order to solve the aforementioned problems and to realize the aforementioned purposes, the present invention provides a type of Reed-Solomon encoding device characterized by the fact that the Reed-Solomon encoding device that handles multiple RS (Reed-Solomon) codes by means of different field formation polynomials has the following means: a first Galois field transformation means that transforms the input encoding target data into data of a prescribed Galois field on the basis of the input first Galois field transformation parameter, an encoding means that performs encoding processing by means of said transformed Galois field for said transformed encoding target data, a second Galois field transformation means that inverse transforms said encoded data into data of said Galois field before transformation on the basis of input second Galois field transformation parameter, and a parameter output means that outputs said first Galois field transformation parameter and said second Galois field transformation parameter.

[0038] In the Reed-Solomon encoding device of the present invention, a first Galois field transformation means and a second Galois field transformation means are used. For any of multiple RS codes, encoding processing is performed using a prescribed Galois field in the encoding means. As a result, there is no need to use multiplier and inverse element arithmetic units to correspond to each of multiple RS codes separately in the encoding means, so that the circuit scale can be reduced significantly.

[0039] Also, because said first Galois field transformation means and second Galois field transformation means perform Galois field transformation on the basis of the first Galois field transformation parameter and second Galois field transformation parameter output from the parameter output means, respectively, it is possible to make diversified and flexible changes for the contents of the Galois field transformation.

[0040] For the Reed-Solomon encoding device of the present invention, it is preferred that said encoding means have a multiplier corresponding to said transformed Galois field.

[0041] Also, the Reed-Solomon encoding device of the present invention preferably has the following features: said multiple RS codes are RS_acodes and RS_bcodes using different field formation polynomials; the encoding symbols are Galois fields GF_a(2^m) and GF_b(2^m) extended on the basis of different mth field formation polynomials Gp_a(x) and Gp_b(x) on Galois field GF(2), respectively; for α, which is a root of said Gp_a(x) and a primitive element of said GF_a(2^m), and β, which is a root of said Gp_b(x) and a primitive element of said GF_b(2^m), following Equation (25) is established; said RS_bcode is a t-symbol correction code, and its code forming polynomial G_cb(x) is represented by following Equation (26); when said input encoding target data is encoded by means of said RS_bcode, said first Galois field transformation means transforms said input encoding target data from said Galois field GF_b(2^m) into data of said Galois field GF_a(2^m); said encoding means performs encoding corresponding to following Equation (27), which is the polynomial transforming said code forming polynomial G_cb(x) into said Galois field GF_a(2^m); and said second Galois field transformation means inverse-transforms said encoded data from said Galois field GF_a(2^m) into data of said Galois field GF_b(2^m). $\begin{array}{cc}{\mathrm{Gp}}_b\left({\alpha }^p\right)=0& \mathrm{Equation}25\end{array}$ $\begin{array}{cc}{\mathrm{Gc}}_b\left(x\right)=\prod _{j=0}^L\left(x+{\beta }^{q\left(b+j\right)}\right),L=2t-1,\mathrm{or}2t& \mathrm{Equation}26\end{array}$ $\begin{array}{cc}{\mathrm{Gc}}_{\mathrm{ba}}\left(x\right)=\prod _{j=0}^L\left(x+{\alpha }^{\mathrm{pq}\left(b+j\right)}\right),L=2t-1,\mathrm{or}2t.& \mathrm{Equation}27\end{array}$

[0042] Also, the Reed-Solomon encoding device of the present invention is preferably characterized by the following features: for said first Galois field transformation means, when m of the 2^minput/output relationships are represented by a transposed matrix ( . . . )^T, with respect to m-bit input (00 . . . 0001)^T, m-bit output A₁=(00 . . . 001)^Tis performed; with respect to m-bit input (00 . . . 0010)^T, m-bit output A₁=(A_1,m−1, A_1,m−2, . . . A_1,0)^Tis performed; with respect to m-bit input (00 . . . 0100)^T, m-bit output A₂=(A_2,m−1, A_2,m−2, . . . A_2,0)^Tis performed; with respect to m-bit input (01 . . . 0000)^T, m-bit output A_m−2=(A_m−2,m−1, A_m−2,m−2, . . . A_m−2,0)^Tis performed; with respect to m-bit input (10 . . . 0000)^T, m-bit output A_m−1=(A_m−1,m−1, A_m−1,m−2, . . . A_m−1,0)^Tis performed; when m×m matrix [H_ba] is defined by following Equation (28), with respect to said m-bit input data D_b-in, arithmetic operation is performed according to following Equation (29) to form m-bit output data D_a-out. $\begin{array}{cc}\left[H_{\mathrm{ba}}\right]=\left(A_{m-1}{A}_{m-2}\dots A_2{A}_1{A}_0\right)& \mathrm{Equation}28\end{array}$ $\begin{array}{cc}{D}_{a\text{-}\mathrm{out}}=\left[H_{\mathrm{ba}}\right]\times D_{b\text{-}\mathrm{in}}.& \mathrm{Equation}29\end{array}$

[0043] Also, for the Reed-Solomon encoding device, it is preferred that said parameter output means outputs said matrix [H_ba] as said first Galois field transformation parameter to said first Galois field transformation means.

[0044] Also, the Reed-Solomon encoding device of the present invention preferably has the following features: said parameter output means outputs rows of said matrix [H_ba] as said first Galois field transformation parameter to the first Galois field transformation means in the order of rows; said first Galois field transformation means has the following means: multiple AND operation means corresponding in number to said bit data and performing the following operation: inputting from the first input terminal the bit data corresponding to the rows of said matrix [H_ba] input as said first Galois field transformation parameter, inputting from the second input terminal the corresponding bit data of said input encoding target data, and performing a logical AND operation on said bit data input from the first input terminal and said bit data input from the second input terminal; and an exclusive-OR operation means that operates to get exclusive-OR of the operation results of said multiple AND operation means.

[0045] Also, for the Reed-Solomon encoding device of the present invention, it is preferred that when the inverse matrix of said matrix [H_ba] is taken as [H_ab], said second Galois field transformation means perform arithmetic operation according to following Equation (30) to form m-bit output data D_b-out. $\begin{array}{cc}{D}_{b\text{-}\mathrm{out}}=\left[H_{\mathrm{ab}}\right]\times D_{a\text{-}\mathrm{in}}& \mathrm{Equation}30\end{array}$

[0046] Also, for the Reed-Solomon encoding device of the present invention, it is preferred that said parameter output means output said matrix [H_ab] as said second Galois field transformation parameter to said second Galois field transformation means.

[0047] Also, the Reed-Solomon encoding device preferably has the following features: said parameter output means outputs rows of said matrix [H_ab] as said second Galois field transformation parameter to the second Galois field transformation means in the order of rows; said second Galois field transformation means has the following means: multiple AND operation means corresponding in number to said bit data and performing the following operation: input from the first inputting terminal the bit data corresponding to rows of said matrix [H_ab] input as said second Galois field transformation parameter, inputting from the second input terminal the corresponding bit data of said encoded data, and performing a logical AND operation on said bit data input from the first input terminal and said bit data input from the second input terminal; and an exclusive-OR operation means that performs an exclusive-OR operation on the results of said multiple AND operations.

[0048] Also, it is preferred that the Reed-Solomon encoding device of the present invention also includes a multiplication coefficient memory means, and that said parameter output means sends the multiplication coefficients stored in said multiplication coefficient memory means to said multiplier.

[0049] Also, the present invention provides a type of Reed-Solomon decoding device characterized by the fact that the Reed-Solomon decoding device that corresponds to multiple RS codes by means of different field formation polynomials comprises the following means: a first Galois field transformation means that transforms the input decoding target data into prescribed Galois field data on the basis of the first input Galois field transformation parameters, a decoding means that performs the decoding process by means of said transformed Galois field for said transformed decoding target data, a second Galois field transformation means that inverse-transforms said decoded data into said Galois field data before transformation on the basis of the second input Galois field transformation parameters, and a parameter output means that outputs said first Galois field transformation parameter and said second Galois field transformation parameter.

[0050] In the Reed-Solomon decoding device of the present invention, a first Galois field transformation means and a second Galois field transformation means are arranged. For any of multiple RS codes, decoding processing is performed using a prescribed Galois field in the decoding means. As a result, there is no need to use multiplier and inverse element arithmetic unit to correspond to each of the multiple RS codes separately in the decoding means, so that the circuit scale can be reduced significantly.

[0051] Also, because said first Galois field transformation means and second Galois field transformation means perform Galois field transformation on the basis of the first Galois field transformation parameters and second Galois field transformation parameters output from the parameter output means, respectively, it is possible to make diverse and flexible changes for the contents of the Galois field transformation.

[0052] For the Reed-Solomon decoding device of the present invention, it is preferred that said decoding means have a multiplier corresponding to said transformed Galois field.

[0053] Also, the Reed-Solomon decoding device of the present invention preferably has the following features: said multiple RS codes are RS_acodes and RS_bcodes using different field formation polynomials; the encoding symbols are Galois fields GF_a(2^m) and GF_b(2^m) extended on the basis of the different mth field formation polynomials Gp_a(x) and GP_b(x) on Galois field GF(2), respectively; with respect to α, which is a root of said Gp_a(x) and a primitive element of said GF_a(2^m), and β, which is a root of said Gp_b(x) and a primitive element of said GF_b(2^m), the following Equation (31) is established; said RS_bcode is a t-symbol correction code, and its code forming polynomial G_cb(x) is represented by following Equation (32); when said input decoding target data is decoded, said first Galois field transformation means transforms said decoding target data from said Galois field GF_b(2^m) into data of said Galois field GF_a(2^m); said decoding means performs decoding corresponding to the following Equation (33) that is the polynomial transforming said code forming polynomial G_cb(x) into said Galois field GF_a(2m); and said second Galois field transformation means transforms said decoded data from said Galois field GF_a(2^m) into data of said Galois field GF_b(2^m). $\begin{array}{cc}{\mathrm{Gp}}_b\left({\alpha }^p\right)=0& \mathrm{Equation}31\end{array}$ $\begin{array}{cc}{\mathrm{Gc}}_b\left(x\right)=\prod _{j=0}^L\left(x+{\beta }^{q\left(b+j\right)}\right),L=2t-1,\mathrm{or}2t& \mathrm{Equation}32\end{array}$ $\begin{array}{cc}{\mathrm{Gc}}_{\mathrm{ba}}\left(x\right)=\prod _{j=0}^L\left(x+{\alpha }^{\mathrm{pq}\left(b+j\right)}\right),L=2t-1,\mathrm{or}2t& \mathrm{Equation}33\end{array}$

[0054] Also, the Reed-Solomon decoding device of the present invention preferably has the following features: for said first Galois field transformation means, when m of the 2^minput/output relationships are represented by a transposed matrix ( . . . )^T, with respect to m-bit input (00 . . . 0001)^T, m-bit output A₁=(00 . . . 001)^Tis performed; with respect to m-bit input (00 . . . 0010)^T, m-bit output A₁=(A_1,m−1, A_1,m−2, . . . A_1,0)^Tis performed; with respect to m-bit input (00 . . . 0100)^T, m-bit output A₂=(A_2,m−1, A_2,m−2, . . . A_2,0)^Tis performed; with respect to m-bit input (01 . . . 0000)^T, m-bit output A_m−2=(A_m−2,m−1, A_m−2,m−2, . . . A_m2,0)^Tis performed; with respect to m-bit input (10 . . . 0000)^T, m-bit output A_m−1=(A_m−1,m−1, A_m−1,m−2, . . . A_m−1,0)^Tis performed; when m×m matrix [H_ba] is defined by following Equation (34), with respect to said m-bit input data D_b-in, arithmetic operation is performed according to following Equation (35) to form m-bit output data D_a-out. $\begin{array}{cc}\left[H_{\mathrm{ba}}\right]=\left(A_{m-1}{A}_{m-2}\dots A_2{A}_1{A}_0\right)& \mathrm{Equation}34\end{array}$ $\begin{array}{cc}{D}_{a\text{-}\mathrm{out}}=\left[H_{\mathrm{ba}}\right]\times D_{b\text{-}\mathrm{in}}& \mathrm{Equation}35\end{array}$

[0055] Also, for the Reed-Solomon decoding device of the present invention, it is preferred that said parameter output means outputs said matrix [H_ba] as said first Galois field transformation parameters to said first Galois field transformation means.

[0056] Also, the Reed-Solomon decoding device of the present invention preferably has the following features: said parameter output means outputs rows of said matrix [H_ba] as said first Galois field transformation parameter to the first Galois field transformation means in the row order; said first Galois field transformation means comprises the following means: multiple AND operation means corresponding in number to said bit data and performing the following operation: inputting from the first input terminal the bit data corresponding to the rows of said matrix [H_ba] input as said first Galois field transformation parameter, inputting from the second input terminal the corresponding bit data of said input decoding target data, and performing a logical AND operation on said bit data input from the first input terminal and said bit data input from the second input terminal; and an exclusive-OR operation means that performs an exclusive-OR operation on the results of said multiple AND operations.

[0057] Also, for the Reed-Solomon decoding device of the present invention, it is preferred that when the inverse matrix of said matrix [H_ba] is taken as [H_ab], said second Galois field transformation means perform arithmetic operation according to following Equation (36) to form m-bit output data D_b-out. $\begin{array}{cc}{D}_{b-\mathrm{out}}=\left[H_{\mathrm{ab}}\right]\times D_{a-\mathrm{in}}& \mathrm{Equation}6\end{array}$

[0058] Also, for the Reed-Solomon decoding device of the present invention, it is preferred that said parameter output means output said matrix [H_ab] as said second Galois field transformation parameter to said second Galois field transformation means.

[0059] Also, the Reed-Solomon decoding device of the present invention preferably has the following features: said parameter output means outputs rows of said matrix [H_ab] as said second Galois field transformation parameter to the second Galois field transformation means in the order of rows; said second Galois field transformation means has the following means: multiple AND operation means corresponding in number to said bit data and performing the following operation: inputting from the first input terminal the bit data corresponding to the rows of said matrix [H_ab] input as said second Galois field transformation parameter, inputting from the second input terminal the corresponding bit data of said encoded data, and performing a logical AND operation on said bit data input from the first input terminal and said bit data input from the second input terminal; and an exclusive-OR operation means that performs an exclusive-OR operation on the results of said multiple AND operations.

[0060] Also, it is preferred that the Reed-Solomon decoding device of the present invention also comprises a multiplication coefficient memory means, and that said parameter output means send the multiplication coefficients stored in said multiplication coefficient memory means to said multiplier.

[0061] FIG. 1 is a schematic diagram illustrating the Reed-Solomon encoding/decoding device in an embodiment of the present invention.

[0062] FIG. 2 is a diagram illustrating the transformation table in the input-side transformation circuit and output-side transformation circuit shown in FIG. 1.

[0063] FIG. 3 is a diagram illustrating the constitution of the input-side transformation circuit shown in FIG. 1.

[0064] FIG. 4 is a diagram illustrating the constitution of the output-side transformation circuit shown in FIG. 1.

[0065] FIG. 5 is a diagram illustrating the constitution of the surplus arithmetic circuit used in the RS encoding core unit shown in FIG. 1.

[0066] FIG. 6 is a diagram illustrating the constitution of the syndrome arithmetic circuit used in the RS decoding core unit shown in FIG. 1.

[0067] FIG. 7 is a diagram illustrating the constitution of the division circuit used in the RS decoding core unit shown in FIG. 1.

[0068] FIG. 8 is a diagram illustrating the constitution of the multiplication circuit used in the RS decoding core unit shown in FIG. 1.

[0069] FIG. 9 is a diagram illustrating the constitution of the location detecting circuit used in the RS decoding core unit shown in FIG. 1.

[0070] FIG. 10 is a diagram illustrating the constitution of the evaluation value detecting circuit used in the RS decoding core unit shown in FIG. 1.

[0071] FIG. 11 is a schematic diagram illustrating a conventional RS encoding/decoding device.

[0072] FIG. 12 is a diagram illustrating the constitution of the surplus arithmetic circuit used in the RS encoding core unit shown in FIG. 11 of the prior art.

[0073] FIG. 13 is a diagram illustrating the constitution of the syndrome arithmetic circuit used in the RS decoding core unit shown in FIG. 11 of the prior art.

[0074] FIG. 14 is a diagram illustrating the constitution of the division circuit used in the RS decoding core unit shown in FIG. 11 of the prior art.

[0075] FIG. 15 is a diagram illustrating the constitution of the multiplication circuit used in the RS decoding core unit shown in FIG. 11 of the prior art.

[0076] FIG. 16 is a diagram illustrating the constitution of the location detecting circuit used in the RS decoding core unit shown in FIG. 11 of the prior art.

[0077] FIG. 17 is a diagram illustrating the constitution of the evaluation value detecting circuit used in the RS decoding core unit shown in FIG. 11 of the prior art.

[0078] In the figures, 101 represents a RS encoding/decoding device, 102 a surplus arithmetic circuit, 109 a syndrome arithmetic circuit, 111 a multiplication coefficient memory unit, 112 a RS encoding/decoding core unit, 113-0˜113-L a multiplier, 115 an inverse element arithmetic circuit, 119 an output-side transformation circuit, 120 a parameter setting unit, 121 a division circuit of polynomial, 141 a multiplication circuit of polynomial, 151 an error location detecting circuit, and 161 an evaluation value detecting circuit.

[0079] FIG. 1 is a schematic diagram illustrating RS encoding/decoding device 101 of the present embodiment.

[0080] RS encoding/decoding device 101 can handle two or more RS codes, that is, RS_acode, RS_bcode, . . . RS_xcode.

[0081] As shown in FIG. 1, it has the following parts: multipliers 113 of Galois fields corresponding to field formation polynomials of GF_a(2^m), multiplication coefficient memory units 111 that store collection of multiplication coefficients of Galois fields {α_a[l]}, {α_b[j]}, . . . {α_x[k]}, corresponding to code forming polynomials, respectively, RS encoding/decoding core unit 112 inverse element arithmetic circuit 115, input-side transformation circuit 116, output-side transformation circuit 119, and parameter setting unit 120.

[0082] As shown in FIG. 1, RS encoding/decoding device 101 has a constitution in which input-side transformation circuit 116 and output-side transformation circuit 119 are attached to the input side and output side of RS encoding/decoding core unit 112, respectively.

[0083] Input-side transformation circuit 116 and output-side transformation circuit 119 perform transformation of data on the basis of Galois field transformation parameters S120aand S120binput from parameter setting unit 120.

[0084] Also, RS encoding/decoding core unit 112 performs encoding and decoding on the basis of multiplication coefficient S120cinput from parameter setting unit 120.

[0085] Switching is performed for Galois field transformation parameters S120a,S120band multiplication coefficient S120coutput from parameter setting unit 120 corresponding to the types of RS encoding and RS decoding, such as instructions from the user.

[0086] In the following, in order to simplify the explanation, RS encoding/decoding device 101 will be described that handles two RS codes, that is, RS_acode and RS_bcode. Here, for both RS_acode and RS_bcode, the correction power is for correcting t bytes.

[0087] In this embodiment, as an example of the case of RS encoding and decoding when q=88 and m=8 in said Equations (25)-(30) will be examined.

[0088] In this embodiment, because the topic pertains to the encoding/decoding method and device for said RS_bcode, for said RS_acode, the only requirement is that the order of its field formation polynomial be identical to that of said RS_bcode. Also, in this embodiment, in order to simplify the explanation, it is assumed that the correction power for said RS_acode is also for correction of t bytes, same as said RS_bcode.

[0089] RS_aCode

[0090] For said RS_acode, the field formation polynomial on GF(2) that forms basic field GF_a-B(2⁸) as defined by the encoding symbol of said code is defined by following Equation (37). $\text{[Mathematical formula 37]}$ $\begin{array}{cc}{\mathrm{Gp}}_a\left(x\right)=x^8+x^4+x^3+x^2+1& \left(37\right)\end{array}$

[0091] In addition, the code forming polynomial of said RS_ais defined by following Equation (38). $\text{[Mathematical formula 38]}$ $\begin{array}{cc}{\mathrm{Gc}}_a\left(x\right)=\prod _{i=0}^L\left(x+{\alpha }^{a+1}\right),L=2t-1,21\mathrm{or}2t& 38)\end{array}$

[0092] In this case, the coefficient of x is an element of said GF_a-B(2⁸), and extended field of encoding GF_a-E(2⁸) is equal to the basic field GF_a-B(2⁸). That is, in this embodiment, said Galois field GF_a(2⁸) as target of transformation corresponds to GF_a-B(2⁸)=GF_a-E(2⁸).

[0093] Also, α is taken as a root of said Gp_a(x) and the primitive element of said GF_a(2⁸)=GF_a-B(2⁸). Here, in order to simplify the explanation, α is represented by means of a column vector (00000010)^T. Also, following Equation (39) is derived from said Equation (37). $\text{[Mathematical formula 39]}$ $\begin{array}{cc}{\alpha }^B={\alpha }^4+{\alpha }^3+{\alpha }^2+1& \left(39\right)\end{array}$

[0094] In column representation, one has (α⁸)_a=(00011101)^T. Here, (X)_ashows the column vector representation of element X of said GF_a(2⁸). Also, one has (α⁰)_a=(1)_a=(00000001)^T.

[0095] RS_bCode

[0096] For said RS_bcode, the field formation polynomial on GF(2) that forms the basic field as defined by the encoding symbol of said code is defined by following Equation (40). $\text{[Mathematical formula 40]}$ $\begin{array}{cc}{\mathrm{Gp}}_b\left(x\right)=x^B+x^5+x^3+x^2+1& \left(40\right)\end{array}$

[0097] In addition, the code forming polynomial of said RS_bcode is defined by following Equation (41). $\text{[Mathematical formula 41]}$ $\begin{array}{cc}{\mathrm{Gc}}_b\left(x\right)=\prod _{j=0}^L\left(x+{\beta }^{8B\left(b+j\right)}\right),L=2t-1,21\mathrm{or}2t& \end{array}$

[0098] Equation (41) corresponds to setting q=88 in said Equation (26). Strictly speaking, this RS code is contained in the Goppa code. Consequently, although the coefficient of x in said Equation (41) can be represented with an element of said GF_b-B(2⁸), it is still different from GF_b-B(2⁸), the basic field of the extended field GF_b-B(2⁸) of encoding. In this embodiment, said Galois field GF_b(2⁸) as target of transformation corresponds to GF_b-B(2⁸). Also, the Euclid decoding method for said Goppa code is described in “Sugiyama, Kasahara, Hirasawa: A method for solving key equation for decoding Goppa codes, Inf. and Cont., 27, 1975,” and its erasure-and-error correction method is described in “Sugiyama, Kasahara, Hirasawa, Namekawa: An erasures-and-errors decoding algorithm for Goppa codes, IEEE Trans. Inform, Theory, 1976.”

[0099] Also, β is taken as a root of said Gp_b(x) and the primitive element of said GF_b(2⁸)=GF_b-B(2⁸). Here, β is also represented by means of a column vector (00000010)^T. Also, following Equation (42) is derived from said Equation (40). $\text{[Mathematical formula 42]}$ $\begin{array}{cc}\begin{array}{c}{\beta }^8={\beta }^6+{\beta }^3+{\beta }^2+1\\ {\beta }^9=\beta \times {\beta }^8={\beta }^6+{\beta }^4+{\beta }^3+\beta \\ {\beta }^{10}=\beta \times {\beta }^9={\beta }^7+{\beta }^5+{\beta }^4+{\beta }^2\\ {\beta }^{11}=\beta \times {\beta }^{10}={\beta }^8+{\beta }^6+{\beta }^5+{\beta }^3\\ ={\beta }^5+{\beta }^3+{\beta }^2+1+{\beta }^6+{\beta }^5+{\beta }^3\\ ={\beta }^6+{\beta }^2+1\end{array}& \left(42\right)\end{array}$

[0100] In column representation, one has (β⁸)_b=(00101101)^T. Here, (X)_bshows the column vector representation of element X of said GF_b(2⁸). Also, one has (β⁰)_b=(1)_b=(00000001)^T.

[0101] For encoding of said RS_bcode, it is possible to perform transformation of the code forming polynomial while the Galois field is transformed. The transformation itself is relatively simple.

[0102] In the following, the various structural elements of RS encoding/decoding device 101 and the circuit that forms RS encoding/decoding core portion 112 will be examined.

[0103] Input-side Transformation Circuit and Output-side Transformation Circuit

[0104] For example, one can derive the relationship between α and β as follows. Gp_a(x) is a primitive polynomial on GF(2), and it has 8 roots, namely, α, α², α⁴, α⁸, α¹⁶, α³², α⁶⁴, α¹²⁸. Similarly, for primitive polynomial Gp_a-p(x) with α^Pas a root, there are a total of 8 roots, that is, in addition to α^P, there are also the following roots: α^2P, α^4P, α^8P, α^16P, α^32P, α^64P, α^128P. The following Equation (43) is established. $\text{[Mathematical formula 43]}$ $\begin{array}{cc}{\mathrm{Gp}}_{\mathrm{a\_p}}\left(x\right)=\left(x+{\alpha }^p\right)\left(x+{\alpha }^{4p}\right)\left(x+{\alpha }^{8p}\right)\dots \left(x+{\alpha }^{64p}\right)\left(x+{\alpha }^{128p}\right)& \left(43\right)\end{array}$

[0105] For said Equation (43), when p=241, following Equation (44) is established. $\text{[Mathematical formula 44]}$ $\begin{array}{cc}{\mathrm{Gp}}_{\mathrm{a\_p}}\left(x\right)={\alpha }^0{x}^8+{\alpha }^0{x}^6+{\alpha }^0{x}^3+{\alpha }^0{x}^2+{\alpha }^0& \left(44\right)\end{array}$

[0106] Here, because α⁰=1 on GF(2), the right-hand side of Equation (44) is in agreement with the right-hand side of said Equation (40). That is, said Gp_a-p(x) and said Gp_b(x) have the same roots on GF(2).

[0107] Also, when calculation is performed on said GF_a(2⁸), following Equation (45) is established. $\text{[Mathematical formula 45]}$ $\begin{array}{cc}{\mathrm{Gp}}_b\left({\alpha }^{241}\right)=0& \left(45\right)\end{array}$

[0108] In this way, α²⁴¹of said Galois field GF_a(2⁸) corresponds to β of said Galois field GF_b(2⁸). More specifically, from said Equation (45), following Equation (46) is established. $\text{[Mathematical formula 46]}$ $\begin{array}{cc}\begin{array}{c}{\left({\alpha }^{241}\right)}^8={\left({\alpha }^{241}\right)}^5+{\left({\alpha }^{241}\right)}^3+{\left({\alpha }^{241}\right)}^2+1\\ {\left({\alpha }^{241}\right)}^9={\alpha }^{241}\times {\left({\alpha }^{241}\right)}^8={\left({\alpha }^{241}\right)}^6+{\left({\alpha }^{241}\right)}^4+{\left({\alpha }^{241}\right)}^3+{\alpha }^{241}\\ {\left({\alpha }^{241}\right)}^{10}={\alpha }^{241}\times {\left({\alpha }^{241}\right)}^9={\left({\alpha }^{241}\right)}^7+{\left({\alpha }^{241}\right)}^5+{\left({\alpha }^{241}\right)}^4+\\ {\left({\alpha }^{241}\right)}^2\\ {\left({\alpha }^{241}\right)}^{11}={\alpha }^{241}\times {\left({\alpha }^{241}\right)}^{10}={\left({\alpha }^{241}\right)}^8+{\left({\alpha }^{241}\right)}^2+1\end{array}& \left(46\right)\end{array}$

[0109] On the basis of said Equation (46), if z represents any integer, it is possible to represent any element α^241Eof said Galois field GF_a(2⁸) as a linear combination of (α²⁴¹)⁷, (α²⁴¹)⁶, . . . (α²⁴¹)², α²⁴¹and 1 .

[0110] That is, in the case of the following Equation (47), the relationship of following Equation (48) is established. $\text{[Mathematical formula 47]}$ $\begin{array}{cc}{\beta }^z=\sum _{i=0}^7{B}_{z,i}{\beta }^i& \left(47\right)\end{array}$ $\text{[Mathematical formula 48]}$ $\begin{array}{cc}{\alpha }^{241z}=\sum _{i=0}^7{B}_{z,i}{\alpha }^{2411}& \left(48\right)\end{array}$

[0111] In said Equations (47) and (48), B_E,i=0 or 1.

[0112] In this way, on said Galois field GF_a(2⁸), α^241xacts as if it is β^xon Galois field GF_b(2⁸). On the other hand, β^xon said Galois field GF_b(2⁸) corresponds to α^241Bon said Galois field GF_a(2⁸).

[0113] As explained above, with input-side transformation circuit 116, which transforms from said Galois field GF_b(2⁸)=GF_b-B(2⁸) to said Galois field GF_a(2⁸)=GF_a-H(2⁸), any element β^xof GF_b(2⁸) is transformed into element α^241xof GF_a(2⁸), and 0 is transformed to 0. For the transformed series, because the calculation rule for said GF_a(2⁸) is observed, as the multiplier in the Reed-Solomon encoding/composite treatment to be explained below, it is possible to make use of that which is defined for said GF_a(2⁸). This transformation operation is specifically carried out pertaining to the respective vector representation. In input-side transformation circuit 116, the transformation represented by the transformation table shown in FIG. 2 is carried out on the basis of Galois field transformation parameter S120a.Also, in output-side transformation circuit 119, transformation represented by the transformation table shown in FIG. 2 is carried out on the basis of Galois field transformation parameter S120b.

[0114] As shown by the transformation table in FIG. 2, input-side transformation circuit 116 outputs 8-bit data corresponding to 0, 1, α²⁴¹, α^241×2, α^241×3, . . . according to the 8-bit address input corresponding to 0, 1, β¹, β², β³, . . . , respectively.

[0115] Also, for the series as a result of processing of said Galois field GF_a(2⁸), any element α^241xof GF_a(2⁸) is transformed into the series of GF_b(2⁸), and, by means of output-side transformation circuit 119 that transforms 0 to 0, it is transformed into the series of original Galois field GF_b(2⁸). As shown in FIG. 2, output-side transformation circuit 119, which transforms from said Galois field GF_a(2⁸) into said Galois field GF_b(2⁸), outputs 8-bit data corresponding to 0, 1, β¹, β², β³, . . . with respect to 8-bit address input corresponding to 0, 1, α²⁴¹, α^241×2, α^241×3, . . . on the basis of Galois field transformation parameter S120b.

[0116] Also, because the following Equation (49) is established on the basis of said Galois field GF_b(2⁸), from the essence of the constitution, one may output Galois field transformation parameters S120aand 120bcorresponding to the transformation table shown in FIG. 2 from parameter setting unit 120. $\text{[Mathematical formula 49]}$ $\begin{array}{cc}{\mathrm{Gp}}_a\left({\beta }^{91}\right)=0& \left(49\right)\end{array}$

[0117] Said Equations (45) and (49) form a pair in the sense that they obtain the same formulation table. In addition, there are other pairs, such as the pair of Gp_b(α³¹)=0 and Gp_a(β¹⁸¹)=0, the pair Gp_b(α⁶²)=0 and Gp_a(β²¹⁸)=0, etc. There are a total of 8 pairs. For the RS encoding/decoding device of this embodiment, one may use Galois field transformation parameters S120aand S120bcorresponding to the transformation table with any of these pairs.

[0118] The aforementioned Galois field transformation can be described by means of 8×8 matrix.

[0119] Before starting explanation of an example, a generalization of the law of element transformation will be examined.

[0120] [Theorem 1]

[0121] m×m matrix [H_ba(z)] that transforms Galois field GF_b(2^m) into Galois field GF_a(2^m) is defined by following Equation (50). $\text{[Mathematical formula 50]}$ $\begin{array}{cc}{\left({\alpha }^{\mathrm{pz}}\right)}_n=\left[H_{\mathrm{ba}}\left(z\right)\right]{\left({\beta }^z\right)}_b& \left(50\right)\end{array}$

[0122] In said Equation (50), z represents any integer; (X)_arepresents the column vector representation of element X of said Galois field GF_a(2^m). Similarly, (Y)_brepresents the column vector representation of element Y of said Galois field GF_b(2^m). That is, those are m×1 matrixes. α is a primitive element of said Galois field Gf_a(2^m), and it is a root of mth field formation polynomial GP_a(x) on GF(2). β is a primitive element of said Galois field GF_b(2^m), and it is a root of mth field formation polynomial Gp_a(x) on GF(2), and (β)_b=(000 . . . 010)^T.

[0123] Also, on Gp_a(2^m), following Equation (51) is established. $\text{[Mathematical formula 51]}$ $\begin{array}{cc}{\mathrm{Gp}}_b\left({\alpha }^p\right)=0& \left(51\right)\end{array}$

[0124] In this case, following Equation (52) is established. $\text{[Mathematical formula 52]}$ $\begin{array}{cc}\left[H_{\mathrm{ba}}\left(z\right)\right]=\left[H_{\mathrm{ba}}\right]=\left[{\left({\alpha }^{p\left(m-1\right)}\right)}_a{\left({\alpha }^{p\left(m-2\right)}\right)}_a\dots {\left({\alpha }^{2p}\right)}_a{\left({\alpha }^p\right)}_a{\left({\alpha }^0\right)}_a\right]& \left(52\right)\end{array}$

[0125] That is, said Equation (50) is established independently of the value of z.

[0126] Said [Theorem 1] can be proved as follows.

[0127] First, because following Equation (53) is established, following Equation (54) is established using matrix [H_ba] of said Equation (52). $\text{[Mathematical formula 53]}$ $\begin{array}{cc}{\left({\beta }^0\right)}_b={\left(00\dots 001\right)}^T{\left({\beta }^1\right)}_b={\left(00\dots 010\right)}^T{\left({\beta }^2\right)}_b={\left(00\dots 100\right)}^T{\left({\beta }^{m-2}\right)}_b={\left(01\dots 000\right)}^T{\left({\beta }^{m-1}\right)}_b={\left(10\dots 000\right)}^T& \left(53\right)\end{array}$ $\text{[Mathematical formula 54]}$ $\begin{array}{cc}{\left({\alpha }^0\right)}_a=\left[H_{\mathrm{ba}}\right]{\left({\beta }^0\right)}_b{\left({\alpha }^p\right)}_a=\left[H_{\mathrm{ba}}\right]{\left({\beta }^1\right)}_b{\left({\alpha }^{2p}\right)}_a=\left[H_{\mathrm{ba}}\right]{\left({\beta }^2\right)}_b{\left({\alpha }^{p\left(m-2\right)}\right)}_a=\left[H_{\mathrm{ba}}\right]{\left({\beta }^{m-2}\right)}_b{\left({\alpha }^{p\left(m-1\right)}\right)}_a=\left[H_{\mathrm{ba}}\right]{\left({\beta }^{m-1}\right)}_b& \left(54\right)\end{array}$

[0128] Also, for any element β^zof said Galois field GF_b(2^m), following Equation (55) is established. $\text{[Mathematical formula 55]}$ $\begin{array}{cc}{\beta }^z=\sum _{i=0}^{m-1}{B}_{z,1}{\beta }^1& \left(55\right)\end{array}$

[0129] Here, B_z,1=0 or 1, and z represents any integer. Then, as said Equation (51) is established, following Equation (56) is obtained. $\text{[Mathematical formula 56]}$ $\begin{array}{cc}{\alpha }^{\mathrm{pz}}=\sum _{i=0}^{m-1}{B}_{z,i}{\alpha }^{\mathrm{pi}}& \left(56\right)\end{array}$

[0130] This can also readily seen from said Equations (47) and (48). Consequently, for the vector representation on the two sides, it is possible to transform said Equation (54) into following Equation (57). $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}57\right]& \\ \begin{array}{c}{\left({\alpha }^{\mathrm{pz}}\right)}_a=\sum _{i=0}^{m-1}{B_{z,i}\left({\alpha }^{\mathrm{pi}}\right)}_a\\ =\sum _{i=0}^{m-1}{B}_{z,i}\left[H_{\mathrm{ba}}\right]{\left({\beta }^i\right)}_b\\ =\left[H_{\mathrm{ba}}\right]\sum _{i=0}^{m-1}{B_{z,i}\left({\beta }^i\right)}_b\end{array}& \left(57\right)\end{array}$

[0131] In addition, when the vector representation on the two sides of said Equation (55) is substituted into said Equation (57), the following Equation (58) is obtained. $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}58\right]& \\ {\left({\alpha }^{\mathrm{pz}}\right)}_a=\left[H_{\mathrm{ba}}\right]{\left({\beta }^z\right)}_b& \left(58\right)\end{array}$

[0132] This concludes the proof of [Theorem 1].

[0133] Also, according to said Equation (55), the following Equation (59) is established for matrix [H_ba] with respect to (0)_a=(000 . . . 000)^Tand (0)_b=(000 . . . 000)^T. $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}59\right]& \\ {\left(0\right)}_a=\left[H_{\mathrm{ba}}\right]{\left(0\right)}_b& \left(59\right)\end{array}$

[0134] That is, all of the elements of said Galois field Gp_a(2^m) are transformed into all of the elements of said Galois field GP_b(2^m).

[0135] The foregoing can be summarized as follows: m of the 2^minput/output relationships in the input-side transformation process, for m-bit output A₀=(000 . . . 001)^Twith respect to m-bit input (00 . . . 0001)^T, m-bit output A₁=(A_1,m−1, A_1,m−2, . . . A_1,0)^Twith respect to m-bit input (00 . . . 0001)^T, m-bit output A₂=(A_2,m−1, A_2,m−2, . . . A_2,0)^Twith respect to m-bit input (00 . . . 0001)^T, m-bit output A_m−2=(A_m−2,m−1, A_m−2,m−2, . . . A_m−2,0)^Twith respect to m-bit input (01 . . . 0000)^T, and m-bit output A_m−1=(A_m−1,m−1, A_m−1,m−2, . . . A_m−1,0)^Twith respect to m-bit input (10 . . . 0000)^T, the m×m matrix is defined by following Equation (60). $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}60\right]& \\ \left[H_{\mathrm{ba}}\right]=\left(A_{m-1}{A}_{m-2}\dots A_2{A}_1{A}_0\right)& \left(60\right)\end{array}$

[0136] Said input-side transformation process is realized in a calculating process for output m-bit D_a-outwith respect to input m-bit D_b-inindicated by following Equation (61). $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}61\right]& \\ D_{\mathrm{a\_out}}=\left[H_{\mathrm{ba}}\right]\times D_{\mathrm{b\_in}}& \left(61\right)\end{array}$

[0137] Input-side transformation circuit 116 performs the aforementioned input-side transformation process on the basis of Galois field transformation parameter S120a.

[0138] In the following, a specific example of input-side transformation circuit 116 when m=1, q=1, p=241 in said Equations (49)-(57) will be examined.

[0139] From the transformation table shown in FIG. 2, the following Equation (62) is established. $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}62\right]& \\ \begin{array}{c}{\left({\alpha }^0\right)}_a=A_0={\left(00000001\right)}^T\\ {\left({\alpha }^{241}\right)}_a=A_1={\left(01011000\right)}^T\\ {\left({\alpha }^{241\times 2}\right)}_a=A_2={\left(10010000\right)}^T\\ {\left({\alpha }^{241\times 3}\right)}_a=A_2={\left(11110010\right)}^T\\ {\left({\alpha }^{241\times 4}\right)}_a=A_6={\left(00001110\right)}^T\\ {\left({\alpha }^{241\times 5}\right)}_a=A_2={\left(00110111\right)}^T\\ {\left({\alpha }^{241\times 6}\right)}_a=A_6={\left(10110011\right)}^T\\ {\left({\alpha }^{241\times 7}\right)}_a=A_7={\left(11010101\right)}^T\end{array}& \left(62\right)\end{array}$

[0140] Consequently, from said Equation (60), the following Equation (63) is established. $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}63\right]& \\ \begin{array}{c}\left[H_{\mathrm{ba}}\right]=\left(A_7{A}_6\dots A_2{A}_1{A}_0\right)\\ =\left(\begin{array}{cccccccc}1& 1& 0& 0& 1& 1& 0& 0\\ 1& 0& 0& 0& 1& 0& 1& 0\\ 0& 1& 1& 0& 1& 0& 0& 0\\ 1& 1& 1& 0& 1& 1& 1& 0\\ 0& 0& 0& 1& 0& 0& 1& 0\\ 1& 0& 1& 1& 0& 0& 0& 0\\ 0& 1& 1& 1& 1& 0& 0& 0\\ 1& 1& 1& 0& 0& 0& 0& 1\end{array}\right)\end{array}& \left(63\right)\end{array}$

[0141] In this case, when the input/output relationship indicated by said Equation (61) is shown as following Equation (64) for each bit, from Equation (65), following Equation (66) is established. $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}64\right]& \\ D_{\mathrm{b\_in}}={\left(d_{\mathrm{b\_i7}}{d}_{\mathrm{b\_i6}}{d}_{\mathrm{b\_i5}}{d}_{\mathrm{b\_i4}}{d}_{\mathrm{b\_i3}}{d}_{\mathrm{b\_i2}}{d}_{\mathrm{b\_i1}}{d}_{\mathrm{b\_i0}}\right)}^T& \left(64\right)\\ D_{\mathrm{a\_out}}=\left(d_{\mathrm{a\_o7}}{d}_{\mathrm{a\_o6}}{d}_{\mathrm{a\_o5}}{d}_{\mathrm{a\_o4}}{d}_{\mathrm{a\_o3}}{d}_{\mathrm{a\_o2}}{d}_{\mathrm{a\_o1}}{d}_{\mathrm{a\_o0}}\right)& \end{array}$ $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}65\right]& \\ \left(\begin{array}{c}{d}_{\mathrm{a\_o7}}\\ d_{\mathrm{a\_o6}}\\ d_{\mathrm{a\_o5}}\\ d_{\mathrm{b\_o4}}\\ d_{\mathrm{a\_o3}}\\ d_{\mathrm{a\_o2}}\\ d_{\mathrm{a\_o1}}\\ d_{\mathrm{a\_o0}}\end{array}\right)=\left(\begin{array}{cccccccc}1& 1& 0& 0& 1& 1& 0& 0\\ 1& 0& 0& 0& 1& 0& 1& 0\\ 0& 1& 1& 0& 1& 0& 0& 0\\ 1& 1& 1& 0& 1& 1& 1& 0\\ 0& 0& 0& 1& 0& 0& 1& 0\\ 1& 0& 1& 1& 0& 0& 0& 0\\ 0& 1& 1& 1& 1& 0& 0& 0\\ 1& 1& 1& 0& 0& 0& 0& 1\end{array}\right)\left(\begin{array}{c}{d}_{\mathrm{b\_i7}}\\ d_{\mathrm{b\_i6}}\\ d_{\mathrm{b\_i5}}\\ d_{\mathrm{b\_i4}}\\ d_{\mathrm{b\_i3}}\\ d_{\mathrm{b\_i2}}\\ d_{\mathrm{b\_i1}}\\ d_{\mathrm{b\_i0}}\end{array}\right)& \left(65\right)\end{array}$ $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}66\right]& \\ \begin{array}{c}{d}_{\mathrm{a\_o7}}=d_{\mathrm{b\_i7}}\mathrm{XOR}{d}_{\mathrm{b\_i6}}\mathrm{XOR}{d}_{\mathrm{b\_i3}}\mathrm{XOR}{d}_{\mathrm{b\_i2}}\\ d_{\mathrm{a\_o6}}=d_{\mathrm{b\_i7}}\mathrm{XOR}{d}_{\mathrm{b\_i3}}\mathrm{XOR}{d}_{\mathrm{b\_i1}}\\ d_{\mathrm{a\_o5}}=d_{\mathrm{b\_i6}}\mathrm{XOR}{d}_{\mathrm{b\_i5}}\mathrm{XOR}{d}_{\mathrm{b\_i3}}\\ d_{\mathrm{a\_o4}}=d_{\mathrm{b\_i7}}\mathrm{XOR}{d}_{\mathrm{b\_i6}}\mathrm{XOR}{d}_{\mathrm{b\_i5}}\mathrm{XOR}{d}_{\mathrm{b\_i3}}\mathrm{XOR}{d}_{\mathrm{b\_i2}}\\ \mathrm{XOR}{d}_{\mathrm{b\_i1}}\\ d_{\mathrm{a\_o3}}=d_{\mathrm{b\_i4}}\mathrm{XOR}{d}_{\mathrm{b\_i1}}\\ d_{\mathrm{a\_o2}}=d_{\mathrm{b\_i7}}\mathrm{XOR}{d}_{\mathrm{b\_i5}}\mathrm{XOR}{d}_{\mathrm{b\_i4}}\\ d_{\mathrm{a\_o1}}=d_{\mathrm{b\_i6}}\mathrm{XOR}{d}_{\mathrm{b\_i5}}\mathrm{XOR}{d}_{\mathrm{b\_i4}}\mathrm{XOR}{d}_{\mathrm{b\_i3}}\\ d_{\mathrm{a\_o0}}=d_{\mathrm{b\_i7}}\mathrm{XOR}{d}_{\mathrm{b\_i6}}\mathrm{XOR}{d}_{\mathrm{b\_i5}}\mathrm{XOR}{d}_{\mathrm{b\_i0}}\end{array}& \left(66\right)\end{array}$

[0142] Here, XOR represents Exclusive-OR. Consequently, for example, the constitution shown in FIG. 3 may be adopted for input-side transformation circuit 116 that performs transformation of said Equation (66).

[0143] As shown in FIG. 3, input-side transformation circuit 116 has registers 200₀-200₇, 2-input/1-output AND gates 202₀-202₇, and XOR (exclusive-OR) circuit 204.

[0144] Registers 200₀-200₇input and latch bit data S120a₀-S120a₇of Galois field transformation parameter S120afrom parameter setting unit 120, and outputs them to input terminals on one side of AND gates 202₀-202₇, respectively.

[0145] As explained above, for AND gates 202₀-202₇, bit data S120a₀-S120a₇are input from input terminals on one side, and bit data d_a-i0-d_a-i7of data S250 as target of encoding/decoding are input from the input terminals on the other side, and they output their AND as data S202₀-S202₇.

[0146] XOR gates 204 performs exclusive-OR operation on data S202₀-S202₇. Data S116 consisting of bit data d_b-i0-d_b-i7that indicate the operation result is output to RS encoding/decoding core portion 112 as shown in FIG. 1 below.

[0147] In the following, a specific example of input-side transformation circuit 116 shown in FIG. 3 will be explained. As a first example, RS_bencoding and RS_bdecoding are performed. In this case, in input-side transformation circuit 116, arithmetic operation is performed on the basis of said Equation (65).

[0148] That is, first, as bit data that form Galois field transformation parameter S120a(S120a₀, S120a₁, S120a₂, S120a₃, S120a₄, S120a₅, S120a₆, S120a₇), the bit data of the 7^throw of said Equation (65) (1, 0, 0, 0, 0, 1, 1, 1) is input from parameter setting unit 120, and the logical AND values of said bit data (1, 0, 0, 0, 0, 1, 1, 1) and bit data (d_b-i0, d_b-i1, d_b-i2, d_b-i3, d_b-i4, d_b-i5, d_b-i6, d_b-i7) are calculated with AND gates 202₀-202₇, respectively, and data S202₀-S202₇that show said AND values are output to XOR gates 204. Then, XOR gates 204 calculates the exclusive-OR and outputs the result as data d_a-i0.

[0149] Then, as bit data that form Galois field transformation parameter S120a(S120a₀, S120a₁, S120a₂, S120a₃, S120a₄, S120a₅, S120a₆, S120a₇), the bit data of the 6^throw of said Equation (65) (0, 0, 0, 1, 1, 1, 1, 0) is input from parameter setting unit 120, and the logical AND values of said bit data (0, 0, 0, 1, 1, 1, 1, 0) and bit data (d_b-i0, d_b-i1, d_b-i2, d_b-i3, d_b-i4, d_b-i5, d_b-i6, d_b-i7) are calculated with AND gates 202₀-202₇, respectively, and data S202₀-S202₇that show said AND values are output to XOR gates 204. Then, XOR gates 204 calculates the exclusive-OR and outputs the result as data d_a-i1.

[0150] Then, as bit data that form Galois field transformation parameter S120a(S120a₀, S120a₁, S120a₂, S120a₃, S120a₄, S120a₅, S120a₆, S120a₇), the bit data of the 5^throw of said Equation (65) (0, 0, 0, 0, 1, 1, 0, 1) is input from parameter setting unit 120, and the logical AND values of said bit data (0, 0, 0, 0, 1, 1, 0, 1) and bit data (d_b-i0, d_b-i1, d_b-i2, d_b-i3, d_b-i4, d_b-i5, d_b-i6, d_b-i7) are calculated with AND gates 202₀-202₇, respectively, and data S202₀-S202₇that show said logical AND values are output to XOR gates 204. Then, XOR gates 204 calculates the exclusive-OR and outputs the result as data d_a-i2.

[0151] Then, as bit data that form Galois field transformation parameter S120a(S120a₀, S120a₁, S120a₂, S120a₃, S120a₄, S120a₅, S120a₆, S120a₇), the bit data of the 4^throw of said Equation (65) (0, 1, 0, 0, 1, 0, 0, 0) is input from parameter setting unit 120, and the logical AND values of said bit data (0, 1, 0, 0, 1, 0, 0, 0) and bit data (d_b-i0, d_b-i1, d_b-i2, d_b-i3, db-i, d_b-i5, d_b-i6, d_b-i7) are calculated with AND gates 202₀--202₇, respectively, and data S202₀-S202₇that show said logical AND values are output to XOR gates 204. Then, XOR gates 204 calculates the exclusive-OR and outputs the result as data d_a-i3.

[0152] Then, as bit data that form Galois field transformation parameter S120a(S120a₀, S120a₁, S120a₂, S120a₃, S120a₄, S120a₅, S120a₆, S120a₇), the bit data of the 3^rdrow of said Equation (65) (0, 1, 1, 1, 0, 1, 1, 1) is input from parameter setting unit 120, and the logical AND values of said bit data (0, 1, 1, 1, 0, 1, 1, 1) and bit data (d_b-i0, d_b-i1, d_b-i2, d_b-i3, d_b-i4, d_b-i5, d_b-i6, d_b-i7) are calculated by AND gates 202₀-202₇, respectively, and data S202₀-S202₇that show said logical AND values are output to XOR gates 204. Then, XOR gates 204 calculates the exclusive-OR and outputs the result as data d_a-i4.

[0153] Then, as bit data that form Galois field transformation parameter S120a(S120a₀, S120a₁, S120a₂, S120a₃, S120a₄, S120a₅, S120a₆, S120a₇), the bit data of the 2^ndrow of said Equation (65) (0, 0, 0, 1, 0, 1, 1, 0) is input from parameter setting unit 120, and the logical AND values of said bit data (0, 0, 0, 1, 0, 1, 1, 0) and bit data (d_b-i0, d_b-i1, d_b-i2, d_b-i3, d_b-i4, d_b-i5, d_b-i6, d_b-i7) are calculated by AND gates 202₀-202₇, respectively, and data S202₀-S202₇that show said logical AND values are output to XOR gates 204. Then, XOR gates 204 calculates the exclusive-OR and outputs the result as data d_a-i5.

[0154] Then, as bit data that form Galois field transformation parameter S120a(S120a₀, S120a_l, S120a₂, S120a₃, S120a₄, S120a₅, S120a₆, S120a₇), the bit data of the 1^strow of said Equation (65) (0, 1, 0, 1, 0, 0, 0, 1) is input from parameter setting unit 120, and the logical AND values of said bit data (0, 1, 0, 1, 0, 0, 0, 1) and bit data (d_b-i0, d_b-i1, d_b-i2, d_b-i3, d_b-i4, d_b-i5, d_b-i6, d_b-i7) are calculated by AND gates 202₀-202₇, respectively, and data S202₀-S202₇that show said logical AND values are output to XOR gates 204. Then, XOR gates 204 calculates the exclusive-OR and outputs the result as data d_a-6.

[0155] Then, as bit data that form Galois field transformation parameter S120a(S120a₀, S120a₁, S120a₂, S120a₃, S120a₄, S120a₅, S120a₆, S120a₇), the bit data of the 0^thEquation (65) (0, 0, 1, 1, 0, 0, 1, 1) is input from parameter setting unit 120, and the logical AND values of said bit data (0, 0, 1, 1, 0, 0, 1, 1) and bit data (d_b-i0, d_b-i1, d_b-i2, d_b-i3, d_b-i4, d_b-i5, d_h-i6, d_b-i7) are calculated by AND gates 202₀-202₇, respectively, and data S202₀-S202₇that show said logical AND values are output to XOR gates 204. Then, XOR gates 204 calculates the exclusive-OR and outputs the result as data d_a-i7.

[0156] In this way, arithmetic operation shown in said Equation (65) comes to an end.

[0157] As a second example, RS_aencoding is performed. In this case, a unit matrix is used in place of matrix [H_ba] in said Equation (65). Galois field transformation parameter S120acorresponding to said unit matrix is output from parameter setting unit 120 to input-side transformation circuit 116.

[0158] In this case, without transformation in input-side transformation circuit 116, data S250 is directly output as data S116.

[0159] As explained above, input-side transformation circuit 116 can perform any 8×8 matrix operation corresponding to the parameter from parameter setting unit 120. Consequently, it is possible to make use of common hardware for multiple types of RS encoding and RS decoding. As a result, compared with the case when multiple types of hardware are used corresponding to various types of RS encoding and RS decoding, it is possible to have a smaller scale and a lower cost. Also, since the arithmetic operation itself is carried out by means of hardware, it is possible to perform arithmetic operations at high speed.

[0160] In the following, output-side transformation circuit 119 will be examined.

[0161] It is possible to determine matrix [H_ab] corresponding to the output-side transformation operation by means of the inverse operation from the transformation table shown in FIG. 2. However, it is also possible to determine it directly from matrix [H_ba] that has been obtained.

[0162] That is, in the output-side transformation process, m-bit D_b-outof output corresponding to the element of said Galois field Gp_b(2^m) is obtained with respect to m-bit D_a-inof input corresponding to the element of said Galois field Gp_a(2^m). In this case, in said generalized Equation (61), D_a-outis replaced with D_a-in, and D_b-inis replaced with D_b-out, so that following Equation (67) is established. Consequently, one has: $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}67\right]& \\ D_{\mathrm{a\_out}}=\left[H_{\mathrm{ba}}\right]\times D_{\mathrm{b\_in}}& \left(67\right)\end{array}$

[0163] Matrix [H_ba]⁻¹, the inverse matrix of matrix [H_ba], is multiplied from the left side on both sides of said Equation (61), and the following Equation (68) is obtained. $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}68\right]& \\ \begin{array}{c}{\left[H_{\mathrm{ba}}\right]}^{-1}\times D_{\mathrm{a\_in}}={\left[H_{\mathrm{ba}}\right]}^{-1}\left[H_{\mathrm{ba}}\right]\times D_{\mathrm{a\_out}}\\ =D_{\mathrm{b\_out}}\end{array}& \left(68\right)\end{array}$

[0164] Consequently, with following Equation (69), one has following Equation (70) established. $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}69\right]& \\ \left[H_{\mathrm{ab}}\right]={\left[H_{\mathrm{ba}}\right]}^{-1}& \left(69\right)\end{array}$ $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}70\right]& \\ D_{\mathrm{b\_out}}=\left[H_{\mathrm{ab}}\right]\times D_{\mathrm{a\_in}}& \left(70\right)\end{array}$

[0165] As an example, the following Equation (71) is obtained from matrix [H_ba] of said Equation (63). $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}71\right]& \\ \left[H_{\mathrm{ab}}\right]={\left[H_{\mathrm{ba}}\right]}^{-1}=\left(\begin{array}{cccccccc}1& 0& 0& 1& 1& 1& 0& 0\\ 0& 1& 1& 0& 1& 1& 0& 0\\ 1& 0& 1& 1& 1& 0& 1& 0\\ 0& 0& 1& 0& 0& 0& 1& 0\\ 1& 1& 1& 1& 0& 1& 1& 0\\ 1& 0& 0& 0& 0& 1& 1& 0\\ 0& 0& 1& 0& 1& 0& 1& 0\\ 0& 1& 0& 0& 1& 0& 1& 1\end{array}\right)& \left(71\right)\end{array}$

[0166] Similarly, by means of Galois field transformation parameter S120bcorresponding to said matrix [H_ab], one can realize output-side transformation circuit 119 as shown in FIG. 4.

[0167] As shown in FIG. 4, output-side transformation circuit 119 has registers 300₀-300₇, 2-input/1-output AND gates 302₀-302₇, and XOR (exclusive-OR) gate 304.

[0168] As shown in FIG. 4, output-side transformation circuit 119 has the same constitution as that of input-died transformation circuit 116 shown in FIG. 3 above.

[0169] Registers 300₀-300₇input and latch bit data S120b₀-S120b₇of Galois field transformation parameters S120bfrom parameter setting unit 120, and outputs them to input terminals on one side of AND gates 302₀-302₇, respectively.

[0170] As explained above, for AND gates 302₀-302₇, bit data S120b₀-S120b₇are input from input terminals on one side, and bit data d_a-i0-d_a-i7of data S250 as target of encoding/decoding are input from the input terminals on the other side, and they output their logical AND values as data S302₀-S302₇.

[0171] XOR gates 304 performs the exclusive-OR operation on data S302₀-S302₇. Data S116 consisting of bit data d_b-i0-d_b-i7that indicate the operation result is output.

[0172] As far as the operation of output-side transformation circuit 119 shown in FIG. 4 is concerned, except the contents of Galois field transformation parameter S120binput from parameter setting unit 120, the operation is basically identical to that of input-side transformation circuit 116 shown in FIG. 3.

[0173] That is, when output-side transformation circuit 119 performs RS_bencoding and RS_bdecoding, Galois field transformation parameter S120bcorresponding to matrix [H_ab] shown in said Equation (71) is input.

[0174] That is, when data d_b-00-d_b-077 are formed, as the bit data that form Galois field transformation parameter S120b(S120b₀, S120b₁, S120b₂, S120b₃, S120b₄, S120b₅, S120b₆, S120b₇), the 7^throw (1, 1, 0, 1, 0, 0, 1, 0), 6^throw (0, 1, 0, 1, 0, 1, 0, 0), 5^throw (0, 1, 1, 0, 0, 0, 1), 4^throw (0, 1, 1, 0, 1, 1, 1, 1), 3^rdrow (0, 1, 0, 0, 0, 1,0, 0), 2^ndrow (0, 1, 0, 1, 1, 1, 0, 1), 1^strow (0, 0, 1, 1, 0, 1, 1, 0) and 0^throw (0, 0, 1, 1, 1, 0, 0, 1) shown in said Equation (71) are input in order, followed by formation of the logical product with AND gates 302₀-302₇, and the exclusive-OR operation with XOR gates 304.

[0175] On the other hand, in output-side transformation circuit 119, when RS_aencoding and RS_adecoding are performed, a unit matrix is used in place of matrix [H_ab] in said Equation (70). Galois field transformation parameter S120bcorresponding to said unit matrix is output from parameter setting unit 120 to input-side transformation circuit 116.

[0176] In this case, without transformation in output-side transformation circuit 119, data S112 is directly output as data S251.

[0177] As explained above, output-side transformation circuit 119 can perform any 8×8 matrix operation corresponding to the parameter from parameter setting unit 120. Consequently, it is possible to make use of common hardware for multiple types of RS encoding and RS decoding. As a result, compared with the case when multiple types of hardware are used corresponding to various types of RS encoding and RS decoding, it is possible to have a smaller scale and a lower cost. Also, since the arithmetic operations are realized in hardware, it is possible to perform arithmetic operations at high speed.

[0178] RS Encoding/decoding Core Unit

[0179] In the following, the various circuits that form RS encoding/decoding core unit 112 will be explained in detail.

[0180] Surplus Arithmetic Circuit

[0181] In the following, the embodiment of the surplus arithmetic circuit of polynomial as a principal structural element of the RS encoding device will be examined. The RS encoding/decoding core unit shown in FIG. 1 has RS encoding function. Multipliers of the Galois field that forms the surplus arithmetic circuit of polynomial originally exist corresponding to RS_acode. When encoding of RS_bcode is performed, data series D_a-outtransformed by input-side transformation circuit 116bcorresponds to the element of Galois field Gp_a(2^m). Consequently, multiplication of said Galois field is performed according to the rule of multiplication on Gp_a(2^m). Consequently, it is possible to use the same multipliers when encoding is performed for RS_bcode.

[0182] As explained above, because element β^pmof Gp_b(2^m) corresponds to α^pmon Gp_a(2^m), it is necessary to perform the transformation pertaining to the multiplication coefficient of Galois field on Gp_a(2^m). That is, for any integers u, v, multiplication of Galois field indicated by following Equation (72) on said Gp_b(2^m) corresponds to following Equation (73) on Gp_a(2^m). $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}72\right]& \\ {\beta }^u\times {\beta }^v={\beta }^{u+v}& \left(72\right)\end{array}$ $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}73\right]& \\ {\alpha }^{\mathrm{pu}}\times {\alpha }^{\mathrm{pv}}={\alpha }^{p\left(u+v\right)}& \left(73\right)\end{array}$

[0183] It is clear that the division of the Galois field is the same. Also, for addition (=subtraction) of the Galois field, with reference to said Equations (55) and (56), when it is following Equation (74), following Equation (75) is obtained on Gp_a(2^m). $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}74\right]& \\ \begin{array}{c}{\beta }^u+{\beta }^v=\sum _{i=0}^{m-1}{B}_{u,i}{\beta }^i+\sum _{i=0}^{m-1}{B}_{v,i}{\beta }^i\\ =\sum _{i=0}^{m-1}\left(B_{u,i}+B_{v,i}\right){\beta }^i\\ =\sum _{i=0}^{m-1}{B}_{w,i}{\beta }^i\\ ={\beta }^w\end{array}& \left(74\right)\end{array}$ $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}75\right]& \\ \begin{array}{c}{\alpha }^{\mathrm{pu}}+{\alpha }^{\mathrm{pv}}=\sum _{i=0}^{m-1}{B}_{u,i}{\alpha }^{\mathrm{pi}}+\sum _{i=0}^{m-1}{B}_{v,i}{\alpha }^{\mathrm{pi}}\\ =\sum _{i=0}^{m-1}\left(B_{u,i}+B_{v,i}\right){\alpha }^{\mathrm{pi}}\\ =\sum _{i=0}^{m-1}{B}_{w,i}{\alpha }^{\mathrm{pi}}\\ ={\alpha }^{\mathrm{pw}}\end{array}& \left(75\right)\end{array}$

[0184] As a result, usually, for the equation of F(x)=0 including any arithmetic operation, F(β)=0 on GF_b(2^m) corresponds to F(α^p)=0 on GF_a(2^m).

[0185] In the process of RS encoding, the surplus arithmetic process of polynomial due to the code forming polynomial is contained. For the multiplication coefficient in the surplus arithmetic circuit of polynomial of encoding device of the conventional RS_bcode shown in FIG. 12, the relationship represented by following Equation (76) is established. $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}76\right]& \\ \begin{array}{c}\left\{{\beta }_{\mathrm{be}\left(j\right)}\right\}=\left\{{\beta }_{\mathrm{be}\left[0\right]},{\beta }_{\mathrm{be}\left[1\right]},{\beta }_{\mathrm{be}\left[2\right]},\dots {\beta }_{\mathrm{be}\left[L-1\right]},{\beta }_{\mathrm{be}\left[L\right]}\right\}\\ =\left\{{\beta }^{e\left[0\right]},{\beta }^{e\left[1\right]},{\beta }^{e\left[2\right]},\dots {\beta }^{e\left[L-1\right]},{\beta }^{e\left[L\right]}\right\}\end{array}& \left(76\right)\end{array}$

[0186] That is, following Equation (77) is established $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}77\right]& \\ \begin{array}{c}{\mathrm{Gc}}_b\left(x\right)=\prod _{i=0}^L\left(x+{\beta }^{a\left(b+j\right)}\right)\\ ={\beta }^{e\left[L\right]}{x}^L+{\beta }^{e\left[L-1\right]}{x}^{L-1}+\dots {\beta }^{e\left[2\right]}{x}^2+{\beta }^{e\left[1\right]}{x}^1+\\ {\beta }^{e\left[0\right]}{x}^0\end{array}& \left(77\right)\end{array}$

[0187] Here, L=2t−1or 2t. From the relationship of said equation and Equations (72)-(75), the collection (α_be[j]) of the multiplication coefficients of the corresponding Galois field on GF_a(2^m) should meet following Equation (78). $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}78\right]& \\ \begin{array}{c}\left\{{\alpha }_{\mathrm{be}\left(j\right)}\right\}=\left\{{\alpha }_{\mathrm{be}\left[0\right]},{\alpha }_{\mathrm{be}\left[1\right]},{\alpha }_{\mathrm{be}\left[2\right]},\dots {\alpha }_{\mathrm{be}\left[L-1\right]},{\alpha }_{\mathrm{be}\left[L\right]}\right\}\\ =\left\{{\alpha }^{p\times e\left[0\right]},{\alpha }^{p\times e\left[1\right]},{\alpha }^{p\times e\left[2\right]},\dots {\alpha }^{p\times e\left[L-1\right]},{\alpha }^{p\times e\left[L\right]}\right\}\end{array}& \left(78\right)\end{array}$

[0188] In this case, corresponding code forming polynomial Gc_ba(x) becomes following Equation (79). $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}79\right]& \\ \begin{array}{c}\mathrm{Gcba}\left(x\right)={\alpha }^{p\times e\left[L\right]}{x}^L+{\alpha }^{p\times e\left[L-1\right]}{x}^{L-1}+\dots {\alpha }^{p\times e\left[2\right]}{x}^2+\\ {\alpha }^{p\times e\left[1\right]}{x}^1+{\alpha }^{p\times e\left[0\right]}{x}^0\\ =\prod _{i=0}^L\left(x+{\alpha }^{\mathrm{pe}\left(b+j\right)}\right)\end{array}& \left(79\right)\end{array}$

[0189] That is, in this embodiment, the surplus arithmetic circuit of polynomial in the RS encoding device corresponding to two RS codes is shown in FIG. 5.

[0190] As shown in FIG. 5, surplus arithmetic circuit 102 has multipliers 103-0˜103-L, registers 105-0˜105-L, and adders 106-0˜106-L.

[0191] Multipliers 103-0˜103-L selectively have corresponding multiplication coefficients (α_be[j]) and multiplication coefficients (α_ae[j]) input from multiplication coefficient memory unit 111, and the results of multiplication of said input multiplication coefficients and input data are output to registers 105-0˜105-L. More specifically, when RS_aencoding is performed, by means of parameter setting unit 120, multiplication coefficients (α_ae[j]) are output to multipliers 103-0˜130-L, respectively, to perform multiplication of multiplication coefficients (α_ae[j]) and input data. On the other hand, when RS_bencoding is performed, by means of parameter setting unit 120, multiplication coefficients (α_be[j]) are output to multipliers 103-0˜130-L, respectively, and multiplication of multiplication coefficients (α_be[j]) and input data is carried out.

[0192] Here, multiplication coefficients (α_be[j]) are a collection of the multiplication coefficients of Galois field of the surplus arithmetic operation of polynomial corresponding to code forming polynomial G_Cbashown in said Equation (79). Also, multiplication coefficients (α_ae[j]) are a collection of the multiplication coefficients of Galois field of the surplus arithmetic operation of polynomial corresponding to code forming polynomial G_Cashown in said Equation (38). As shown in FIG. 5, multipliers of Galois field 103-0˜103-L are multipliers on GF_a(2^m), and adders of Galois field 106-0˜106-L are adders on GF_a(2^m).

[0193] Consequently, with respect to the surplus arithmetic circuit of the polynomial expression, which corresponds to said RS_acodes that exist originally, it is possible to realize the surplus arithmetic circuits of polynomials corresponding to RS_aand RS_bcodes at the same time by simply switching the multiplication coefficients of the Galois field. Also, as shown in FIG. 1, this embodiment may also be adopted in encoding three or more RS codes with different field formation polynomials. The larger the number, the more significant the effect. Also, it is believed that said collection (β_be[j]) contains 0. However, as 0^P=0, element of said collection (α_be[j]) is still 0, and the corresponding code forming polynomial Gc_ba(x) is still represented by said Equation (79). Also, strictly speaking, this code forming polynomial is also contained in the Goppa code.

[0194] For the example with m=8, q=88, p=241, more specifically, b=120, L=15 are substituted into said Equation (78), obtaining following Equations (80) and (81). $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}80\right]& \\ \begin{array}{c}{\mathrm{Gc}}_b\left(x\right)=\prod _{j=0}^{15}\left(x+{\beta }^{86\left(120+j\right)}\right)\\ ={\beta }^0{x}^{15}+{\beta }^{30}{x}^{14}+\dots +{\beta }^{230}{x}^2+{\beta }^{30}{x}^1+{\beta }^0{x}^0\end{array}& \left(80\right)\end{array}$ $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}81\right]& \\ \left\{{\beta }_{\mathrm{be}\left[1\right]}\right\}=\left\{{\beta }^0,{\beta }^{30},{\beta }^{230},\dots {\beta }^{30},{\beta }^0\right\}& \left(81\right)\end{array}$

[0195] Also, the following Equations (82) and (83) are established. $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}82\right]& \\ \begin{array}{c}{\mathrm{Gc}}_{\mathrm{ba}}\left(x\right)=\prod _{j=0}^{15}\left(x+{\alpha }^{241\times 88\left(120+j\right)}\right)\\ ={\alpha }^0{x}^{15}+{\alpha }^{90}{x}^{14}+\dots +{\alpha }^{95}{x}^2+{\alpha }^{90}{x}^1+{\alpha }^0{x}^0\end{array}& \left(82\right)\end{array}$ $\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{formula}83\right]& \\ \left\{{\alpha }_{\mathrm{be}\left[j\right]}\right\}=\left\{{\alpha }^0={\alpha }^{241\times 0},{\alpha }^{90}={\alpha }^{241\times 30},{\alpha }^{96}={\alpha }^{241\times 230},\dots {\alpha }^{90}={\alpha }^{241\times 30}\right\}& \left(83\right)\end{array}$