Adjustable offset voltage circuit

[0002] The invention relates to offset voltage circuits, and particularly relates to offset voltage circuits for use in digital data receiver systems.

[0003] A digital data receiver system typically includes some threshold detection circuitry for distinguishing between a high (or binary one) signal, and a low (or binary zero) signal. If the signals are relatively clean with respect to noise, then the threshold detection circuitry may simply set the threshold value to zero volts differential, and signals above zero volts differential are detected as a binary one, and signals below zero volts differential are detected as a binary zero.

[0004] Many digital data receiver systems, such as those that may be used with fiber optic communication systems, suffer from the presence of noise in the receiver signal. The presence of noise becomes potentially problematic if the noise causes the signal to cross the threshold, e.g., zero volts differential, within a single bit of information. One approach to reducing the noise is to include a capacitor in the receiver system that would integrate the signal with respect to time. This approach, however, limits the data clock speed of the receiver circuit due to the time delay required by the capacitor.

[0005] In certain communication systems, the noise in the received signal has been found to disproportionately affect the high signal to a greater extent than it affects the low signal. For example in receiver systems that include either an optical preamplifier or an avalanche photo diode, the high signal has been found to generally have more noise than the low signal Another approach, therefore, is to lower the threshold voltage by an offset voltage (e.g., 100 mv differential) that is tailored to the needs of the particular receiver system. Such offset circuits, however, typically provide non-linear responses to changes in adjustment voltages due to the non-ideal and non-linear characteristics of transistors within the offset circuitry itself, making proper adjustment difficult to achieve. The use of such adjustable offset voltage circuits, therefore, may have remained limited due to difficulties in setting the offset to a desired voltage.

[0006] There is a need, therefore, for an improved digital data receiver system that efficiently and accurately distinguishes between high and low data signals at high clock speeds.

[0007] There is a further need for an improved offset voltage circuit that provides a linear response to adjustment voltage inputs.

[0008] An adjustable offset voltage circuit is disclosed for applying an offset voltage to a differential voltage in a digital data receiver system. The circuit includes a pair of emitter follower units, and a pair of current generating units. The first emitter follower unit provides a first offset voltage, and the second emitter follower unit provides a second offset voltage. The first current generating unit provides a biasing current to the first emitter follower unit, and the second current generating unit provides a biasing current to the second emitter follower unit. The circuit also includes a pair of differential signal input ports, each of which is coupled to one of the first and second emitter follower units, and an offset adjustment unit for permitting offset adjustment of a differential output signal with respect to a differential input signal at the input ports. In an embodiment, the offset adjustment unit includes a, degenerated differential pair of transistors.

[0009] The following description may be further understood with reference to the accompanying drawing in which:

[0010] FIG. 1 shows an illustrative diagrammatic view of a system of the invention in a digital data transmitter and receiver circuit;

[0011] FIG. 2A shows an illustrative graphical view of an example of data signals that are received in a receiver circuit that includes a system of the invention;

[0012] FIG. 2B shows an illustrative graphical view of the distribution of the data signals of FIG. 2A;

[0013] FIG. 3 shows an adjustable offset voltage circuit in accordance with an embodiment of the invention; and

[0014] FIGS. 4A-4C show illustrative graphical views of an example of data signals at various nodes in the circuit of FIG. 3.

[0015] A circuit of the invention may be employed in a digital data transmission system as shown in FIG. 1. In particular, such a system may include a transmitter system 10, an optical fiber communication channel 12, and a receiver system 14. The transmitter system 10 includes a data transmitter input port 16, a laser diode driver 18, and a laser diode 20. The receiver system includes a photo diode 22, a transimpedance amplifier 24, an adjustable offset circuit of the invention 26, a limiting amplifier 28, and a clock and data recovery circuit 30 that produces digital data output at an output port 32.

[0016] The transimpedance amplifier 24 includes a positive data signal line 34, and a negative data signal line 36, that are coupled to a positive input (PIN) 38 of the adjustable offset circuit 26 and to a negative input (NIN) 40 of the circuit 26 respectively as shown. The offset circuit 26 may be adjusted by varying the voltage input to the offset adjust positive (SP) input 42 as well as the offset adjust negative (SN) input 44. The output offset positive signal (IN) 46 and the output offset negative signal (INB) 48 of the offset circuit 26 are coupled to the limiting amplifier 28 as shown in FIG. 1.

[0017] Generally, digital data is transmitted by the transmitter system 10, through the fiber optic cable 12, and received at the receiver system 14. The receiver system 14 must distinguish between high signals that represent binary one data, and low signals that represent binary zero data. This is achieved by the limiting amplifier 28, and the input to the limiting amplifier may be adjustably offset by the circuit 26 to reduce the potential for error due to signal noise that is disproportionately greater for either the positive or negative data signal.

[0018] For example, as shown in FIG. 2A, the high signal that represents binary one data 50 may include more noise than the low signal that represents binary zero data 52. If the threshold is set to zero volts, the noise on the high signal 50 may cause erroneous information to be received by the receiver system, for example, if the noise causes the high signal to drop below zero volts. The offset circuit of the invention permits the threshold to be lowered to a lower threshold of −d volts as shown to optimize the receiver's bit error rate. The probability distribution curves 54, 56 for the high and low signals 50 and 52 respectively are shown in FIG. 2B. The preferred value of −d is the point at which the distribution curve 54 crosses the distribution curve 56 as shown in FIG. 2B.

[0019] Adjustment of the offset circuit may be easily achieved by varying the offset adjust positive input (SP) 42, and the offset adjust negative input (SN) 44 to provide an offset voltage between the differential voltage signal inputs 38 and 40, and the differential output signal voltages 46 and 48.

[0020] As shown in FIG. 3, an offset circuit in accordance with a specific embodiment of the invention includes a pair of emitter follower circuits for providing the offset voltages, a pair of current generating circuits for providing biasing currents, and a degenerated differential pair transconductance circuit for permitting the adjustment of the offset voltages.

[0021] The first emitter follower circuit includes a transistor 60 (q₆₀) and a series resistor 62 (R₆₂) that is coupled to the emitter of transistor 60 as shown. The base of transistor 60 is coupled to the positive input (PIN) 38 from the transimpedance amplifier 24, and the collector of transistor 60 is coupled to ground. Similarly, the second emitter follower circuit includes a transistor 64 (q₆₄) and a series resistor 66 (R₆₆) that is coupled to the emitter of transistor 64 as shown. The base of transistor 64 is coupled to the negative input (NIN) 40 from the transimpedance amplifier 24, and the collector of transistor 64 is coupled to ground.

[0022] The first current generating circuit includes a transistor 68 (q₆₈) and a series resistor 70 (R₇₀) that is coupled to the emitter of transistor 68 and to a voltage source (VCC) as shown. The base of transistor 68 is coupled to a bias voltage source (VB) 72, and the collector of transistor 68 is coupled to the resistor 62 of the first emitter follower circuit. The second current generating circuit includes a transistor 74 (q₇₄) and a series resistor 76 (R₇₆) that is coupled to the emitter of transistor 74 and to a voltage source (VCC) as shown. The base of transistor 74 is coupled to the bias voltage source (VB) 72, and the collector of transistor 74 is coupled to the resistor 66 of the second emitter follower circuit. The differential output offset signals 46 and 48 are provided at the collectors of the transistors 68 and 74 respectively as shown.

[0023] The degenerated differential pair transconductance circuit includes a pair of transistors 78 and 80 (q₇₈, q₈₀), the emitters of which are coupled to one another by a resistor 82 (R₈₂) and to a pair of current sources 84 and 86 respectively as shown. The collector of transistor 78 (q₇₈) is coupled to the emitter of transistor 68, and the offset adjust positive (SP) input 42 is coupled to the base of transistor 78. The collector of transistor 80 (q₈₀) is coupled to the emitter of transistor 74, and the offset adjust negative (SN) input 44 is coupled to the base of transistor 80.

[0024] The circuit shown in FIG. 3 is particularly robust against systematic offset errors that are typically present in bipolar transistor at varying currents, as well as process variations. This characteristic permits the voltage offset circuit to provide a predicable linear response to changes in the differential adjust inputs 42 and 44. Moreover, the voltage offset circuit is well suited for applications involving low voltage power supplies (e.g., 3.3 v.), as well as applications requiring relatively simple offset circuits that are efficient to manufacture. Finally, the circuit of FIG. 3 minimizes any additional parasitic capacitances that might be added to the critical nodes in a high-speed data path. Such parasitic capacitances might otherwise limit the maximum data rate of operation of the receiver system.

[0025] The circuit of FIG. 3 minimizes errors due to the varying voltage potentials that typically exist between transistor bases and emitters when biased at different collector currents. The delta base to emitter voltage (δV_be) represents the change in the base-emitter voltage for each bipolar transistor from the condition where the nodes SP and SN are at the same voltage, to the condition where there is a differential voltage applied across SP and SN. The delta base to emitter voltage (δ_be) for a transistor may be expressed as $\delta V_{\mathrm{be}}=\frac{\mathrm{kT}}{q}{\mathrm{Log}}_N\left(\frac{I_C}{I_{C,\mathrm{SN}=\mathrm{SP}}}\right)$

[0026] where k is Boltzman's constant, T is temperature in degrees Kelvin, q is the electronic charge, I_cis the collector current flowing in the transistor and I_C.SN=SPis the collector current flowing in the transistor when the voltage at SP is equal to the voltage at SN.

[0027] Initially, consider the case where V_SP=V_SN, and the inputs at nodes 38 and 40 are equal. In this case, Is₁=Is₂=Is₀, where Is₁is the current into the collector of transistor 78, Is₂is the current into the collector of transistor 80, and Is₀is the current drawn by each of current sources 84 and 86. If it assumed that the current through resistor 62 (I₀₁) is equal to the current through resistor 66 (I₀₂), which for convenience will be referred to as the current I₀, and that the voltages at inputs 38 and 40 (V_PINand V_NIN) are each zero volts, then the voltages at nodes 46 and 48 (V_inand V_inbrespectively) are provided by V_in=V_be,q60+(I₀₁R₆₂), and V_inb=V_be,q64+(I₀₂R₆₆). The total current through resistor 70 (It₁)=(VCC−(VB+V_be,q68))/R₇₀, and the total current through resistor 76 (It₂)=(VCC−(VB+V_be,q74))/R₇₆. Also, the current I₀₁=It₁−Is₁and the current I₀₂=It₂−Is₂. The difference V_in−V_inb, therefore, equals zero since I₀₁=I₀₂, and R₆₂=R₆₆, and consequently V_be,q60=V_be,q64, and V_be,q68=V_be,q74.

[0028] When there is a differential voltage applied to nodes 42 and 44, and Is₁>Is₂, then ${\mathrm{It}}_1=\frac{\mathrm{VCC}-\left(\mathrm{Vb}+V_{\mathrm{be},\mathrm{q68}}+\delta V_{\mathrm{be},\mathrm{q68}}\right)}{R_{70}}\text{and}$ ${\mathrm{It}}_2=\frac{\mathrm{VCC}-\left(\mathrm{Vb}+V_{\mathrm{be},\mathrm{q74}}+\delta V_{\mathrm{be},\mathrm{q74}}\right)}{R_{76}}$

[0029] The value δV_be,q68will be negative (and will be equal to δV_be,q60) because when Is₁increases, there is less current flow through transistor 68. Consequently, I₀₁<I₀and It₁will increase. Conversely, the value δV_be,q74will be positive (and will be equal to δV_be,q64) because when Is₂decreases, there is more current flow through transistor 74. Consequently, I₀₂>I₀and It₂will decrease.

[0030] To calculate the differential offset voltage generated between nodes 46 and 48 when V_PIN=V_NIN=zero volts, the current flowing through resistors 62 and 66 may be expressed as $I_{01}={\mathrm{It}}_1-{\mathrm{Is}}_1=\frac{\mathrm{VCC}-\left(\mathrm{Vb}+V_{\mathrm{be},\mathrm{q68}}+\delta V_{\mathrm{be},\mathrm{q68}}\right)}{R_{70}}-{\mathrm{Is}}_1\text{and}$ $I_{02}={\mathrm{It}}_2-{\mathrm{Is}}_2=\frac{\mathrm{VCC}-\left(\mathrm{Vb}+V_{\mathrm{be},\mathrm{q74}}+\delta V_{\mathrm{be},\mathrm{q74}}\right)}{R_{76}}-{\mathrm{Is}}_2$

[0031] Since V_in=V_be,q60+δV_be,q60+I₀₁R₆₂, and V_inb=V_be,q64+δV_be,q64+I₀₂R₆₆, the above expressions for I₀₁and I₀₂may be employed, and the offset voltage that appears between the differential outputs 46 and 48 may, therefore, be defined as:

[0032] V_IN−V_INB=(Is₂−Is₁)R₀+(δV_be,q60−R₆₂/R₇₀δV_be,q68−δV_be,q64+R₆₆/R₇₆δV_be,q74)

[0033] where the emitter areas of q₆₀, q₆₄, q₆₈and q₇₄are assumed to be equal to one another, and Is₁is the current drawn from VCC through R₇₀that does not travel into the emitter of transistor 68, Is₂is the current drawn from VCC through R₇₆that does not travel into the emitter of transistor 74, and R₆₂equals R₆₆, which for convenience will be referred to as R₀(R₆₂=R₆₆=R₀). If we assume that R₇₀=R₇₆, then the currents may be set such that the errors cancel out of the above equation leaving the term (Is₂−Is₁)R₀. This permits the circuit to provide predicable linear responses to changes in the SP and SN inputs. The transistors 60 and 68 must always have substantially the same V_bevalues and δ_bevalues because they always have substantially the same current flowing in their collectors. The same is true for transistors 64 and 74.

[0034] When SP is not equal to SN, then δV_be,q60must have a polarity that is opposite to δV_be,q64. The same is true for δV_be,q68and δV_be,q74. Because of these relationships, the terms may not simply cancel by themselves. In order to cause these terms to cancel, R₀must be made equal to R₇₀and R₇₆.

[0035] A further refinement of the circuit involves the reduction of the errors in the degenerated differential transistor pair q₇₈and q₈₀that are used to generate the differential offset adjust current (Is₁−Is₂). The current Is₁−Is₂is given by ${\mathrm{Is}}_1-{\mathrm{Is}}_2=\frac{2\left(V\left(\mathrm{SP}\right)-V\left(\mathrm{SN}\right)\right)}{\mathrm{re},q_{78}+\mathrm{re},q_{80}+R_{82}}$

[0036] where re,q₇₈equals kT/qIs₁, and re,q₈₀equals kT/qIs₂where q is the electronic charge. The resulting offset gain is defined as $\frac{V\left(\mathrm{IN}\right)-V\left(\mathrm{INB}\right)}{V\left(\mathrm{SP}\right)-V\left(\mathrm{SN}\right)}=-R_0\frac{{\mathrm{Is}}_1-{\mathrm{Is}}_2}{V\left(\mathrm{SP}\right)-V\left(\mathrm{SN}\right)}=\left(-R_0\right)\frac{2}{\mathrm{re},q_{78}+\mathrm{re},q_{80}+R_{82}}$

[0037] When Is₁>>Is₂, then re,q₇₈becomes negligible, and re,q₈₀becomes comparable to the required value of R₈₂, which introduces significant non-linearity by making the value (Is₁−Is₂) sub-linear to V(SP)−V(SN). In this example, the term (Is₁−Is₂)R₀is less negative than ideally required for linear performance. The typical approach to correcting this is to choose a large bias current Is and only operate over a part of the available range (V(SP)−V(SN))max=(Is R₈₂)/2, where the variation is small. However, if R₇₀is made larger than R₀by a certain amount, then the error may be compensated. When Is₁>Is₂, then δV_be,q60=δV_be,q68(which is a negative number), and δV_be,q64=δV_be,q74(which is a positive number), and (Is₂−Is₁) R₀is negative. By making R₇₀somewhat larger than R₀, the δV_be,q60term does not exactly cancel with the δV_be,q68term. Also, the δV_be,q64term does not exactly cancel with the δV_{be,q 74}term. The effect is that the contribution of the δV_beterms compensate for the fact that the (Is₁−Is₂)R₀term was not negative enough.

[0038] Using the above techniques, the gain spread has been simulated to be approximately 2.7% with worst case process, temperature, and supply voltage conditions, and having an offset range of 0 to greater than 100 mv.

[0039] As shown in FIG. 4A, an example of a differential input signal that may be received at nodes 38 and 40 includes signals that alternate between V_A(e.g., 1.1 volts) and V_B(e.g., 0.1 volts) as shown to provide, for example digital data of alternating binary ones and zeros. The signals at nodes 38 and 40 are shown in FIG. 4A without noise for clarity, and alternate with respect to a middle voltage V_MID, where V_MID=(V_A−V_B)/2+V_B.

[0040] As shown in FIG. 4B, the signal at node 90 associated with the signal 38 of FIG. 4A alternates between voltages V_A1and V_B1, where V_A1=V_A+V_be,q60, and V_B1=V_B+V_be,q60. The signal at node 92 associated with the signal 40 of FIG. 4A alternates between voltages V_A2and V_B2, where V_A2=V_A+V_be,q64, and V_B2=V_B+V_be,q64. If the inputs SP and SN at nodes 42 and 44 are equal to one another, then V_be,q60=V_be,q64=V_be,q60=q64and the middle voltage for signals 90 and 92 are each V_MIDOas shown where V_MIDO=V_MID+V_be,q60=q64. As the inputs SP and SN are varied with respect to one another, the middle voltage for the signal 90 is at V_MID1=V_MID0+δV_be,q60, and the middle voltage for the signal 92 is at V_MID2=V_MID0+δV_be,q64.

[0041] As shown in FIG. 4C, the signal at node 46 associated with the signal 38 of FIG. 4A alternates between voltages V_A1′ and V_B1′ where V_A1′=V_A+V_be,q60+(I₀₁R₀), and V_B1′=V_B+V_be,q60+(I₀₁R₀). The signal at node 48 associated with the signal 40 of FIG. 4A alternates between voltages V_A2′ and V_B2′ where V_A2′=V_A+V_be,q64+(I₀₂R₀) and V_B2′=V_B+V_be,q64+(I₀₂R₀). Again, if the inputs SP and SN at nodes 42 and 44 are equal to one another, then V_be,q60=V_be,q64=V_be,q60=q64and I₀₁=I₀₂=I₀, then the middle voltage for signals 46 and 48 are each V_MIDO′ as shown where V_MIDO′=V_MID+V_be,q60=q64+(I₀R₀). As the inputs SP and SN are varied with respect to one another, the middle voltage for the signal 46 is at V_MID1′=V_MID0+δV_be,q60+(I₀₁R₀), and the middle voltage for the signal 48 is at V_MID2′=V_MID0+δV_be,q64+(I₀₂R₀). The offset voltage, therefore, is the difference between V_MID1′ and V_MID2′.

[0042] Those skilled in the art will appreciate that numerous modifications and variations may be made to the above embodiments without departing from the spirit and scope of the invention. For example, a wide variety of other types of transistors and other components may be used in addition to those disclosed above, such as the substitution of npn transistors for the pnp transistors disclosed above with the polarity of the circuit reversed.