Electrical and thermal contact for use in semiconductor devices

[0002] This application is a continuation of application Ser. No. 09/568,901, filed May 11, 2000, now U.S. Pat. No. 6,284,643 B1, issued Sep. 4, 2001, which is a divisional of application Ser. No. 09/189,098, filed Nov. 9, 1998, pending.

[0003] 1. Field of the Invention

[0004] The present invention relates to an electrical and thermal contact for use in semiconductor devices. Particularly, the present invention relates to an electrical and thermal contact which reduces the amount of energy input that is required in order to switch a semiconductor device structure that is contacted thereto between two or more states. More specifically, the electrical and thermal contact of the present invention includes thin conductive layers which envelop an insulator component. The electrical and thermal contact is particularly useful for switching contacted structures that include a phase change component between two or more states of electrical conductivity.

[0005] 2. State of the Art

[0006] Electrically erasable programmable memory devices (EEPROMS) typically include several memory elements that may be switched between a first logic state and a second logic state. A first logic state may be an inactive state, or an “off” state, wherein electrical impulses do not travel across the memory element. Memory elements may be said to be in a second logic state, such as an “activated” state or an “on” state, when low voltage electrical impulses (i.e., of the operational voltage of the EEPROM) will readily travel thereacross.

[0007] Memory elements may comprise fuse elements or antifuse elements. Fuse elements are programmed by “blowing” (i.e., breaking the electrical connection across) the fuse thereof, which switches the fuse elements from an active state to an inactive state. Conversely, antifuse elements are programmed by forming a low resistance electrical path across (i.e., activating) the antifuses thereof. The programming of both fuse and antifuse elements requires the application of a sufficient current and voltage to such memory elements. Nevertheless, the application of too great a current to memory elements, such as fuse and antifuse elements, increases the potential that various other components of the EEPROM of which they are a part, including without limitation the gate oxide layer, transistors, and other structures on the surface thereof, may be damaged.

[0008] FIG. 1 is a schematic representation of an exemplary conventional antifuse element 1, which includes a metal contact 2, first and second electrodes 4 and 8, respectively, and a dielectric layer 6, which electrically insulates the first electrode 4 from the second electrode 8. Metal contact 2 is typically a large element relative to the remainder of antifuse element 1. As a current is applied to metal contact 2, the resistance that is generated thereby and by at least one of the electrodes 4, 8 that are in contact therewith locally heats dielectric layer 6, destroying at least a portion of the same and facilitating the formation of an electrically conductive pathway between first electrode 4 and second electrode 8. Thus, an electrical contact is established between first and second electrodes 4 and 8, respectively, thereby activating the antifuse element.

[0009] As noted previously, programming pulses which comprise high electrical voltages may damage various components of an EEPROM, including, without limitation, the gate oxide layer, transistors and other structures on the surface of the EEPROM. Consequently, in order to reduce the potential for damaging EEPROMs during the programming thereof, the programming pulses for EEPROMs are ever-decreasing, as are the normal operating voltages thereof. State of the art EEPROMs typically operate at either 5V or 3.3V. U.S. Pat. No. 5,486,707, issued to Kevin T. Look et al. on Jan. 23, 1996, discloses an exemplary programmable memory that includes antifuse elements that may be switched to an “on” state by a programming voltage of about 7.5V to about 10V. While in the “off” state, the electrical resistance of a typical EEPROM antifuse element is on the order of about 1 gigaohm or greater. After an antifuse of a typical state of the art EEPROM has been switched to the “on” state by a programming pulse, the former has a low electrical resistance, on the order of tens of ohms or less.

[0010] The memory elements of such state of the art EEPROMs typically have lower programming voltage requirements than their predecessors, due to the structure of the memory elements of the former and the materials that are utilized in the memory elements. While the programming voltage requirements of such EEPROMs are ever-decreasing, due to the widespread use of conventional, low thermal impedance metal contacts in connection with the antifuse elements thereof, an extremely high current is typically required in order to generate a sufficient temperature to activate such antifulse elements. Further, due to the high rate at which many conventional metal contacts dissipate heat, such contacts may necessitate the input of even greater amounts of current in order to adequately heat and activate an antifuse element. Moreover, the typical use of conventional, relatively large metal contacts on such EEPROMs is somewhat undesirable from the standpoint that such contacts consume a great deal of surface area or “real estate” on the surface of the semiconductor device. Thus, conventional metal contacts limit the density of active device regions on the semiconductor device.

[0011] The dissipation of heat away from the memory cell through the metal contact is especially undesirable when the memory cell includes a phase change component, such as a chalcogenide material layer, such as the EEPROM devices disclosed in U.S. Pat. No. 5,789,758 (hereinafter “the '758 patent”), which issued to Alan R. Reinberg on Aug. 4, 1998. As is known in the art, chalcogenide materials and some other phase change materials exhibit different electrical characteristics, depending upon their state. For example, chalcogenide materials have a lower electrical conductivity in their amorphous state, or phase, than in their crystalline state. Chalcogenide materials may be changed from an amorphous state to a crystalline state by increasing their temperature. The electrical conductivity of the material may vary incrementally between the amorphous state and the crystalline state.

[0012] Some EEPROMs include metal contacts that are offset from the active device regions of the former. Such offset contacts are said to reduce the dissipation of thermal energy from the active device regions. Although the direct dissipation of heat from the active device regions of such EEPROM structures may be reduced, thermal energy is conducted to the offset metal contacts, which dissipate heat at approximately the same rate as conventionally positioned metal contacts.

[0013] Thus, an electrical and thermal contact is needed which facilitates the input of reduced current and voltage into a structure that is electrically contacted thereto (i.e., conserves energy) and which has a low rate of thermal dissipation relative to conventional metal contacts. A more compact electrical and/or thermal contact structure is also needed.

[0014] The electrical and thermal contact of the present invention addresses each of the foregoing needs. The electrical and thermal contact of the present invention contacts a structure of a semiconductor device, such as a phase change component of an active device region thereof, as disclosed in the '758 patent, and in U.S. Pat. No. 5,789,277 (“the '277 patent”), which issued to Zahorik et al. on Aug. 4, 1998, the disclosures of both of which are hereby incorporated by reference in their entirety. The electrical and thermal contact of the present invention includes an intermediate conductive layer adjacent the contacted structure, a thermal insulator component, which is also referred to as an insulator component, that is adjacent the intermediate conductive layer, and a contact layer that is adjacent the thermal insulator component and which partially contacts the intermediate conductive layer. Preferably, the contact layer and intermediate conductive layer are in electrical and thermal communication with the contacted structure. The thermal insulator component is preferably sandwiched between the intermediate conductive layer and the contact layer, such that the thermal insulator component is substantially enveloped by the intermediate conductive and contact layers. An exemplary active device region to which the electrical and thermal contact of the present invention may be contacted is a memory cell, or element, of an electrically erasable programmable memory (EEPROM) device.

[0015] Fabricating the electrical and thermal contact includes forming a dielectric layer around the lateral peripheral portions of a semiconductor device structure to be contacted, patterning the dielectric layer to expose at least a portion of the semiconductor device structure to be contacted, such as an active device region thereof, depositing a first thin conductive layer, depositing another dielectric layer adjacent the first thin conductive layer, patterning the dielectric layer to define a thermal insulator component, depositing a second thin conductive layer adjacent the thermal insulator component and in electrical communication with the first thin conductive layer, and patterning the first and second thin conductive layers to define the intermediate conductive layer and the contact layer, respectively. The dielectric layer is fabricated from an electrically and thermally conductive material. Preferably, during patterning of the dielectric layer, the first thin conductive layer is utilized as an etch stop. The processes that may be employed to fabricate the electrical and thermal contact facilitate the fabrication of a relatively small electrical and thermal contact, when compared with conventional metal contacts.

[0016] Other advantages of the present invention will become apparent to those of ordinary skill in the relevant art through a consideration of the ensuing description, the accompanying drawings, and the appended claims.

[0017] FIG. 1 is a schematic representation of an exemplary conventional antifuse element;

[0018] FIG. 2 is a cross-section of a contact according to the present invention, depicting the association of the contact with a contacted structure on the surface of a semiconductor device;

[0019] FIG. 3 is a cross-section of a variation of the semiconductor device of FIG. 2, the contacted structure of which includes a phase change component;

[0020] FIG. 4 is a cross-section of a semiconductor device, depicting the formation of a first thin layer of electrically conductive material over the phase change component of FIG. 3;

[0021] FIG. 5 is a cross-section of a semiconductor device, depicting the formation of a dielectric layer over the first thin layer of FIG. 4;

[0022] FIG. 6 is a cross-section of a semiconductor device, depicting the patterning of the dielectric layer of FIG. 5;

[0023] FIG. 7 is a cross-section of a semiconductor device, depicting the formation of a second thin layer of electrically conductive material over the patterned dielectric layer and first thin layer of FIG. 6;

[0024] FIG. 8 is a cross-section of a semiconductor device, depicting the patterning of the first and second layers of FIG. 7;

[0025] FIG. 9 is a schematic cross-sectional representation of a semiconductor device including a contact according to the present invention which is in contact with a memory element; and

[0026] FIGS. 10 and 11 are schematic cross-sectional representations of alternative embodiments of the electrical and thermal contact of the present invention.

[0027] The present invention comprises an electrical and thermal contact for a contacted structure of a semiconductor device. With reference to FIGS. 2 and 3, in a preferred embodiment, the electrical and thermal contact 10 is disposed on a surface 15 of a semiconductor device 14. Electrical and thermal contact 10 may be positioned adjacent a contacted structure 12, such as an antifuse or other memory element, that is exposed through oxide layer 11, such that it electrically and thermally contacts the contacted structure 12. Preferably, contact 10 contacts an electrically conductive phase change component 13 of contacted structure 12 (FIG. 3), such as the memory element disclosed in the '758 patent. Preferably, contacted structure 12 includes a dielectric element 19 surrounding the lateral peripheral portions of phase change component 13 to thermally and electrically insulate the latter.

[0028] Electrical and thermal contact 10 includes a thin, intermediate conductive layer 16, disposed adjacent contacted structure 12, a thermal insulator component 20 positioned adjacent the intermediate conductive layer, and a thin, electrically conductive contact layer 22 disposed adjacent the thermal insulator component. Preferably, thermal insulator component 20 is sandwiched between intermediate conductive layer 16 and contact layer 22, such that thermal insulator component 20 is substantially enveloped by the intermediate and contact layers.

[0029] Phase change component 13 is preferably fabricated from an electrically conductive phase change material, such as amorphous silicon or a so-called “chalcogenide” alloy, which typically includes at least one of germanium, antimony, selenium, and telurium. Such materials exhibit different electrical characteristics, depending upon their state. For example, phase change materials such as chalcogenides exhibit greater electrical conductivity when in a crystalline phase than in an amorphous phase.

[0030] Intermediate conductive layer 16 is positioned such that it electrically contacts phase change component 13 and establishes electrical communication between contact layer 22 and contacted structure 12. Intermediate conductive layer 16 is fabricated from an electrically conductive material and preferably has a thickness of about 200 Å or less. Preferably, in order to maintain the structural integrity of intermediate conductive layer 16 during the operation of semiconductor device 14, the material from which the intermediate conductive layer is fabricated has a melting point that is higher than both the ambient temperature at which the semiconductor device operates and the phase change temperature of phase change component 13. An exemplary material that may be used to fabricate intermediate conductive layer 16 is titanium nitride (TiN), which may be deposited in highly conformal layers of about 200 Å or less by techniques that are known in the art, such as chemical vapor deposition processes. Other materials that may be used to define intermediate conductive layer 16 include, without limitation, tungsten, titanium, other refractory metals, other refractory metal nitrides, metal alloys and other materials which are useful as electrically conductive traces on semiconductor devices.

[0031] Thermal insulator component 20 is disposed upon intermediate conductive layer 16, and is preferably positioned over contacted structure 12. Thermal insulator component 20 may be fabricated from a thermally insulative material, such as a silicon oxide (e.g., SiO₂), a doped silicon oxide (e.g., borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG)), silicon nitride, thermoset resins, thermoplastic polymers, and other dielectric materials which exhibit good thermal insulative properties.

[0032] Contact layer 22 is preferably disposed over the entire surface of thermal insulator component 20 and over the exposed portions of intermediate conductive layer 16 that are adjacent to the thermal insulator component. Contact layer 22 is fabricated from an electrically conductive material that preferably has a thickness of about 200 Å or less. Preferably, in order to maintain the structural integrity of contact layer 22 during the operation of semiconductor device 14, the material from which the contact layer 22 is fabricated has a melting point that is higher than both the ambient temperature at which the semiconductor device operates and the phase change temperature of phase change component 13. An exemplary material from which contact layer 22 may be fabricated is titanium nitride (TiN), which may be deposited in highly conformal layers of about 200 Å or less by techniques that are known in the art, such as chemical vapor deposition processes. Alternatively, contact layer 22 may be manufactured from materials including, without limitation, aluminum, tungsten, titanium, other refractory metals, other refractory metal nitrides, metal alloys and other materials that are useful as electrically conductive traces in semiconductor device applications.

[0033] Turning now to FIGS. 4 through 8, a process for fabricating electrical and thermal contact 10 is described and illustrated.

[0034] Referring now to FIG. 4, in order to form intermediate conductive layer 16 (see FIGS. 2 and 3), a first thin layer 24 of thermally and electrically conductive material is deposited on surface 15 of semiconductor device 14, such that it contacts portions of phase change component 13 that are exposed through the oxide layer 11 of surface 15. First thin layer 24 may be formed by techniques that are known in the art which are capable of depositing an electrically conductive layer formed of a desired material and having a desirable thickness and conformity. Thin-film deposition techniques that are useful for forming first thin layer 24 include, without limitation, chemical vapor deposition (CVD) processes (e.g., atomospheric pressure CVD, low pressure CVD, plasma-enhanced CVD) and sputtering, or physical vapor deposition, processes. Such techniques typically blanket-deposit a layer of the desired material over the entire surface of a semiconductor device or larger substrate including a multitude of such devices, including any exposed contacted structures thereof.

[0035] FIG. 5 illustrates the deposition of a dielectric layer 26 adjacent first thin layer 24. Preferably, dielectric layer 26 is deposited upon first thin layer 24. As described in greater detail below, thermal insulator component 20 (see FIGS. 2 and 3) will be defined from dielectric layer 26. Dielectric layer 26, which comprises a thermally insulative material, such as those disclosed previously in reference to FIGS. 2 and 3, may be deposited adjacent first thin layer 24 across the contact by techniques that are known to those in the art, such as chemical vapor deposition processes. Dielectric layer 26 has a thickness that will provide the desired amount of heat retention proximate phase change component 13 at a desirable temperature to effect the desired phase change and consequent change in the electrical conductivity of phase change component 13.

[0036] With reference to FIG. 6, dielectric layer 26, which is depicted by broken lines, is patterned to define one or more distinct thermal insulator components 20 of desired dimensions which are positioned in desired locations upon semiconductor device 14. Processes that are known in the art, such as masking and etching, are employed to pattern dielectric layer 26 and define one or more thermal insulator components 20 therefrom. Preferably, first thin layer 24 is utilized as an etch stop while defining one or more thermal insulator components 20 from dielectric layer 26.

[0037] Turning to FIG. 7, a second thin layer 28 of thermally and electrically conductive material is then deposited adjacent thermal insulator component 20. Second thin layer 28 is preferably deposited conformally and in substantially uniform thickness over surface 15 of semiconductor device 14 (or larger substrate as noted above), including substantially over the exposed areas of the thermal insulator component 20 and upon the exposed portions of first thin layer 24. Second thin layer 28 may be formed by techniques that are known in the art which are capable of depositing an electrically conductive layer formed of a desired material and having a desirable thickness and conformity. Thin-film deposition techniques that are useful for forming second thin layer 28 include, without limitation, chemical vapor deposition (CVD) processes and sputtering processes. Such techniques typically blanket-deposit a layer of the desired material over the entire surface 15 of semiconductor device 14.

[0038] Referring now to FIG. 8, first and second thin layers 24 and 28 are patterned to define intermediate conductive layer 16 and contact layer 22 of each distinct electrical and thermal contact 10 on surface 15, as well as any electrical traces (not shown) that are in electrical contact with the electrical and thermal contacts. First and second thin layers 24 and 28 may be patterned by techniques that are known in the art, such as masking and etching.

[0039] The processes that may be employed to fabricate electrical and thermal contact 10 facilitate the fabrication of a structure that is relatively small when compared to the size of conventional metal contacts. Similarly, electrical and thermal contact 10 may be fabricated by processes that form and define structures of various dimensions. The thermal and electrical conductivity of electrical and thermal contact 10 is dependent upon several factors, including, without limitation, the thickness of the first and second thin layers, the height and mass of the thermal insulator component 20, and various characteristics of the materials from which intermediate conductive layer 16, contact layer 22 and thermal insulator component 20 are fabricated.

[0040] Referring again to FIG. 3, as noted previously, the disposition of electrical and thermal contact 10 adjacent and in direct contact with phase change component 13 of contacted structure 12 facilitates a reduction in the overall amount of current and heat that are required to operate or activate the contacted structure relative to the respective amount of current that is typically required by many semiconductor devices which include conventional heavy electrical contacts over contacted chalcogenide memory elements. Many conventional electrical contacts dissipate substantial amounts of thermal energy into the surrounding environment, and thus away from the structures in contact therewith.

[0041] In contrast, the thin electrically conductive layers (i.e., intermediate conductive layer 16 and contact layer 22) and the thermal insulator component 20 of electrical and thermal contact 10 effectively retain thermal energy in contacted structure 12. The thin intermediate conductive layer 16 and contact layer 22 each exhibit high impedances relative to conventional metal contacts.

[0042] As current is conveyed through contact layer 22 and intermediate conductive layer 16, thermal energy is created and absorbed by phase change component 13. The long path lengths of layers 16 and 22 provide a high thermal impedance and prevent the heat generated in phase change component 13 from being conducted away from phase change component 13. Thus, phase change component 13 heats to a desirable temperature (e.g., a temperature that will switch phase change component 13 from a first conductivity state to a second conductivity state) with a low voltage input relative to that required by conventional metal contacts.

[0043] When phase change component 13 is heated to a sufficient temperature, thermal insulator component 20, which is proximate to phase change component 13, opposite intermediate conductive layer 16, prevents heat from escaping into the environment surrounding thermal contact 10 and, therefore, prevents heat from escaping phase change component 13.

[0044] Thus, electrical and thermal contact 10 effectively contains thermal energy within phase change component 13 of contacted structure 12. Moreover, due to its small surface area relative to that of conventional metal contacts, electrical and thermal contact 10 does not dissipate heat as quickly as conventional metal contacts. Thus, the amount of voltage that is required to effect a thermally-induced switching of contacted structure 12 from a first state to a second state is also reduced.

[0045] FIG. 9 illustrates an exemplary use of electrical and thermal contact 10 in an electrically erasable programmable memory semiconductor device 30, which is also referred to as a semiconductor device for simplicity, that includes a plurality of memory elements 32 (although only a single memory element 32 is illustrated in FIG. 9). Exemplary memory elements 32 with which the electrical and thermal contact 10 of the present invention are particularly useful include those disclosed in the '758 patent. Memory element 32 includes an upper contact electrode 36 and a lower contact electrode 38, both of which may comprise a phase change material. As illustrated, memory element 32 also includes diffusion regions of p-doped isolation channels 39 adjacent lower contact electrode 38, and an n-epitaxial structure 40 adjacent the p-doped isolation channel 39. An n+ channel 41, which addresses the individual memory cells 32, is adjacent and in electrical communication with n-epitaxial structure 40. Electrical and thermal contact 10 preferably contacts upper contact electrode 36, which may comprise phase change component 13. Although FIG. 9 illustrates a vertically contacted memory element 32, the electrical and thermal contact 10 of the present invention may also be employed in association with other memory element designs or configurations, as are known to those of skill in the art, as well as with other types of memory devices and other structures that may be fabricated on semiconductor devices and for which an infusion of thermal energy with a reduced, or lower, level of current input may be desired.

[0046] With continued reference to FIG. 9, as an example of the use of electrical and thermal contact 10 in programming memory element 32, a programming impulse source 42 is placed into electrical contact with contact layer 22. An electrical current generated by programming impulse source 42 is then conducted through contact layer 22 and intermediate conductive layer 16, and through the phase change component 13 thereof, and causes phase change component 13 to change phase, thereby altering the electrical conductivity characteristics of phase change component 13. Thermal insulator component 20 and low thermal conduction of upper contact electrode 36 prevent the escape of heat from memory element 32. Thus, self-heating of the phase change material of phase change component 13, due in part to the resistivity thereof, heats memory element 32 to a temperature that is sufficient to activate the memory element and create a low resistance electrical pathway through memory element 32, thereby switching memory element 32 from an “off” state to an “on” state.

[0047] FIGS. 10 and 11 illustrate alternative embodiments of an electrical and thermal contact 110, 110′, respectively, which is disposed on a surface 115, 115′ of a semiconductor device 114, 114′ in electrical contact with a contacted structure, such as a memory element 112, 112′ of a type known in the art.

[0048] Electrical and thermal contact 110, 110′ includes a thin, electrically conductive base layer 116, 116′ disposed on surface 115, 115′ of semiconductor device 114, 114′ and in electrical contact with a first conductive element 130, 130′ of memory element 112, 112′. An insulator component 120, 120′ of contact 110, 110′ is disposed on base layer 116, 116′. An electrically conductive contact layer 122, 122′ is disposed adjacent insulator component 120, 120′, and in electrical contact with base layer 116, 116′. Each of the elements of contact 110, 110′ may be fabricated from the materials and by the processes that were discussed above.

[0049] Memory element 112, 112′ includes a memory cell 132, 132′ in electrical contact with first conductive element 130, 130′. Memory cell 132, 132′ is fabricated as known in the art from materials such as polysilicon that will undergo a phase change, “rupture,” or “fuse” to create a higher or lower electrical resistance pathway upon the application of a minimum predetermined current thereto. Memory element 112′ may also include a second electrically conductive element 134′ that electrically contacts memory cell 132′ (see FIG. 11).

[0050] As an example of the use of electrical and thermal contact 110, 110′ in programming a memory element 112, 112′, a programming impulse source 142 is placed into contact with contact layer 122, 122′. An electrical current that is generated by source 142, 142′ is then conducted through contact layer 122, 122′ to memory element 112, 112′. Heat generated in memory element 112, 112′ causes it to switch states. The heat is prevented from leaving the memory element 112, 112′ by the low thermal conductivity of contact 110, 110′.

[0051] Although the foregoing description contains many specifics, these should not be construed as limiting the scope of the present invention, but merely as providing illustrations of some of the presently preferred embodiments. Similarly, other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention. The scope of this invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions and modifications to the invention as disclosed herein which fall within the meaning and scope of the claims are to be embraced thereby.