Unified constant-frequency integration control of three-phase power factor corrected rectifiers, active power filters and grid-connected inverters

[0002] The present application is a continuation-in-part application of U.S. patent application Ser. No. 09/632,772, filed on Aug. 4, 2000, issued as U.S. Pat. No. 6,297,980, which in turn was related to U.S. Provisional Patent Application No. 60/147,623 filed on Aug. 6, 1999 and U.S. Provisional Patent Application No. 60/157,321 filed on Oct. 1, 1999.

[0003] 1. Field of the Invention

[0004] The invention relates to the field of 3-phase power factor corrected rectifiers, active power filters, and grid-connected inverters and in particular to control methods based on one-cycle control.

[0005] 2. Description of the Prior Art

[0006] The invention in this document covers vast applications spanning from power factor corrected rectifiers in front of and active power filters in parallel to electronic equipement such as computers, communication, motion control, aviation, space electronics, etc. to the grid-connected inverters for distributed power generation.

[0007] Power factor corrected rectifiers

[0008] In recent years, the usage of modern electronics equipment has been widely proliferating. The electronics equipment usually have a rectifier of single-phase or three-phases in the front end. Three-phases are more desirable for high power applications. A three-phase rectifier is a device that converts three-phase sinusoidal ac power into dc power. Traditional rectifiers draw pulsed currrent from the ac main as shown in FIG. 1, which causes significant harmonic pollution, low power factor, reduced transmition efficiency, harmful electromagnetic interference to neighborhood appliances, as well as overheating of transformers.

[0009] In order to solve these problems, many international agencies have proposed harmonic restrictions to electronic equipment. As a result, a vast number of power factor corrected (PFC) rectifers have been proposed to comply with these regulations.

[0010] A three-phase power factor corrected rectifeir is a device that converts three-phase sinusoidal ac power into dc power while the input currents are sinusoidal and unity power factor, as shown in FIG. 2. Many three-phase topologies are suitable for implementing PFC function for rectification. Usually, high frequency active switches are used in the rectifiers to realize the PFC function.

[0011] The control methods that modulate the pulse width of the switches are an important issue in the power electronics research. A third harmonic injection method was reported for a dual-boost converter with center-tapped dc-link and split output capacitors. This method achieves low current distortion. However, it is not convenient to generate the third harmonic signal tuned to the right frequency and right amplitude.

[0012] Hysteresis control and d-q transformation control were frequently used control approaches. Hysteresis control results in variable switching frequency that is difficult for EMI filter design. The d-q approach is based on digital implementation that leads to complicated systems. An analog control method with constant switching frequency modulation was reported for a particular rectifier, where several multipliers are necessary to implement the three phase current references. Due to the disadvantages of variable frequency or complexity of implementation, three-phase PFC rectifiers are not commercially practical.

[0013] Active power filters:

[0014] One alternative for dealing with the current harmonics generated by treaditional rectifiers is to use active power filters (APF). Considering electronic equipment with traditional rectifier as nonlinear loads to the ac main, a three-phase APF is a device that is connected in parallel to and cancels the reactive and harmonic currents from one or a group of nonlinear loads 110 so that the resulting total current drawn from the ac main is sinusoidal as shown in FIG. 3. In contrast to PFC, where a PFC unit is usually inserted in the energy pass, which processes all the power and corrects the current to unity power factor, APF provides only the harmonic and reactive power to cancel the one generated by the nonlinear loads. In this case, only a small portion of the energy is processed, which may result in overall higher energy efficiency and higher power processing capability.

[0015] Most APF control methods proposed previously need to sense the three-phase line voltages and the three-phase nonlinear load currents, and then manipulate the information from these sensors to generate three-phase current references for the APF. Since the reference currents have to reflect the load power of the nonlinear load, several multipliers are needed to scale the magnitude of the current references. A control loop is necessary to control the inverter to generate the reactive and harmonic current required by the nonlinear load. These functions are generally realized by a digital signal processing (DSP) chip with fast analog-to-digital (A/D) converters and high-speed calculations. The complex circuitry results in high cost and unreliable systems, preventing this technique from being used in practical applications.

[0016] Some approaches that sense the main line current were reported for single-phase APF and for three-phase APF. The overall circuitry is reduced. However, multipliers, input voltage sensors are still necessary. High speed DSPs are still used in three-phase systems due to the complexity of the systems.

[0017] Grid-connected inverters:

[0018] Distributed power generation is the trend in the future in order to promote new power generation technologies and reduce transmition costs. An effective use of natural resources and renewable resources as alternatives to fossil and nuclear energy for generation of electricity has the effect of protecting the environment. In order for the alternative energy sources to impact the energy supply in the future, they need to be connected to the utility grid. Therefore, grid-connected inverters are the key elements for the distributed power generation systems. A grid-connected inverter is a device that converts dc power to ac power of single phase or three-phase power that is injected to the utility grid. In order for an alternative energy source to be qualified as a supplier, sinusoidal current injection is required as shown in FIG. 4.

[0019] Again, control methods are crucial. In the past, d-q transformer modulation based on digital implementation was often employed for a standard six-switched bridge inverter topology. The complexity results in low reliability and high cost. In addition, short-through hazard exists in this inverter.

[0020] What is needed is a design for 3-phase power factor corrected rectifiers, active power filters, and grid-connected inverters which overcomes each of the foregoing limitations of the prior art.

[0021] The method of the invention is an unified constant-frequency integration (UCI) control method based on one-cycle control. It employs an integrator with reset as its core component along with logic and linear components to control the pulse width of a three-phase recitifier, active power filter, or grid-connected inverter so that the all three phase current draw from or the current output to the utility line is sinusoidal. No multipliers are required, as used in many control approaches to scale the current references according to the load level. Furthermore, no reference calculation circuitry is needed for controlling active power filters.

[0022] The UCI control employs constant switching frequency and operates in continuous conduction mode (CCM) that is desirable for industry applications. This control approach is simple, general, and flexible and is applicable to many topologies with slight modification of the logic circuits, while the control core remains unchanged. Although, a DSP is not required to implement the UCI control; if in some cases a DSP is desired for other purposes, the unified constant-frequency control function may be realized by a low cost DSP with a high reliability, because no high speed calcutation, high speed A/D converter, or mutipliers are required.

[0023] The implementation of UCI control can be roughly classified into two categories: (1) vector control mode and (2) bipolar control mode. A three-phase system in the vector control mode has only two switches operating at a switching frequency at a given time, while a three-phase system in bipolar control mode has three switches operating at a switching frequency.

[0024] Power factor corrected rectifiers:

[0025] The power train of a three-phase rectifier is usually a boost-derived three-phase converter. The UCI controller for PFC applications can control the power train in either the vector and bipolar control mode.

[0026] In vector control mode, the boost-derived three-phase rectifiers are categorized into two groups. One group of them can be decoupled into a series-connected dual-boost topology that features central-tapped or split dc output capacitors. The other group can be decoupled into a parallel-connected dual-boost topology that features a single dc output capacitor. The dual-boost sub-topologies rotate their connection every 60° of the line cycle depending on the line voltage states: In each 60° of ac line cycle, only two switches are switched at high frequency. Therefore, the switching loss is significantly reduced. The switches operate at a current lower than the phase current, which results in reduced current ratings and conduction losses.

[0027] In bipolar control mode the input phase voltage, output dc voltage, and duty ratios of switches for some boost rectifiers are related by a general equation. Based on the one-cycle control and solutions of this general equation, which is singular and has infinite solutions, several UCI control solutions are derived below for topologies such as the standard six-switch rectifier, VIENNA rectifier and similar circuits.

[0028] The UCI control method for PFC rectifiers has demonstrated excellent performance, great simplicity, namely an order of magnitude fewer components than prior art, and unparallelled reliability.

[0029] Active Power Filters:

[0030] The UCI control approach is based on an one-cycle control and senses main currents. No multipliers nor reference calculation circuitry are required. Thus, the implementaion cirucitry is an order of magnitute simpler than previously proposed control methods. The UCI control for active power filters has serveral solutions. One solution uses a vector control mode and the need to sense the three-phase line voltage. The switching losses for vector control are reduced. The other version uses bipolar control mode that eliminates three-phase line voltage sensors.

[0031] Inverters for Alternative Energy Sources

[0032] Grid-connected inverters with sinusoidal current output are proposed. A three-phase standard bridge inverter can be decoupled in a parallel-connected dual-buck subtopology during each 60° of line cycle. Therefore, only two switches are controlled at switching frequency in order to realize sinusoidal output with unity-power-factor. By the proposed control method, the grid-connected inverter features an unity-power-factor, low current distortion, as well as low switching losses. In addition, short-through hazard is eliminated because only one of switches in each bridge arm is controlled during each 60° of line cycle.

[0033] While the method has been described for the sake of grammatical fluidity as steps, it is to be expressly understood that the claims are not to be construed as limited in any way by the construction of “means” or “steps” limitations under 35 USC 112, but to be accorded the full scope of the meaning and equivalents of the definition provided by the claims. The invention can be better visualized by turning now to the following drawings wherein like elements are referenced by like numerals.

[0034] FIG. 1 is a schematic diagram of a prior art three-phase rectifier

[0035] FIG. 2 is a schematic diagram of a prior art power factor corrected three-phase rectifier.

[0036] FIG. 3 is a schematic diagram of a prior art active power filter.

[0037] FIG. 4 is a schematic diagram of a prior art grid-connected inverter.

[0038] FIG. 5 is a schematic diagram of a power factor correction circuit (PFC) with UCI control in vector mode according to the invention.

[0039] FIG. 6 is a schematic diagram of a power factor correction circuit (PFC) with UCI control in bipolar mode according to the invention.

[0040] FIG. 7 is a schematic diagram of an active power filter (APF) with UCI control in vector mode according to the invention.

[0041] FIG. 8 is a schematic diagram of an active power filter (APF) with UCI control in bipolar mode according to the invention.

[0042] FIG. 9 is a schematic diagram of a grid-connected inverter with UCI control in vector operation according to the invention.

[0043] FIG. 10 is a schematic diagram of a grid-connected inverter with UCI control in bipolar operation according to the invention.

[0044] FIG. 11ais a schematic of a conventional 3-phase boost rectifier with delta-connected 3 φ switches.

[0045] FIG. 11bis a schematic of a conventional 3-phase boost rectifier with star-connected 3 φ switches.

[0046] FIG. 11cis a schematic of a conventional 3-phase standard bridge boost rectifier.

[0047] FIG. 11dis a schematic of a conventional 3-phase standard bridge boost rectifier with a diode.

[0048] FIG. 11eis a schematic of a conventional 3-phase boost rectifier with an inverter network.

[0049] FIG. 12 is a graph of the normalized three-phase voltage waveforms of the circuits of FIGS. 11a-11e.

[0050] FIG. 13ais a schematic of the equivalent circuit of 3-phase boost rectifier with delta-connected switches and its corresponding parallel-connected dual-boost topology in the portion of the cycle from 0˜60°.

[0051] FIG. 13bis a schematic of the equivalent circuit of 3-phase boost rectifier with delta-connected switches and its corresponding parallel-connected dual-boost topology in the portion of the cycle from 60°˜120°.

[0052] FIGS. 14a-14dare schematics of the equivalent circuits for the parallel-connected dual-boost topology in all four switching states of the circuit of FIG. 13a.

[0053] FIG. 15 is a graph of the inductor voltage and current waveforms for the topology shown in FIG. 13aunder the condition d_p>d_n.

[0054] FIG. 16 is a schematic of the core control block of the UCI three-phase PFC controller of the invention.

[0055] FIG. 17ais a schematic implementation of the selection function Δ(i,θ) i=1, 2, . . . 6.

[0056] FIG. 17bis a graph showing the operation waveforms of the circuit of FIG. 17a.

[0057] FIG. 18 is a graph of the waveforms of the control core in FIG. 16.

[0058] FIG. 19 is a block diagram for the realization of control signal for switch s_ab.

[0059] FIG. 20 is a schematic of a prototype three-phase boost PFC with active soft switching.

[0060] FIG. 21 is a graph of the three phase inductor current waveforms at full load with a horizontal scale at 5 ms/div; and vertical scale at 5 A/div.

[0061] FIG. 22 is a graph of the waveforms of phase voltage and current at full load with a Horizontal scale at 5 ms/div. The top curve on the graph shows the input phase voltage at 100 V/div and the bottom curve on the graph shows the input phase A current, 2 A/div.

[0062] FIG. 23ais a schematic of the equivalent circuit for interval 0˜60° for the three-phase standard bridge boost rectifier of FIG. 11c.

[0063] FIG. 23bis a schematic of the equivalent circuit for interval 0˜60° for the parallel-connected dual-boost topology of FIG. 13a.

[0064] FIG. 24 is a graph of the simulated current waveforms for three-phase standard bridge boost rectifiers shown in FIGS. 11cand 11dwith the UCI three-phase PFC controller of the invention.

[0065] FIG. 25ais a schematic of a 3-phase 3-switch 3-level boost rectifier (VIENNA rectifier).

[0066] FIG. 25bis a schematic of a 3 phase boost rectifier with ac inductors and a split dc rail.

[0067] FIG. 25cis a schematic of a 3 phase boost rectifier with ac inductors and an asymmetric half bridge.

[0068] FIG. 25dis a schematic of a (d). 3-phase boost rectifier with dc inductors and a split dc-rail.

[0069] FIG. 25eis a schematic of a three-phase boost rectifier with dc inductors and an asymmetric half bridge.

[0070] FIG. 26 is a graph of the normalized three-phase voltage waveforms for the rectifiers of FIGS. 25a-25e.

[0071] FIG. 27ais a schematic for the equivalent circuit for a VIENNA rectifier during the (−30°˜30°) interval when s_ais on.

[0072] FIG. 27bis a schematic for a series-connected dual-boost topology corresponding to FIG. 27a.

[0073] FIG. 28 is a graph of the normalized dual-boost topology input voltage V_Pand V_nfor interval −30°˜30° of the circuitry of FIGS. 27aand 27b.

[0074] FIGS. 29a-29dare the equivalent circuit of the topology of FIG. 27bin four switching states.

[0075] FIG. 30 is a graph of the waveforms of the inductor voltages and currents for series-connected dual-boost topology (under condition d_p<d_n).

[0076] FIG. 31 is a schematic of the control block of proposed PFC controller for three-phase boost rectifier with a split dc-rail.

[0077] FIGS. 32aand 32bare graphs of the Implementation of input-selection-function Δ(θ,i) and its waveforms.

[0078] FIG. 33 is a graph of the normalized waveform for voltages v_p,v_nand inductor currents i_Lp,i_Lnduring line cycle.

[0079] FIG. 34 is a graph of a simulated three-phase input current waveforms for VIENNA rectifier with proposed controller.

[0080] FIG. 35 is a graph of measured three-phase inductor current waveforms. The vertical scale is 5 A/div and horizontal scale is 5 ms/div.

[0081] FIG. 36 is a graph of the measured phase A voltage and current waveforms. The top curve is the phase A voltage shown at 50 V/div, and the bottom curve is the phase A current, show at 5 A/div with a horizontal scale of 5 ms/div.

[0082] FIG. 37 is a graph of simulated current waveforms for three-phase boost rectifier in FIGS. 25band 25cwith controller of the invention. For the three-phase boost rectifier with dc inductors and a split-dc rail in FIG. 25(d), the series-connected dual-boost topology is shown in FIG. 28.

[0083] FIG. 38 is a schematic diagram of the series-connected dual-boost converter topology for the rectifier shown in FIG. 25(d).

[0084] FIG. 39 is a graph of simulated waveforms for rectifiers in FIGS. 25(d) and (e) with proposed controller of the invention.

[0085] FIG. 40ais a schematic of a three-phase 6-switch bridge boost rectifier.

[0086] FIG. 40bis a schematic of an average model

[0087] FIG. 41ais a schematic of proposed 3-phase boost PFC controller.

[0088] FIG. 41bis a graph of the operation waveforms of the circuit of FIG. 41a.

[0089] FIG. 42 is the output of a simulated three-phase inductor current waveforms with controller shown in FIG. 41a.

[0090] FIG. 43 is an illustration of sensing switching current for phase A

[0091] FIG. 44 is a schematic for the control block for six-switch boost bridge rectifier with average switching current control.

[0092] FIGS. 45aand 45bshow the simulation results for six-switch boost bridge rectifier with average switching current mode control. FIG. 45(a) is a graph of the simulated three-phase inductor currents. FIG. 45(b) is a graph of the operation waveforms of the control block in FIG. 4.

[0093] FIGS. 46aand 46bare two examples of bridge boost rectifier. FIG. 46(a) is a schematic of a 6-switch boost bridge rectifier with dc-diode. FIG. 46(b) is a schematic of a three-level rectifier.

[0094] FIG. 47 is a graph of simulated three-phase inductor current waveforms for 6-switch bridge rectifier with dc diode and inductor current control.

[0095] FIG. 48 is a schematic of a 3-phase rectifier with reduced switch count.

[0096] FIG. 49 The schematic of control block for the 3-phase rectifier in FIG. 48.

[0097] FIG. 50 is a garph of the operation waveforms for the controller in FIG. 49.

[0098] FIG. 51 is a graph of simulated inductor current waveforms for the 3-phase rectifier in FIG. 49 with proposed UCI PWM controller.

[0099] FIGS. 52aand 52bare schematics for an equivalent circuit for the 3-phase rectifier with reduced switch count in FIG. 48.

[0100] FIGS. 53aand 53bshow a 3-phase VIENNA rectifier in FIG. 53aand its average model in FIG. 53b.

[0101] FIGS. 54aand 54bare schematics of proposed 3-phase PFC controller for VIENNA rectifier by sensing inductor current in FIG. 54aand its operation waveform FIG. 54b.

[0102] FIG. 55 is a graph of a simulated inductor current waveforms for VIENNA rectifier with proposed controller in FIGS. 54aand 54b

[0103] FIG. 56 is a schematic illustration of switching current sensing for VIENNA rectifier.

[0104] FIG. 57 is a schematic of 3-PFC controller for VIENNA rectifier with peak switching current mode control.

[0105] FIGS. 58aand 58bshow the simulation results for 3-PFC for VIENNA rectifier with switching peak current control. FIG. 58ais a graph of the operation waveforms of the controller. FIG. 58bis a graph of the simulated inductor current waveforms.

[0106] FIG. 59 is a schematic of control block for 3-PFC VIENNA rectifier with average switching current mode control.

[0107] FIGS. 60aand 60bare graphs of simulated waveforms for 3-phase VIENNA rectifier with average switching current mode control. FIG. 60ashows the operation of control block. FIG. 60bshows the simulated inductor current.

[0108] FIGS. 61aand 61bshow a comparison between the general topology for UCI controlled 3-phase PFC and APF. FIG. 61ais a general diagram of the UCI controlled 3-phase PFC. FIG. 61bis a general diagram of the UCI controlled 3-phase APF.

[0109] FIG. 62 is a schematic of three-phase APF with standard six-switch bridge converter and bipolar operated UCI controller.

[0110] FIG. 63 is an implementation of equation 38 with integrator with reset.

[0111] FIG. 64 is a graph of the simulation results for active power filter with proposed controller in FIG. 62.

[0112] FIG. 65 is a schematic of three-phase APF diagram based on 3-phase bridge with reduced switch count.

[0113] FIG. 66 is a graph of the simulation results for three-phase APF in FIG. 65.

[0114] FIG. 67 is a schematic of three-phase APF with half-bridge configuration

[0115] FIG. 68 is a graph of three-phase voltage waveforms.

[0116] FIG. 69 is a diagram of vector operated UCI controller for 3-phase APF.

[0117] FIG. 70 is a schematic of logic circuit for switching drive signal Q_anand Q_ap.

[0118] FIG. 71 is a graph of a simulation waveform for three-phase APF with proposed controller based on vector control.

[0119] FIG. 72 is a schematic of a three-phase grid-connected circuit with a standard six-switch bridge inverter.

[0120] FIG. 73 is a graph of a three-phase utility voltage waveforms.

[0121] FIG. 74ais a schematic of an equivalent circuit for inverter in FIG. 72 during 0˜60°. FIG. 74bis a schematic of parallel-connected dual buck topology.

[0122] FIGS. 75a-75dare equivalent circuit for parallel-connected dual buck sub-topology.

[0123] FIG. 76 are the inductor current and voltage waveforms.

[0124] FIG. 77 is a diagram for proposed UCI controller for three-phase grid-connected inverter.

[0125] FIGS. 78aand 78bshow the waveforms for equivalent circuit model during one line cycle. FIG. 78ashows the line-line voltage and voltage V_Pand V_n. FIG. 78bshows the average inductor currents i_a=<i_La>, i_b=<i_Lb>, i_c=<i_Lc> and equivalent inductor currents <i_Lp> <i_Ln>.

[0126] FIG. 79 is a graph of the operation waveforms of the core section of the proposed UCI controller

[0127] FIG. 80 is a graph of the simulated inductor current waveforms for inverter in Fig. with proposed UCI controller.

[0128] The invention and its various embodiments can now be better understood by turning to the following detailed description of the preferred embodiments which are presented as illustrated examples of the invention defined in the claims. It is expressly understood that the invention as defined by the claims may be broader than the illustrated embodiments described below.

[0129] The disclosure is organized into three parts according to the function of the circuits. In each part, various embodiments will be given for the vector control mode and the bipolar operation mode.

[0130] PFC Rectifiers:

[0131] In its simplest terms the control method of the invention is based on one cycle control to realize a three-phase PFC function given by: $[\begin{array}{c}{i}_a\\ i_b\\ i_c\end{array}]=\frac{1}{R_e}.[\begin{array}{c}{v}_a\\ v_b\\ v_c\end{array}]\mathrm{or}{I}_s=\frac{1}{R_e}·V_s$

[0132] where i_a, i_b, i_cis are the three-phase source currents, v_a, v_band v_care the three-phase source voltages and R_eis the equivalent resistance by which the source is loaded; I_s, V_sare matrix vectors representing the input source current and voltage.

[0133] Every converter can be described by:

[0134] V_s=V_o·M(D)

[0135] where M(D) is a function of the duty cycle D, and is called the conversion matrix. Vo is the dc output voltage. This matrix is singular; thus many solutions are available. According to the invention the two equations above are combined so that the circuit realizes the function described by: $I_s=\frac{V_o}{R_e}·M\left(D\right)$

[0136] If an equivalent current sensing resistor, R_sis used to measure the source currents i_a, i_b, i_cthen the circuit performance can also be described by a control key equation: $R_s·I_s=\frac{R_s·V_o}{R_e}·M\left(D\right).$

[0137] Where $\frac{R_s·V_o}{R_e}$

[0138] can be expressed as V_m. Compared to the switching frequency, V_mvaries at much lower frequency, therefore it may be approximated by the output of a feedback compensator which is automatically adjusted whenever $\frac{R_s·V_o}{R_e}$

[0139] has a discrepancy compared to a reference value. The control key equation can be used with any boost-derived converter. For each solution of the control key equation, a control implementation is available based on one-cycle control. Those implementations can be roughly classified into two categories: (1) vector control mode as shown in FIG. 5 and bipolar control mode FIG. 6.

[0140] The control circuit, generally denoted by reference numeral 10 in FIG. 5, for the vector mode is comprised of an integrator 12 having an input with a timed reset circuit 15 and an output 14 coupled to the input of an adder 16. The adder 16 has another input coupled to the input 18 of the integrator 12. The output 22 of the adder 16 is coupled to two comparators 20. The other input to comparators 20 are derived from adders 17. Adders 17 in turn have an input from doublers or fixed multipliers 19 and are cross-connected to the inputs to fixed multipliers 19. Nodes 21 coupled to the outputs of low pass filters 23 are the inputs to fixed multipliers 19 and the cross-connection to adders 17. Low pass filters 23 are in turn coupled to the outputs of multiplexer 40. The inputs to multiplexer 40 are taken from the three phase inductor currents or switching currents i_a, i_band i_c.The outputs of comparators 20 are coupled to clocked flip-flops 38, whose outputs are coupled to a logic circuit 42. Logic circuit 42 and multiplexer 40 are coupled to and controlled by region selection circuit 30, whose operation will be made clear below. The output of logic circuit 42 are coupled back to rectifiers 24 to switch them again in a manner described in detail below in various embodiments. The output, V₀, from load 25 or rectifiers 24 is fed back to an subtractor 27 to generate the difference between a reference voltage, V_ref, and V₀. This difference, v(s), is coupled to a voltage loop compensator 29 and provided as the input to integrator 12.

[0141] The control circuit 10 for bipolar mode shown in FIG. 6 is comprised of an integrator 12 having an input 18 including a reset circuit. The output 14 of integrator 12 is coupled to three comparators 20. The other input to comparators 20 is provided from an input current processing circuit 31 described below. The input in turn to input current processing circuit 31 is derived from an inductor current or switching circuit 33. The outputs of comparators 20 are coupled to clocked flip-flops 38, whose outputs in turn are coupled to a logic circuit 42, again described below in various embodiments. Logic circuit 42 is coupled to and controlled by zero-crossing sensing network 35, which takes as its inputs the three phase voltage signals, V_a, V_band V_c. The remaining elements of FIG. 6 are similar to those in FIG. 5.

[0142] For vector control in FIG. 5, the control variable rotates in each 60° of line cycle. Therefore, the input voltages are sensed that are used to decouple the sensed current signals and direct the trigger signals to the correct switches. Again the detailed nature of the trigger signals and correct switches is described below for various embodiments. For bipolar control in FIG. 6, the control variables do not rotate, therefore no decoupling circuitry is required. In this case, voltage sensing may or may not be necessary.

[0143] A unified constant-frequency integration (UCI) control of the power factor corrected rectifiers 24 is thus described above based on one-cycle control. This control method employs an integrator 12 with reset as the core component to control the duty ratio of a PFC rectifier 24 to realize sinusoidal current draw from the AC source 26. Compared to previously proposed control methods, the UCI controller features a constant switching frequency, simpler circuitry, and no need for multipliers. Since the input three-phase currents, i_a, i_b, and i_c, are controlled cycle by cycle, they match the input three-phase voltages closely, thus a unity power factor and low total harmonic distortion (THD) are achieved. Experimental and simulation results show that the PFC has excellent input current waveform demonstrated using many rectifier topologies. PFC rectifiers 24 with an UCI controller provide a cost-effective, highly reliable, and flexible solution for power quality control. Due to the simplicity and generality of the circuitry, it is very suitable for industrial production.

[0144] A digital implementation of UCI control method can be realized by programming the control key equation and the supporting logic and linear functions into a digital signal processing (DSP) chip. The details of digital implementation of the various embodiments will not be further described, but it will be immediately evident according to the teachings of the invention what digital operations must be designed or programmed into the DSP's for each embodiment based on the equations and tables given for each embodiment below. Since control key equation and the supporting logic and linear functions are very simple, a low cost DSP can be employed.

[0145] The general approach of the invention to three-phase power factor corrected rectifiers with UCI control having been introduced above, turn now to a more detailed description of an unified constant-frequency integration (UCI) controller 10 for power-factor-correction (PFC) for three-phase rectifiers. As stated the UCI controller 10 can be used for vector or bipolar operation. Vector operated UCI controller 10 is derived from parallel or series connected dual boost subtopologies. Most types of the boost-derived three-phase rectifiers 24 can be decoupled into these topologies. For rectifiers based on a parallel-connected dual boost topology, all switches are switched at low current, which results in reduced current ratings. Vector operated UCI controller 10 usually features lower switching losses because only two-high frequency switches are switched during each 60° of the line cycle. In bipolar operation, all switches are switched at high frequency independently from the line voltage states, therefore, no region selection circuit and rotation circuits are necessary, so that the cost is reduced. However, the switching losses are higher compared to that of vector operation. UCI control can be realized by sensing the inductor currents or by sensing the switching currents. A bipolar operated UCI controller 10 can be applied to several topologies such as the standard six-switch boost bridge rectifier as well as the VIENNA rectifier.

[0146] Consider now the vector operated UCI controller 10 for a three-phase rectifier 24 based on parallel-connected dual boost topology. FIGS. 11a-11edepict a family of rectifiers 24 with a parallel-connected dual-boost topology using three AC inductors & a single dc-rail. FIG. 11ashows a conventional three-phase AC source 26 coupled through line inductance 32 into rectifier circuit 24 coupled to a tuned load 36, which rectifier circuit 24 is controlled by three-phase delta connected switches 34a.FIG. 11bshows a conventional three-phase AC source 26 coupled through line inductance 32 into rectifier circuit 24 coupled to a tuned load 36, which rectifier circuit 24 is controlled by three-phase star connected switches 34b.The three-phase H-bridge boost rectifier 24 in FIGS. 11cand 11dare similar except for an additional diode 38 in FIG. 11d.FIG. 11eis a 3-phase boost rectifier configured by switches 34eas an inverter network.

[0147] The normalized three-phase input voltage waveforms are shown in FIG. 12. During each 60° of the AC line cycle as shown in FIG. 12, all the rectifiers given in FIGS. 1a-11ecan be decoupled into a parallel-connected dual-boost topology. Consider for example rectifier 24 with delta-connected 3 φ switched shown in FIG. 11a.During the 60 degree region (0˜60°) of FIG. 12, switch S_cais off, while the other two switches S_aband S_bcare controlled so that the input inductor currents i_Laand i_Lcfollow the phase voltages V_aand V_crespectively. The equivalent circuit can be viewed as a parallel connected dual-boost topology as shown in FIG. 13a.In the next 60° (60°˜120°), switch S_bcis off, while switches S_aband S_caare controlled. The equivalent circuit along with its dual-boost topology is shown in FIG. 13b.These dual-boost topologies are equivalent for each 60° interval, while the circuit parameters of the dual-boost topology are different in each 60° interval as listed in Table I. Note there are two possibilities for the parameter combination, i.e. voltage V_pcan be either V_a−V_bor V_c−V_bduring interval (0˜60°), and so on. The first possibility is considered here, since the second one is similar.

[0148] For the dual-boost topology shown in FIG. 13a,four switching states are available for the two switches T_pand T_n. The switching states and inductor voltages are shown in Table II. The equivalent circuits of the dual-boost topology in all switching states are shown in FIG. 14.

[0149] where $[\begin{array}{c}{V}_p^{*}\\ V_n^{*}\\ V_t^{*}\end{array}]=[\begin{array}{cc}\frac{2}{3}& -\frac{1}{3}\\ -\frac{1}{3}& \frac{2}{3}\\ \frac{1}{3}& \frac{1}{3}\end{array}]·\left[\begin{array}{c}{V}_p\\ V_n\end{array}\right]$

[0150] and voltage ‘E’ equals the output voltage V₀.

[0151] For a three-phase PFC with a constant switching frequency, only two switching sequences are possible, i.e. states I, II, IV (condition d_p>d_n) or states I, III, IV (condition d_p<d_n) during each switching cycle, if trailing-edge modulation is performed. The voltage and current waveforms of the inductors are shown in FIG. 15 for the first switching sequence (d_p>d_n).

[0152] Based on the assumption that switching frequency is much higher than the line frequency, the inductor voltage-second balance is used, which yields $\begin{array}{cc}\{\begin{array}{c}{V}_p^{*}·d_n+\left(V_p^{*}+\frac{1}{3}·E\right)·\left(d_p-d_n\right)+\left(V_p^{*}-\frac{1}{3}·E\right)·\left(1-d_p\right)=0\\ V_n^{*}·d_n+\left(V_n^{*}-\frac{2}{3}·E\right)·\left(d_p-d_n\right)+\left(V_n^{*}-\frac{1}{3}·E\right)·\left(1-d_p\right)=0\\ V_t^{*}·d_n+\left(V_t^{*}-\frac{1}{3}·E\right)·\left(d_p-d_n\right)+\left(V_t^{*}-\frac{2}{3}·E\right)·\left(1-d_p\right)=0\end{array}& \left(1\right)\end{array}$

[0153] The following equation is true for a symmetrical three-phase system:

[0154] V_p^*+V_n^*−V_t^*=0   (2)

[0155] Combination of the equation (1), (2) and further simplification yield $\begin{array}{cc}\left[\begin{array}{c}1-d_p\\ 1-d_n\end{array}\right]=[\begin{array}{cc}2& 1\\ 1& 2\end{array}]·\left[\begin{array}{c}\frac{V_p^{*}}{E}\\ \frac{V_n^{*}}{E}\end{array}\right]& \left(3\right)\end{array}$

[0156] It can be verified that this equation is valid for the other switching states I, III, and IV (d_p<d_n) as well. In the steady sate, equation $\frac{E}{V_{\mathrm{in}}}=\frac{1}{1-D}$

[0157] is valid for a dc—dc boost converter operated in continuous conduction mode (CCM), where voltages V_in, E are the input and output voltages for the dc—dc boost converter respectively. Similarly Equation (3) gives an inherent relationships between the duty cycle and the input, output voltage for the parallel-connected dual-boost topology. This relationship is independent of the control scheme as long as the dual-boost topology operates in CCM.

[0158] A Three-Phase UCI PFC Controller

[0159] For the unity power factor three-phase PFC, the control goal is to force the switching-cycle average of the inductor currents in each phase to follow the sinusoidal phase voltages.

[0160] V_a=R_e·i_a; V_b=R_e·i_b; V_c=R_e·i_c  (4)

[0161] where R_eis the emulated resistance that reflects the load current.

[0162] This control goal can be realized by controlling the inductor currents i_Lpand i_Lnto follow the voltages V_p^*and V_n^*respectively. For example, during the interval (0-60°), assuming that V_p=V_a−V_band V_n=V_c−V_b, following equations are resulted: $\begin{array}{cc}\{\begin{array}{c}{V}_p^{*}=\frac{2}{3}·V_p-\frac{1}{3}·V_n=\frac{2}{3}·\left(V_a-V_b\right)-\frac{1}{3}·\left(V_c-V_b\right)=V_a\\ ⟨i_{\mathrm{Lp}}⟩=⟨i_{\mathrm{La}}⟩=i_a\\ V_n^{*}=\frac{2}{3}·V_n-\frac{1}{3}·V_p=\frac{2}{3}·\left(V_c-V_b\right)-\frac{1}{3}·\left(V_a-V_b\right)=V_c\\ ⟨i_{\mathrm{Ln}}⟩=⟨i_{\mathrm{Lc}}⟩=i_c\end{array}& \left(5\right)\end{array}$

[0163] Therefore, the control goal of three-phase PFC can be rewritten as $\begin{array}{cc}\{\begin{array}{c}{V}_p^{*}=R_e·⟨i_{\mathrm{Lp}}⟩\\ V_n^{*}=R_e·⟨i_{\mathrm{Ln}}⟩\end{array}& \left(6\right)\end{array}$

[0164] Substituting equation (6) into (3) yields $\begin{array}{cc}\left[\begin{array}{c}1-d_p\\ 1-d_n\end{array}\right]=\frac{R_e}{E·R_s}·R_s·[\begin{array}{cc}2& 1\\ 1& 2\end{array}]·\left[\begin{array}{c}⟨i_{\mathrm{Lp}}⟩\\ ⟨i_{\mathrm{Ln}}⟩\end{array}\right]& \left(7\right)\end{array}$

[0165] where R_sis the equivalent current sensing resistance (assuming all the current sensing resistances are equal to R_s).

[0166] Let $\begin{array}{cc}{V}_m=\frac{E·R_s}{R_e}& \left(8\right)\end{array}$

[0167] where V_mis the output of the voltage loop compensator, equation (7) can be rewritten as $\begin{array}{cc}{V}_m·\left[\begin{array}{c}1-d_p\\ 1-d_n\end{array}\right]=R_s·[\begin{array}{cc}2& 1\\ 1& 2\end{array}]·\left[\begin{array}{c}⟨i_{\mathrm{Lp}}⟩\\ ⟨i_{\mathrm{Ln}}⟩\end{array}\right]& \left(9\right)\end{array}$

[0168] It shows that three-phase PFC can be realized by controlling the duty ratio of switches T_pand T_nsuch that the linear combination of inductor currents <i_Lp> and <i_Ln> satisfy equation (9). These equations can be realized through an integrator 16 with reset and a linear network such as a clock (not shown), a comparator 20, a flip/flop 38 and adders 16. The control core circuitry needed to realize the equation (9) is shown in FIG. 16. Since the parallel-connected dual-boost topologies change their parameters such as i_Lp, i_Lnduring each 60° of line cycle, an input multiplexer circuit 40 and an output logic circuit 42 are required. Overall, the control block to realize the three-phase PFC function is shown in FIG. 16.

[0169] This control block includes four functional circuits:

[0170] (1). The region selection circuit 30 functions to determine the operational region as well as the corresponding equivalent circuit at a given time. The region selection function Δ(θ,i) is defined as:

[0171] Δ(θ,i)=u(θ−(i−1)·60)−u(θ−i·60)  (10).

[0172] It can be implemented by sensing the input voltage as shown in FIG. 17a.The waveforms of selection function are shown in FIG. 17b.

[0173] (2). The input multiplexer circuit 40 functions to select the input inductor current in order to configure the <i_Lp> and <i_Ln>. For example, the equivalent current i_Lpcan be expressed as

[0174] i_Lp=|i_La|·(Δ(1,θ)+Δ(6,θ))+|i_Lb|·(Δ(2,θ)+Δ(3,θ))++|i_Lc|·(Δ(4,θ)+Δ(5,θ)).

[0175] (3). The core circuit also includes an adder 16, comparators 20, and an integrator 16 with reset to realize the equation (9). The time constant of integrator 16 is set to equal the switching period. The operation waveforms are shown in FIG. 18.

[0176] (4). The output logic circuit 42 applies the equivalent switching control signal Q_pand Q_nto switches 34a-34ein the rectifier 24. The logic function varies from one type of rectifier 24 to another. The control signals for output switches 34a-34eare also functions of selection function Δ(i,θ) and control signal for switches T_pand T_n. For example, the control signal of switches S_abis given by: Q_ab=Q_p·(Δ(1,θ)+Δ(2,θ))+Q_n·(Δ(4,θ)+Δ(5,θ)); where Q_ab, Q_pand Q_nare control signals for switches S_ab, T_pand T_nrespectively. The implementation circuit is shown in FIG. 19.

[0177] The control algorithm for the boost PFC shown in FIG. 11ais listed in Table III. From the table, two conclusions can be drawn:

[0178] The current i_Lpand i_Lnare smaller than the phase current. Therefore, the switches S_ab, S_bc, and S_cahave lower current rating and lower conduction losses.

[0179] During each 60° region, only two switches T_pand T_nare operating at high frequency. Therefore, switching losses are expected to be lower.

[0180] Experimental verification

[0181] A 1.5 kW prototype of the three-phase rectifier with delta-connected 3 φ switches shown in FIG. 11awas built. In order to improve the efficiency and reduce switching noise, an active zero-voltage soft-switching circuit was employed. The experimental schematic is shown in FIG. 20. The parameters of the components are listed as follows: the inductors L_a=L_b=L_c=560 uH; the output capacitor C_o=470 uF; the main switches use MTY25N60E; and the main diodes d_ap, d_an, . . . d_cnand d_lare MUR3080; the auxiliary switch is MTY8N60E; the soft-switching inductor and capacitor are L_r=10 uH and C_r=3 nF; diodes d₂, d₃are MUR860. The experimental conditions are as follows: the input phase voltage is 120 Vrms; the output voltage is 475 VDC; switching frequency: 55 kHz; load resistance is 160 Ω; output power is 1.41 KW. The measured three-phase current waveforms are shown in FIG. 21. The phase A voltage and current are shown in FIG. 22. All the waveforms are measured by Tektronix oscilloscope TDS 520. The measured THD at full load and 120 Vrms input is 6.1%, while the phase voltages have a THD of 3.9% themselves.

[0182] Analysis And Simulation Of The Proposed Controller For The H-Bridge Boost Rectifier As Well As The Rest Of The Family

[0183] All the members in the parallel connected dual-boost family of FIGS. 11a-11ecan be controlled in a similar way. The H-bridge boost rectifier 24 shown in FIG. 11cis decoupled into the parallel-connected dual-boost topology as shown in FIGS. 13aand 13b.For example, during the 0˜60° interval, switches S_anand S_cnare controlled so that the inductor currents i_La, i_Lcfollow the phase voltages V_a, V_crespectively. The equivalent circuit for this interval and the parallel-connected dual boost topology are shown in FIG. 23. As a result, the H-bridge rectifier 24 can also be controlled by proposed controller shown in FIG. 16 with slight modification of the output logic circuit 42. The corresponding parameters are listed in the Table IV. Control algorithm is shown in Table V. The simulated current waveforms for the H-bridge rectifier are shown in FIG. 24. The simulated THD is 2.86% when the input voltage is purely sinusoidal.

[0184] The operation, the corresponding parameters, and control algorithm for rectifier shown in FIG. 11dare the same as that of the H-bridge rectifier shown in FIG. 11cin CCM operation. However, the operations are different when they get into DCM mode. The rectifier in FIG. 11ccan be designed to operate always in CCM by slightly modifying output logic circuits.

[0185] The rest of the family members, the boost rectifier with star-connected switches shown in FIG. 11band boost rectifier with inverter network shown in FIG. 11e,can also be decoupled into dual-boost topologies in each 60°. The parameter cross-references for these two rectifiers are listed in Table VI. The control algorithm can be derived in a similar way. The simulated waveforms for circuit in FIGS. 11band 11eare not listed here, since they are similar to the simulated waveforms shown in FIG. 24.

[0186] The Vector operated UCI controller for three-phase rectifier based on series-connected dual boost topology.

[0187] Consider now a family of three-phase rectifier with a series-connected dual-boost topology. A family of three-phase boost rectifiers with a split dc-rail is shown in FIG. 25. Normalized three-phase voltage waveforms are shown in FIG. 26. All of the rectifiers 24 depicted in FIGS. 25a-25ecan be de-coupled to series-connected dual-boost topologies during each 60° of line cycle. Take the VIENNA rectifier in FIG. 25aas an example. During (−30°˜30°) from FIG. 26, the bidirection switch S_ais turned on and the other two switches S_band S_care controlled at high frequency so that the average inductor currents i_Lb, i_Lcfollow the phase voltages V_band V_c. The equivalent circuit as well as its series-connected dual-boost topology is shown in FIGS. 27aand b.

[0188] The waveforms of normalized voltage V_pand V_nduring −30°˜30° are shown in FIG. 28. The cross-reference of topology parameters for (−30°˜330°) are listed in Table VII.

[0189] For series-connected dual-boost topology in FIG. 27b,switching states of Tpand T_nhave four possible combinations. The switching states and voltages across the inductors are listed in Table VIII. The equivalent circuits are shown in FIG. 29.

[0190] Where $V_p^{*}=\frac{2}{3}·V_p+\frac{1}{3}·V_n;$ $V_n^{*}=\frac{1}{3}·V_p+\frac{2}{3}·V_n;$ $V_t^{*}=\frac{1}{3}·\left(V_n-V_p\right).$

[0191] For constant switching frequency control, two switching sequences are possible during each switching cycle, i.e. state I, II, IV (d_p<d_n) or I, III, IV (d_p>d_n), where d_p, d_nare duty-ratios of switches T_p, T_nrespectively. These state sequence will last a certain period of time according to the status of the input voltage and the load. For example, the switching sequence I, II, IV is kept for a certain time. The inductor waveforms for this period are shown in FIG. 30.

[0192] Assuming that the switching frequency is much higher than the line frequency, the series-connected dual-boost topology can be viewed as a dc—dc converter. Therefore, the inductor voltage-second balance method can be applied to the inductor voltage waveforms shown in FIG. 30, which yields $\begin{array}{cc}\{\begin{array}{c}{V}_p^{*}·d_n+\left(V_p^{*}-\frac{1}{3}·E\right)·\left(d_p-d_n\right)+\left(V_p^{*}-E\right)·\left(1-d_p\right)=0\\ V_n^{*}·d_n+\left(V_n^{*}-\frac{2}{3}·E\right)·\left(d_p-d_n\right)+\left(V_n^{*}-E\right)·\left(1-d_p\right)=0\\ V_t^{*}·d_n+\left(V_t^{*}-\frac{1}{3}·E\right)·\left(d_p-d_n\right)+V_t^{*}·\left(1-d_p\right)=0\end{array}& \left(11\right)\end{array}$

[0193] Simplifying equation (11) gives $\begin{array}{cc}\{\begin{array}{c}2·d_p+d_n=3·\left(1-\frac{V_p^{*}}{E}\right)\\ d_p+2·d_n=3·\left(1-\frac{V_n^{*}}{E}\right)\\ d_p-d_n=3·\frac{V_t^{*}}{E}\end{array}& \left(12\right)\end{array}$

[0194] For a symmetrical three-phase system, the following equation is true:

[0195] V_p^*−V_n^*+V_t^*=0   (13)

[0196] Therefore, the equation (11) can be further simplified as $\begin{array}{cc}\left[\begin{array}{c}1-d_p\\ 1-d_n\end{array}\right]=\frac{1}{E}·[\begin{array}{cc}2& -1\\ -1& 2\end{array}]·\left[\begin{array}{c}{V}_p^{*}\\ V_n^{*}\end{array}\right]& \left(14\right)\end{array}$

[0197] It can be verified that this equation is also valid for the other sequence I, III and IV (d_p>d_n). Equation (14) gives the inherent relationship between duty cycles d_p, d_nand input, output of the series-connected dual-boost topologies when it operates in Continuous Conduction Mode (CCM).

[0198] UCI three-phase PFC controller for rectifier based on series-connected dual boost topology

[0199] For a unity power factor three-phase PFC, the control goal is to force the average inductor current in each phase to follow the sinusoidal phase voltage.

[0200] V_a=R_e·i_a; V_b=R_e·i_b; R_e·i_c

[0201] where R_eis the emulated resistance. This control goal can be realized by controlling the inductor currents i_Lpand i_Lnto follow the voltage V_p^*and V_n^*respectively. For example, during region −30°˜30°, following equations hold $\begin{array}{cc}\{\begin{array}{c}{V}_p^{*}=\frac{2}{3}·V_p+\frac{1}{3}·V_n=\frac{2}{3}·\left(V_c-V_a\right)+\frac{1}{3}·\left(V_a-V_b\right)=V_c\\ ⟨i_{\mathrm{Lp}}⟩=⟨i_{\mathrm{Lc}}⟩=i_c\\ V_n^{*}=\frac{1}{3}·V_p+\frac{2}{3}·V_n=\frac{1}{3}·\left(V_c-V_a\right)+\frac{2}{3}·\left(V_a-V_b\right)=-V_b\\ ⟨i_{\mathrm{Ln}}⟩=-⟨i_{\mathrm{Lb}}⟩=-i_b\end{array}& \left(15\right)\end{array}$

[0202] With the assumption that the system is symmetrical, the current <i_t> will automatically follow the voltage V_t^*according to equation (3). The control goal of three-phase PFC can be rewritten as $\begin{array}{cc}\{\begin{array}{c}{V}_p^{*}=R_e·⟨i_{\mathrm{Lp}}⟩\\ V_n^{*}=R_e·⟨i_{\mathrm{Ln}}⟩\end{array}& \left(16\right)\end{array}$

[0203] Substituting equation (16) into (14) yields $\begin{array}{cc}\left[\begin{array}{c}1-d_p\\ 1-d_n\end{array}\right]=\frac{R_e}{E·R_s}·R_s·\left[\begin{array}{cc}2& -1\\ -1& 2\end{array}\right]·\left[\begin{array}{c}⟨i_{\mathrm{Lp}}⟩\\ ⟨i_{\mathrm{Ln}}⟩\end{array}\right]& \left(17\right)\end{array}$

[0204] where R_sis the equivalent current sensing resistance.

[0205] Set $\begin{array}{cc}{V}_m=\frac{E·R_s}{R_e}& \left(18\right)\end{array}$

[0206] where V_mis the output of the voltage loop compensator. Equation (17) can be rewritten as $\begin{array}{cc}{V}_m·\left[\begin{array}{c}1-d_p\\ 1-d_n\end{array}\right]=R_s·\left[\begin{array}{cc}2& -1\\ -1& 2\end{array}\right]·\left[\begin{array}{c}⟨i_{\mathrm{Lp}}⟩\\ ⟨i_{\mathrm{Ln}}⟩\end{array}\right]& \left(19\right)\end{array}$

[0207] This shows that the control of three-phase PFC can be realized by controlling the duty ratio of switches T_pand T_nso that the equation (19) is satisfied. This control core function can be realized by one integrator with reset along with a few logic components as shown in the control core block of FIG. 31. To achieve power factor correction in each line cycle, an input multiplexer and output logic circuits are needed to rotate the control core function corresponding to the input voltage V_p, V_nas shown in Table VII. Overall, the proposed control core is shown in FIG. 31, where Δ(θ,i) is the region selection function: Δ(θ,i)=u(θ−(i−1)·60+30)−u(θ−i·60+30), i=1, 2, . . . 6. This function can be realized by sensing input line-line voltage. The schematic of implementation as well as the waveforms for Δ(θ,i) are shown in FIGS. 32aand 32b.

[0208] The control algorithm for VIENNA rectifier is listed in Table IX. The predicted voltage waveforms V_p, V_nand inductor waveform for series-connected dual-boost topology during each line cycle are shown in FIG. 33.

[0209] The simulated current waveforms for VIENNA rectifier with the proposed controller are shown in FIG. 34. Simulation condition is as follows: the input voltage V_g(rms)=120 V; the output voltage V_o=600 V; the output power is 5 KW, the input inductor L=2 mH, and the switching frequency is 10 KHz. The simulated THD is 4.7%.

[0210] Experimental verification

[0211] A 400 watts experimental-circuit of the three-phase VIENNA rectifier shown in FIG. 25awas built to prove the concept. The experimental conditions is as follows: the input voltage is 54 Vrms; the output voltage is 400 V; the output power is 400 watts; the switching frequency is 55 KHz; and the input AC inductance is 560 μH. Three-phase inductor current waveforms and phase A voltage and current waveforms are shown in FIG. 35 and FIG. 36 respectively. All the waveforms were measured by Tektronics scope TDS520. Experimental results indicate that dynamic transient exists when rectifier rotates its connection from one 60° to another, which causes additional distortion. The measured THD was 8.4%, while the phase voltages have a THD of 3.9% themselves. Further studies were followed by simulation and it shows that the THD can be reduced by damping the transient with increased inductance. It was observed that the voltages across two output capacitors can be automatically balanced by the proposed controller. For the series-connected dual-boost topology shown in FIG. 37, the average inductor currents i_Lpand i_Lnare inversely proportional to the voltage across the capacitors, which is one of important features of this control approach. Therefore, the current can be automatically adjusted so that the output voltage is evenly distributed in the two output capacitors.

[0212] Extension of the PFC controller to other rectifier topologies with a split dc rail

[0213] The proposed controller in FIG. 31 can be extended to other topologies in the family shown in FIG. 25 with slight modification of the output logic, while the control core, the input multiplexer circuit, the region selection functions will remain unchanged. The output logic functions for the rectifiers shown in FIGS. 25band 25care listed in Table X. The switches S_a, S_band S_cin these two rectifiers are low frequency switches (operated at twice of the line frequency) and conduct a small portion of the phase current. Switches T_pand T_nare switching frequency switches. The control signal for these two switches are Q_pand Q_n. For the asymmetrical rectifier in FIG. 25cwith proposed control approach, the control algorithm will be exactly same except that the time constant of integrator equals one half of the switching period, i.e. τ=T_s/2.

[0214] Simulated waveforms for the rectifier in FIG. 25bare shown in FIG. 37. The simulation results for the rectifier in FIG. 25cis similar to FIG. 37. The simulated THD is below 5%.

[0215] Applying the analytic approach above relating to PFC controllers based on series-connected dual boost topologies yields the control equation (20). $\begin{array}{cc}\left[\begin{array}{c}{V}_m·\left(1-D_p\right)\\ V_m·\left(1-D_n\right)\end{array}\right]=R_s·[\begin{array}{cc}2& -1\\ -1& 2\end{array}]·\left[\begin{array}{c}⟨i_{\mathrm{Lp}}⟩\\ ⟨i_{\mathrm{Ln}}⟩\end{array}\right]& \left(20\right)\end{array}$

[0216] Equation (20) is exactly the same as the equation (19). Therefore, the proposed controller is also applicable for the topologies shown in FIG. 25(d). However, since dc inductors are the same as the equivalent inductors L_pand L_n, the input multiplexer circuit is eliminated. The algorithm for these two topologies is shown in Table Xl below.

[0217] The duty-ratio calculation equation for the asymmetrical rectifier in FIG. 25(e) is the same as that of FIG. 25(d), except that the time constant of integrator equals one half of the switching period, i.e. τ=T_s/2. Simulated current waveforms for the rectifier of FIG. 25(d) is shown in FIG. 37. The simulated inductor waveforms of FIG. 25(e) are similar to that of FIG. 37. The simulation condition is as follows: the input voltage V_g(rms)=120 V; the output voltage V_o=600 V; the output power is 5 KW, the input inductor L=5 mH, the switching frequency is 10 KHz. The simulated THD is below 5%.

[0218] Bipolar operated UCI controller for 3-phase PFC

[0219] Standard three-phase six-switch bridge rectifier with Bipolar operated UCI control

[0220] General relationship between duty ratios of switches and input phase voltage

[0221] A six-switch standard bridge boost rectifier is shown in FIG. 40(a). If the converter operates in continuous conduction mode (CCM), the average voltages at the node A, B, C refer to node N are given by: $\begin{array}{cc}\{\begin{array}{c}{V}_{\mathrm{AN}}=\left(1-D_{\mathrm{an}}\right)·E\\ V_{\mathrm{BN}}=\left(1-D_{\mathrm{bn}}\right)·E\\ V_{\mathrm{CN}}=\left(1-D_{\mathrm{cn}}\right)·E\end{array}& \left(21\right)\end{array}$

[0222] where D_an, D_bn, D_cnare the duty ratios for switches S_an, S_bn, S_cn. The switch in each bridge arm is controlled complementary; i.e. the duty ratios for switch S_ap, S_bp, S_cpare 1−D_an; 1−D_bn; 1−D_cnrespectively.

[0223] The equivalent average model for rectifier in FIG. 40 (a) is shown in FIG. 40 (b). The average vector voltages at nodes A, B, C refer to the neutral point “O” equal the phase vector voltages minus the voltage across the inductors L_a, L_b, L_cwhich is given by $\begin{array}{cc}\{\begin{array}{c}{\stackrel{.}{V}}_{\mathrm{AO}}={\stackrel{.}{V}}_a-j\mathrm{wL}·{\stackrel{.}{i}}_{\mathrm{La}}\\ {\stackrel{.}{V}}_{\mathrm{BO}}={\stackrel{.}{V}}_b-j\mathrm{wL}·{\stackrel{.}{i}}_{\mathrm{Lb}}\\ {\stackrel{.}{V}}_{\mathrm{CO}}={\stackrel{.}{V}}_c-j\mathrm{wL}·{\stackrel{.}{i}}_{\mathrm{Lc}}\end{array}& \left(22\right)\end{array}$

[0224] where L is inductance of input inductor and w is line angular frequency. The items {right arrow over (i)}_La, {right arrow over (i)}_Lb, {right arrow over (i)}_Lcare inductor current vectors. The inductances L_a, L_b, L_care very small, since they are switching frequency inductors. For a 60 Hz utility system, the voltages across the inductances jwL·{right arrow over (i)}_Laare very small comparing with the phase voltages, thus can be neglected. Therefore, the equation (22) can be approximately simplified as $\begin{array}{cc}\{\begin{array}{c}{\stackrel{.}{V}}_{\mathrm{AO}}\approx {\stackrel{.}{V}}_a\\ {\stackrel{.}{V}}_{\mathrm{BO}}\approx {\stackrel{.}{V}}_b\\ {\stackrel{.}{V}}_{\mathrm{CO}}\approx {\stackrel{.}{V}}_c\end{array}\Rightarrow \{\begin{array}{c}{V}_{\mathrm{AO}}\approx V_a\\ V_{\mathrm{BO}}\approx V_b\\ V_{\mathrm{CO}}\approx V_c\end{array}& \left(23\right)\end{array}$

[0225] For three-phase system, we have

[0226] V_a+V_b+V_c=0   (24)

[0227] Then we get

[0228] V_AO+V_BO+V_CO=0   (25)

[0229] The voltages at nodes A, B, C refer to neutral point are given by $\begin{array}{cc}\{\begin{array}{c}{V}_{\mathrm{AO}}=V_{\mathrm{AN}}+V_{\mathrm{NO}}\\ V_{\mathrm{BO}}=V_{\mathrm{BN}}+V_{\mathrm{NO}}\\ V_{\mathrm{CO}}=V_{\mathrm{CN}}+V_{\mathrm{NO}}\end{array}& \left(26\right)\end{array}$

[0230] Combination of equation (25) and (26) yields $\begin{array}{cc}{V}_{\mathrm{NO}}=-\frac{1}{3}·\left(V_{\mathrm{AN}}+V_{\mathrm{BN}}+V_{\mathrm{CN}}\right)& \left(27\right)\end{array}$

[0231] Substituting equation (27) and (23) into (26) results in $\begin{array}{cc}\{\begin{array}{c}{V}_{\mathrm{AO}}=V_{\mathrm{AN}}+V_{\mathrm{NO}}=V_{\mathrm{AN}}-\frac{1}{3}·\left(V_{\mathrm{AN}}+V_{\mathrm{BN}}+V_{\mathrm{CN}}\right)\approx V_a\\ V_{\mathrm{BO}}=V_{\mathrm{BN}}+V_{\mathrm{NO}}=V_{\mathrm{BN}}-\frac{1}{3}·\left(V_{\mathrm{AN}}+V_{\mathrm{BN}}+V_{\mathrm{CN}}\right)\approx V_b\\ V_{\mathrm{CO}}=V_{\mathrm{CN}}+V_{\mathrm{NO}}=V_{\mathrm{CN}}-\frac{1}{3}·\left(V_{\mathrm{AN}}+V_{\mathrm{BN}}+V_{\mathrm{CN}}\right)\approx V_c\end{array}& \left(28\right)\end{array}$

[0232] Combination of equation (21) and (28) yields the relationship between duty ratio D_an, D_bn, D_cnand voltage V_a, V_b,V_cwhich is as follows: $\begin{array}{cc}\left[\begin{array}{ccc}-\frac{2}{3}& \frac{1}{3}& \frac{1}{3}\\ \frac{1}{3}& -\frac{2}{3}& \frac{1}{3}\\ \frac{1}{3}& \frac{1}{3}& -\frac{2}{3}\end{array}\right]·\left[\begin{array}{c}{d}_{\mathrm{an}}\\ d_{\mathrm{bn}}\\ d_{\mathrm{cn}}\end{array}\right]=\frac{1}{E}·\left[\begin{array}{c}{V}_a\\ V_b\\ V_c\end{array}\right]& \left(29\right)\end{array}$

[0233] The equation illustrates the inherent relationship between average duty ratio of switches and the line voltage under CCM condition.

[0234] Proposed Bipolar UCI controller

[0235] Since the matrix of equation (29) is singular, equation (29) has no unique solution. With constrain of unity power-factor correction, many solutions are available. One possible solution for equation (29) is as follows: $\begin{array}{cc}\{\begin{array}{c}{d}_{\mathrm{an}}=K_1+K_2·\frac{V_a}{E}\\ d_{\mathrm{bn}}=K_1+K_2·\frac{V_b}{E}\\ d_{\mathrm{cn}}=K_1+K_2·\frac{V_c}{E}\end{array}& \left(30\right)\end{array}$

[0236] Substituting above equation into (29) results in:

[0237] Parameter K₂=−1 and K₁can be any number. Because duty ratio should be less than unity and greater than zero, we have the following limitation: $\begin{array}{cc}0\le d_{\mathrm{an}}=K_1-\frac{V_a}{E}\le 1& \left(31\right)\end{array}$

[0238] Define $\begin{array}{cc}M=\frac{E}{\sqrt{2}·V_i}.& \left(32\right)\end{array}$

[0239] The range of K₁is limited by $\begin{array}{cc}\frac{1}{M}\le K_1\le 1-\frac{1}{M}& \left(33\right)\end{array}$

[0240] The equation (30) can be rewritten as $\begin{array}{cc}\{\begin{array}{c}\frac{V_a}{E·K_1}=1-\frac{d_{\mathrm{an}}}{K_1}\\ \frac{V_b}{E·K_1}=1-\frac{d_{\mathrm{bn}}}{K_1}\\ \frac{V_c}{E·K_1}=1-\frac{d_{\mathrm{cn}}}{K_1}\end{array}& \left(34\right)\end{array}$

[0241] For three-phase rectifier with unity-power-factor, we assume $\begin{array}{cc}\{\begin{array}{c}{V}_a=R_e·i_a\\ V_a=R_e·i_a\\ V_a=R_e·i_a\end{array}& \left(35\right)\end{array}$

[0242] where R_eis emulated resistance.

[0243] Combination of above equation and (34) yields: $\begin{array}{cc}\{\begin{array}{c}\frac{R_e}{E·K_1·R_S}·R_S·i_a=1-\frac{d_{\mathrm{an}}}{K_1}\\ \frac{R_e}{E·K_1·R_S}·R_S·i_b=1-\frac{d_{\mathrm{bn}}}{K_1}\\ \frac{R_e}{E·K_1·R_S}·R_S·i_c=1-\frac{d_{\mathrm{cn}}}{K_1}\end{array}& \left(36\right)\end{array}$

[0244] where parameter R_sis the equivalent current sensing resistor.

[0245] Define $\begin{array}{cc}{V}_m=\frac{E·R_s·K_1}{R_e}& \left(37\right)\end{array}$

[0246] where V_mis the output of voltage compensator.

[0247] The equation (36) can be simplified as $\begin{array}{cc}\{\begin{array}{c}{R}_s·i_a=V_m-V_m\frac{D_{\mathrm{an}}}{K_1}\\ R_s·i_b=V_m-V_m\frac{D_{\mathrm{bn}}}{K_1}\\ R_s·i_c=V_m-V_m\frac{D_{\mathrm{cn}}}{K_1}\end{array}& \left(38\right)\end{array}$

[0248] Replacing the i_a, i_b, i_cwith peak, average inductor current or switching current results in two different control approaches.

[0249] Proposed UCI PWM controller by sensing inductor currents

[0250] (a). Schematic.

[0251] Replacing the i_a, i_b, i_cin equation (38) with peak or average inductor current, we get the control key equation. $\begin{array}{cc}\{\begin{array}{c}{R}_s·i_{\mathrm{Lapk}}=V_m-V_m\frac{D_{\mathrm{an}}}{K_1}\\ R_s·i_{\mathrm{Lbpk}}=V_m-V_m\frac{D_{\mathrm{bn}}}{K_1}\\ R_s·i_{\mathrm{Lcpk}}=V_m-V_m\frac{D_{\mathrm{cn}}}{K_1}\end{array}\mathrm{or}\{\begin{array}{c}{R}_s·⟨i_{\mathrm{La}}⟩=V_m-V_m\frac{D_{\mathrm{an}}}{K_1}\\ R_s·⟨i_{\mathrm{Lb}}⟩=V_m-V_m\frac{D_{\mathrm{bn}}}{K_1}\\ R_s·⟨i_{\mathrm{Lc}}⟩=V_m-V_m\frac{D_{\mathrm{cn}}}{K_1}\end{array}& \left(39\right)\end{array}$

[0252] The above equation can be implemented with an integrator with reset as shown in FIG. 41(a). The operation waveforms are shown in FIG. 41(b); where Q_ap, Q_an. . . Q_cnare drive signal for switches S_ap, S_an. . . S_cnrespectively. The time constant of the integrator is set to be τ=K₁·T_S; where T_sis switching period. For instance, K₁may be chosen as 0.5. In that case, the carrier $V_m-V_m·\frac{t}{K_1·T_S}=V_m·\left(1-2·\frac{t}{T_S}\right)$

[0253] is symmetric to the x axis.

[0254] The schematic for the proposed 3-phase PFC controller is shown in FIG. 41(a). By controlling the duty ratio to follow the relationship shown in (39), three-phase PFC can be implemented. The 3-phase PFC controller in FIG. 41ais composed of 3 flip-flops and one integrator with reset as well as some linear components. No voltage sensors and multipliers are required. In order to prevent the short circuit, dead time for complementary switches such as S_an, S_apneed to be considered.

[0255] (b) PSPICE simulation verification.

[0256] In order to verify the idea, a PSPICE simulation was conducted. The simulation conditions are as follows: Input phase voltage 120 Vrms, Output voltage E=500 v; L=3 mH, f=10 KHz, P=5 KW . The conversion ration $M=\frac{V_o}{\sqrt{2}·V_{\mathrm{grms}}}=2.946.$

[0257] The parameter K₁is limited in the range of (0.339, 0.660) according to equation (33). In this simulation, parameter K₁=0.4. The simulation results for the 3-phase bridge rectifier in FIG. 41(a) with proposed controller are given in FIG. 42. The measured total harmonic distortion (THD) is below 5%. Simulation results verified the theoretical analysis.

[0258] Proposed UCI PWM controller for 6-switch bridge rectifier by sensing switching current

[0259] Recall the equation (39) and considering the phase A, we have $V_m·\left(1-\frac{D_{\mathrm{an}}}{K_1}\right)=R_s·⟨i_{\mathrm{La}}⟩$

[0260] For 3-phase rectifier with unity power-factor, we assume the input inductor current follows the input phase voltage. By setting K₁=0.5, the above equation can be rewritten as $\{\begin{array}{c}\begin{array}{c}{V}_m·\left(1-2·D_{\mathrm{an}}\right)=R_s·⟨i_{\mathrm{La}}⟩;D_{\mathrm{ap}}=1-D_{\mathrm{an}}{V}_a>0;⟨i_{\mathrm{La}}⟩>0\\ V_m·\left(2·D_{\mathrm{an}}-1\right)=V_m·\left(1-2·D_{\mathrm{ap}}\right)=R_s·\left(-⟨i_{\mathrm{La}}⟩\right);\end{array}\\ D_{\mathrm{ap}}=1-D_{\mathrm{an}}{V}_a\le 0;⟨i_{\mathrm{La}}⟩\le 0\end{array}$

[0261] The above equation can be simplified as $\begin{array}{cc}\{\begin{array}{c}{V}_m·\left(1-2·D_a\right)=R_s·\left|⟨i_{\mathrm{La}}⟩\right|\\ D_{\mathrm{an}}=\{\begin{array}{c}{D}_a;V_a>0\\ 1-D_a;V_a\le 0\end{array}{D}_{\mathrm{ap}}=\{\begin{array}{c}1-D_a;V_a>0\\ D_a;V_a\le 0\end{array}\end{array}& \left(40\right)\end{array}$

[0262] Assuming input current is positive, i.e, V_a>0; i_a>0, when switch S_anis on, the inductor current flows into switch S_an. When switch S_anis off, the inductor current flows through diode D_ap. In this case, switch S_apcan be turned on at zero voltage condition. Therefore, S_anis “active” switch and S_apis inactive switch. Likewise, under the condition V_a≦0; i_a≦0, S_anis “inactive” switch and S_apis “active” switch. In each switching cycle, there is only one “active” switch is controller in each bridge arm. The loss for “inactive” switch is very small due to the zero-voltage turn-on condition.

[0263] If the converter operates in CCM, the inductor current can be expressed with duty ratio and switching current. The relationship between the switching current and is inductor current for phase A is illustrated in FIG. 43; where <i_Sapn> is equivalent average switching current for switches S_apand S_an.

[0264] The inductor current is a function of switching current and duty ratio, which is given by $\begin{array}{cc}\{\begin{array}{c}{V}_a>0;⟨i_{\mathrm{La}}⟩·D_{\mathrm{an}}=⟨i_{\mathrm{San}}⟩\\ V_a\le 0;\left(-⟨i_{\mathrm{La}}⟩\right)·D_{\mathrm{ap}}=⟨i_{\mathrm{Sap}}⟩\end{array}& \left(41\right)\end{array}$

[0265] Combination of the above equation and equation (40) yields

[0266] |<i_La>|·D_a=<i_Sapn>  (42)

[0267] where <i_sapn> is equivalent average switching current as shown in FIG. 43

[0268] Combination of equation (42); (40) and equation (39) yields $\begin{array}{cc}\{\begin{array}{c}{R}_s·⟨i_{\mathrm{Sapn}}⟩=V_m·\left(1-2·D_a\right)·D_a\\ R_s·⟨i_{\mathrm{Sbpn}}⟩=V_m·\left(1-2·D_b\right)·D_b\\ R_s·⟨i_{\mathrm{Scpn}}⟩=V_m·\left(1-2·D_c\right)·D_c\end{array}& \left(43\right)\end{array}$

[0269] This equation shows that the three-phase PFC for the 6-switch boost bridge rectifier can be implemented by sensing switching current. The schematic of control block is shown in FIG. 44; where Q_ahas the duty ratio D_a. The simulation results are shown in FIG. 45. The simulation condition is same as that described above. The measured THD is below 5%.

[0270] Other variations of bridge boost rectifier with proposed controller

[0271] The proposed controller is applicable to other variations of the bridge topology. Two examples are shown in FIGS. 46aand 46b.One is 6-switch bridge rectifier with dc-diode; the other is three-level boost rectifier. The proposed controller can be applied to these two topologies without any changes. Although the relationship between the duty ratio and input voltage in equation (29) is not completely satisfied in FIG. 46(a), the proposed controller still can guarantee good input current waveforms. The simulation results for the rectifier in FIG. 46(a) with proposed controller by sensing inductor current is given in FIG. 47. The measured THD at 4 KW output is 1.3% and 15% at the 300 W. Although THD is slight higher comparing with the topology in FIG. 44, the performance can still meet the IEC 1000-3-2 standard. Further more, because the dc diode prevents the short through in bridge, the reliability is higher. The three-level bridge rectifier in FIG. 46(b) is suitable for high power and high voltage applications because the voltage stress of each switch is half of the output voltage. The simulation results for three-level rectifier is similar to that of the 6-switch rectifier in FIG. 44 and simulation results are not included here.

[0272] 3-phase bridge rectifier with reduced switch count and Bipolar operated UCI control

[0273] The 3-phase rectifier topology with reduced switch count is shown in FIG. 48. With similar approximation in 0, the relationship shown in equation (28) still exists for the topology in Fig. Rewritten equation (28) yields: $\begin{array}{cc}\{\begin{array}{c}{V}_a\approx V_{\mathrm{AN}}-\frac{1}{3}·\left(V_{\mathrm{AN}}+V_{\mathrm{BN}}+V_{\mathrm{CN}}\right)\\ V_b\approx V_{\mathrm{BN}}-\frac{1}{3}·\left(V_{\mathrm{AN}}+V_{\mathrm{BN}}+V_{\mathrm{CN}}\right)\\ V_c\approx V_{\mathrm{CN}}+V_{\mathrm{NO}}=V_{\mathrm{CN}}-\frac{1}{3}·\left(V_{\mathrm{AN}}+V_{\mathrm{BN}}+V_{\mathrm{CN}}\right)\end{array}& \left(44\right)\end{array}$

[0274] For three-phase system, we have V_a+V_b+V_c=0; therefore, the above equation can be simplified as $\begin{array}{cc}\left[\begin{array}{c}{V}_a\\ V_b\end{array}\right]=\left[\begin{array}{ccc}\frac{2}{3}& -\frac{1}{3}& -\frac{1}{3}\\ -\frac{1}{3}& \frac{2}{3}& -\frac{1}{3}\end{array}\right]·\left[\begin{array}{c}{V}_{\mathrm{AN}}\\ V_{\mathrm{BN}}\\ V_{\mathrm{CN}}\end{array}\right]& \left(45\right)\end{array}$

[0275] For the rectifier in Fig., the average voltage at node A, B, C referring node N are given by $\begin{array}{cc}\{\begin{array}{c}{V}_{\mathrm{AN}}=\left(1-D_{\mathrm{an}}\right)·E\\ V_{\mathrm{BN}}=\left(1-D_{\mathrm{bn}}\right)·E\\ V_{\mathrm{CN}}=\frac{E}{2}\end{array}& \left(46\right)\end{array}$

[0276] Where D_an, D_bnare duty ratios for switches S_an, S_bnrespectively; the duty ratios of switches S_ap, S_bpare the complementary of duty ratio D_an, D_bn, i.e. D_ap=1−D_an; D_bp=1−D_bn.

[0277] Substitution of the equation (46) into equation (45) yields $\begin{array}{cc}\left[\begin{array}{c}1-2·D_{\mathrm{an}}\\ 1-2·D_{\mathrm{bn}}\end{array}\right]=\frac{2}{E}·\left[\begin{array}{c}2·V_a+V_b\\ V_a+2·V_b\end{array}\right]& \left(47\right)\end{array}$

[0278] For 3-phase PFC with unity power factor, we have $\begin{array}{cc}\{\begin{array}{c}{V}_a=R_e·i_a\\ V_b=R_e·i_b\end{array}& \left(48\right)\end{array}$

[0279] where R_eis the emulated resistance.

[0280] The equation (47) can be simplified as: $\begin{array}{cc}{V}_m·\left[\begin{array}{c}1-2·D_{\mathrm{an}}\\ 1-2·D_{\mathrm{bn}}\end{array}\right]=R_s·\left[\begin{array}{cc}2& 1\\ 1& 2\end{array}\right]·\left[\begin{array}{c}{i}_a\\ i_b\end{array}\right]& \left(49\right)\end{array}$

[0281] where $\begin{array}{cc}{V}_m=\frac{E·R_s}{2·R_e}& \left(50\right)\end{array}$

[0282] The parameter V_mis the output of the voltage error compensator.

[0283] Replace the i_a, i_bwith peak or average inductor current results in the control key equation $\begin{array}{cc}{V}_m·\left[\begin{array}{c}1-2·D_{\mathrm{an}}\\ 1-2·D_{\mathrm{bn}}\end{array}\right]=R_s·\left[\begin{array}{cc}2& 1\\ 1& 2\end{array}\right]·\left[\begin{array}{c}⟨i_{\mathrm{La}}⟩\\ ⟨i_{\mathrm{Lb}}⟩\end{array}\right]\mathrm{or}{V}_m·\left[\begin{array}{c}1-2·D_{\mathrm{an}}\\ 1-2·D_{\mathrm{bn}}\end{array}\right]=R_s·\left[\begin{array}{cc}2& 1\\ 1& 2\end{array}\right]·\left[\begin{array}{c}{i}_{\mathrm{Lapk}}\\ i_{\mathrm{Lbpk}}\end{array}\right]& \left(51\right)\end{array}$

[0284] The duty ratio of above equation can be solved with integrator with resets. The schematic is shown in FIG. 49 and operation waveforms are shown in FIG. 50.

[0285] Simulated inductor current waveforms are shown in FIG. 51. The simulation conditions are as follows: Input phase voltage 120 Vrms, Output voltage E=600 v; L=3 mH, f=10 KHz, P=6 KW. The measured total harmonic distortion (THD) is 3.2%.

[0286] The topology shown in FIG. 48 can be seen as a combination of two single-phase rectifiers with half bridge as shown in FIGS. 52aand 52b.The input voltage for single-phase PFC is line—line voltage such as V_ab, V_bc. The input inductor currents follow the phase voltage V_aor V_b. By applying inductor voltage-second balance method, we can get the same control key equation as shown in (51). The advantage of this rectifier is less switches and inductor counts. The disadvantage is that the high voltage stress of the switch. The output voltage is more than twice of the line—line voltage, i.e $\frac{E}{2}\ge V_{\mathrm{ab}}=\sqrt{3}·\sqrt{2}·V_{\mathrm{grms}}·\sin \left(\mathrm{wt}\right).$

[0287] The voltage stress of the switch that equals E is higher comparing with the 6-switch bridge rectifier. Furthermore, the current flowing into the output capacitor has twice line frequency ripple; which results in larger capacitance. Nevertheless, it is a low cost option for 3-phase PFC.

[0288] VIENNA rectifier with Bipolar operated UCI control.

[0289] One of the promising 3-phase rectifiers is VIENNA rectifier. The schematic and its average model are shown in FIG. 53b.The average vector voltage at nodes A, B, C refer to the neutral point “O” equal the phase vector voltages minus the voltage across the inductors L_a, L_b, L_cwhich is given by $\{\begin{array}{c}{\stackrel{.}{V}}_{\mathrm{AO}}={\stackrel{.}{V}}_a-\mathrm{jwL}·{\stackrel{.}{i}}_{\mathrm{La}}\\ {\stackrel{.}{V}}_{\mathrm{BO}}={\stackrel{.}{V}}_b-\mathrm{jwL}·{\stackrel{.}{i}}_{\mathrm{Lb}}\\ {\stackrel{.}{V}}_{\mathrm{CO}}={\stackrel{.}{V}}_c-\mathrm{jwL}·{\stackrel{.}{i}}_{\mathrm{Lc}}\end{array}$

[0290] Following the similar procedure above, the following approximation still exists: $\begin{array}{cc}\{\begin{array}{c}{V}_a\approx V_{\mathrm{AN}}-\frac{1}{3}·\left(V_{\mathrm{AN}}+V_{\mathrm{BN}}+V_{\mathrm{CN}}\right)\\ V_b\approx V_{\mathrm{BN}}-\frac{1}{3}·\left(V_{\mathrm{AN}}+V_{\mathrm{BN}}+V_{\mathrm{CN}}\right)\\ V_c\approx V_{\mathrm{CN}}+V_{\mathrm{NO}}=V_{\mathrm{CN}}-\frac{1}{3}·\left(V_{\mathrm{AN}}+V_{\mathrm{BN}}+V_{\mathrm{CN}}\right)\end{array}i.e.\left[\begin{array}{ccc}\frac{2}{3}& -\frac{1}{3}& -\frac{1}{3}\\ -\frac{1}{3}& \frac{2}{3}& -\frac{1}{3}\\ -\frac{1}{3}& -\frac{1}{3}& \frac{2}{3}\end{array}\right]·\left[\begin{array}{c}{V}_{\mathrm{AN}}\\ V_{\mathrm{BN}}\\ V_{\mathrm{CN}}\end{array}\right]=\left[\begin{array}{c}{V}_a\\ V_b\\ V_c\end{array}\right]& \left(52\right)\end{array}$

[0291] For the VIENNA rectifier, if the converter operates in CCM, the average node voltages V_AN, V_BN, V_CNare given by $\{\begin{array}{c}{V}_{\mathrm{AN}}=\left(1-D_a\right)·\frac{E}{2}\\ V_{\mathrm{BN}}=\left(1-D_b\right)·\frac{E}{2}\\ V_{\mathrm{CN}}=\left(1-D_c\right)·\frac{E}{2}\end{array}\mathrm{when}{i}_a\ge 0\{\begin{array}{c}{V}_{\mathrm{AN}}=\left(1-D_a\right)·\left(-\frac{E}{2}\right)\\ V_{\mathrm{BN}}=\left(1-D_b\right)·\left(-\frac{E}{2}\right)\\ V_{\mathrm{CN}}=\left(1-D_c\right)·\left(-\frac{E}{2}\right)\end{array}\mathrm{when}{i}_a<0$

[0292] Simplification yields $\begin{array}{cc}\{\begin{array}{c}{V}_{\mathrm{AN}}=\left(1-D_a\right)·\frac{E}{2}·\mathrm{sign}\left(i_a\right)\\ V_{\mathrm{BN}}=\left(1-D_b\right)·\frac{E}{2}·\mathrm{sign}\left(i_b\right)\\ V_{\mathrm{CN}}=\left(1-D_c\right)·\frac{E}{2}·\mathrm{sign}\left(i_c\right)\end{array}& \left(53\right)\end{array}$

[0293] where sign(i_a), sign(i_b)., etc depends on the polarity of inductor currents. For example, $\begin{array}{cc}\mathrm{sign}\left(i_a\right)=\{\begin{array}{cc}1& i_a\ge 0\\ -1& i_a<0\end{array}& \left(54\right)\end{array}$

[0294] Substitution equation (53) into equation (52) yields $\begin{array}{cc}\left[\begin{array}{ccc}\frac{2}{3}& -\frac{1}{3}& -\frac{1}{3}\\ -\frac{1}{3}& \frac{2}{3}& -\frac{1}{3}\\ -\frac{1}{3}& -\frac{1}{3}& \frac{2}{3}\end{array}\right]·\left[\begin{array}{c}\left(1-D_a\right)·\mathrm{sign}\left(i_a\right)\\ \left(1-D_b\right)·\mathrm{sign}\left(i_b\right)\\ \left(1-D_c\right)·\mathrm{sign}\left(i_c\right)\end{array}\right]=\frac{2}{E}·\left[\begin{array}{c}{V}_a\\ V_b\\ V_c\end{array}\right]& \left(55\right)\end{array}$

[0295] Equation (55) shows the inherent relationship between duty ratios and input phase voltage in CCM condition. Because the matrix is singular, there is no unique solution for equation (55).

[0296] For three-phase rectifier with unity-power-factor, we have $\begin{array}{cc}\{\begin{array}{c}{V}_a=R_e·i_a\\ V_b=R_e·i_b\\ V_c=R_e·i_c\end{array}& \left(56\right)\end{array}$

[0297] where R_eis the emulated resistance.

[0298] Substitution of the above equation into (55) and simplification yield $\begin{array}{cc}\left[\begin{array}{ccc}\frac{2}{3}& -\frac{1}{3}& -\frac{1}{3}\\ -\frac{1}{3}& \frac{2}{3}& -\frac{1}{3}\\ -\frac{1}{3}& -\frac{1}{3}& \frac{2}{3}\end{array}\right]·\left[\begin{array}{c}\left(1-D_a\right)·\mathrm{sign}\left(i_a\right)\\ \left(1-D_b\right)·\mathrm{sign}\left(i_b\right)\\ \left(1-D_c\right)·\mathrm{sign}\left(i_c\right)\end{array}\right]=\frac{R_s}{V_m}·\left[\begin{array}{c}{i}_a\\ i_b\\ i_c\end{array}\right]& \left(57\right)\end{array}$