Thermal-resistance variable heat sink structure and method of using the same

[0002] The present invention relates to a thermal-resistance variable heat sink structure and to a method of using the same. Particularly, the present invention relates to a technique of screening chips.

[0003] In large-scale computers or the like, the so-called chip set where plural LSIs (large-scale integrated circuits) are mounted on the same board has generally used to realize predetermined functions. When the function of an LSI is realized, a high-dense chip results in larger power consumption, whereas a low-dense chip results in lower power consumption.

[0004] The high-dense chip consumes larger power, thus generating a larger heat amount. For that reason, a heat sink or a cooling fan is attached to the chip to cool the chip, thus stabilizing the performance of the chip itself.

[0005] In the shipment of a chip, whether or not the chip achieves predetermined functions is judged using an automatic IC (integrated circuit) tester. Thus, the screening is carried out to sort defective items and accepted items.

[0006] Conventionally, chips are basically subjected to the DC screening in which a constant voltage is applied to them before the shipment. However, the qualities of chips are not often maintained. Hence, the AC screening (reinforced screening) is required to increase the power consumption after chips are mounted on a board. In this case, the AC screening can be realized by modifying the heat sink structure. However, this approach has not been practically because of a large number of man-hours.

[0007] The present invention is made to solve the above-mentioned problems. An object of the present invention is to provide a thermal-resistance variable heat sink structure that can improve the quality at a working time and can change the shape of a heat sink and reduce the number of steps for attaching or detaching.

[0008] Another object of the present invention is to provide the method of using the above-mentioned heat sink structure.

[0009] According to the present invention, a thermal-resistance variable heat sink structure comprises a thermal resistance adjuster disposed on a heat sink to cool an integrated circuit device. The thermal resistance adjuster has a thermal resistance equal to or more than that of a material for the heat sink.

[0010] Moreover, in a method of using a thermal-resistance variable heat sink structure, according to the present invention, the method comprises the steps of using a thermal resistance adjuster in a factory inspection and then disassembling the thermal resistance adjuster in shipment. The thermal resistance adjuster is disposed on a heat sink to cool an integrated circuit device and is formed of a material having a thermal resistance equal to or more than that of the heat sink.

[0011] That is, in the thermal-resistance variable heat sink structure of the present invention, a thermal resistance adjuster (comb-like plate), which utilizes air blocking function, is mounted on a slit-like heat sink to realize a low thermal resistance. The thermal resistance adjuster is formed of a material having a thermal resistance larger than that of the heat sink.

[0012] In the heat sink structure, a thermal-resistance variable heat sink is used for low-power LSIs among many LSIs mounted on a board. Thus, the screening is performed by accelerating the premature failure while the junction temperature of the low-power LSI is set to the same value as that of a high-power LSI.

[0013] That approach allows the ambient temperature about LSIs mounted on a board to be fixed. Hence, the screening can be carried out with increased junction temperatures of low power LSIs with low integration density.

[0014] Moreover, products that are nearly defective can be initially rejected at the fabrication step. As a result, the quality of an LSI at an operational time can be improved. It is possible to change the structure of a heat sink and to reduce the number of attaching and detaching steps.

[0015] This and other objects, features and advantages of the present invention will become more apparent upon a reading of the following detailed description and drawings, in which;

[0016] FIG. 1 is a front view illustrating a semiconductor integrated circuit device according to an embodiment of the present invention;

[0017] FIG. 2 is a side view illustrating a semiconductor integrated circuit device according to an embodiment of the present invention;

[0018] FIG. 3 is a side view illustrating a semiconductor integrated circuit device with a reduced thermal resistance, according to an embodiment of the present invention;

[0019] FIG. 4 is a front view illustrating a semiconductor integrated circuit device according to another embodiment of the present invention;

[0020] FIG. 5 is a side view illustrating a semiconductor integrated circuit device according to another embodiment of the present invention;

[0021] FIG. 6 is a side view illustrating a semiconductor integrated circuit device with a reduced heat resistance, according to another embodiment of the present invention;

[0022] FIG. 7 is a front view illustrating a semiconductor integrated circuit device according to further another embodiment of the present invention;

[0023] FIG. 8 is a side view illustrating a semiconductor integrated circuit device according to further another embodiment of the present invention; and

[0024] FIG. 9 is a side view illustrating a semiconductor integrated circuit device with a reduced heat resistance, according to further another embodiment of the present invention.

[0025] Embodiments of the present invention will be described below by referring to the attached drawings. FIG. 1 is a front view illustrating a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a side view illustrating a semiconductor integrated circuit device according to an embodiment of the present invention. Referring to FIGS. 1 and 2, a semiconductor integrated circuit device includes solder balls 1, a semiconductor integrated circuit device (LSI) 2, a mounting plate 3, mounting screws 4, radiation fins 5, a thermal resistance adjuster 6, and a marker 7. The marker 7 indicates a place where a predetermined thermal resistance is obtained.

[0026] The thermal resistance adjuster 6 is placed on a heat sink (formed of plural radiation fins 5) to cool the LSI 2. The thermal resistance adjuster 6 is formed of a material having a thermal resistance equal to or more than that of the heat sink. The thermal resistance adjuster 6, not mounted on the heat sink, indicates a lowest thermal resistance. The thermal resistance adjuster 6, mounted on the heat sink, analogously varies its thermal resistance.

[0027] The thermal resistance adjuster 6, shaped in a plate form, is mounted perpendicularly to the radiation fin 5. In other words, the thermal resistance adjuster 6 is mounted on the radiation fin 5 so as to cut the cooling air toward the LSI 2. The position where the thermal resistance adjuster 6 is mounted on the radiation fin 5 varies in the same direction as that of the cooling air. The heat sink is formed of radiation fins 5 arranged in a slit-like form to realize the low thermal resistance.

[0028] FIG. 2 shows an example of a semiconductor integrated circuit device with a high thermal resistance. Specifically, the thermal resistance adjuster 6a, which blocks the air, is mounted on the middle of the radiation fin 5 forming a heat sink. Markers 7, showing a reference thermal resistance, are provided on the outer radiation fins 5.

[0029] FIG. 3 is a side view illustrating a semiconductor integrated circuit device with a reduced thermal resistance. Referring to FIG. 3, the thermal resistance adjuster 6bis mounted on the rear end of the radiation fin 5.

[0030] In the example shown in FIG. 3, markers 7, showing a reference thermal resistance, are provided on the outer radiation fin 5, in a manner similar to that shown in FIG. 2. The heat sink structure (not shown) indicates a lowest thermal resistance when the thermal resistance adjuster 6bis not used.

[0031] The heat sink structure for a semiconductor integrated circuit device, according to an embodiment of the present invention, will be described below by referring to FIGS. 1 to 3.

[0032] Generally, the junction temperature (Tj) of a LSI is one factor determining the reliability of the LSI. The temperature Tj is expressed by the following formula:

[0033] Tj=Ta+Pd*Rθ

[0034] where Ta (° C.) is an ambient temperature, Pd(W) is a power consumption, and Rθ(° C./W) is a thermal resistance.

[0035] The power consumption Pd becomes larger in high dense products. The ambient temperature generally ranges 25° C. to 30° C. In order to suppress the junction temperature to a certain value or less, a radiation structure having a low thermal resistance Rθ is generally used.

[0036] Since the power consumption Pd of low dense LSIs is small, the junction temperature Tj is low. The structure in which LSIs are mounted on the same board provides a small screening effect. In the heat sink structure for a semiconductor integrated circuit device, according to an embodiment of the present invention, the thermal resistance Rθ is simply changed so that the screening effect is improved.

[0037] FIG. 1 shows a heat sink structure viewed from the direction where the cooling air blows. Solder balls 1 are disposed for connection of the LSI 2. A mounting plate 3 for mounting a heat sink, screws 4 for mounting the heat sink, a radiation fin 5, and a thermal resistance adjuster 6 are piled up on the back side of the LSI 2.

[0038] FIG. 2 shows the heat sink structure viewed from the side surface thereof. The thermal resistance adjuster 6ais disposed on the middle of the heat sink structure and has the structure of blocking the cooling air. For example, the thermal resistance adjuster 6ais formed of aluminum. The thermal resistance adjuster 6ais a 4 cm×4 cm cube and has a 1 mm-thick fin. In the case of the wind velocity of 2 m/S, a heat sink with a 3 mm pitch and with no thermal resistance adjuster 6ahas a thermal resistance of 2 to 3° C./W.

[0039] In the structure shown in FIG. 2, the thermal resistance of the heat sink is 5 to 6° C./W. This means that even a half power consumption, compared with the LSI with a maximum power consumption, results in the same junction Tj.

[0040] Similarly, FIG. 3 shows the structure in which the thermal resistance adjuster 6bis moved to the opposite end. It is already known that the thermal resistance of the heat sink is 5 to 6° C./W. With no thermal resistance adjuster, the thermal resistance of the heat sink is 2 to 4° C./W. The movement of the thermal resistance adjuster 6ballows the thermal resistance Rθ of the heat sink to be changed. In this case, the dependency on place of the thermal resistance adjuster 6bis measured in advance. Thus, the marker 7 is denoted in advance.

[0041] In a manufacture and inspection in a factory, the thermal resistance adjuster 6 is mounted on the heat sink and the LSI is subjected to an accelerating test, with the junction temperature Tj increased. After a completion of the inspection, the thermal resistance adjuster 6 is dismounted for shipment. This feature allows the heat sink structure to be minimized. Since it is not necessary to remove the LSI from the heat sink, the screening can be effectively performed.

[0042] FIG. 4 is a front view illustrating a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 5 is a side view illustrating a semiconductor integrated circuit device according to another embodiment of the present invention. FIGS. 4 and 5 show an example of a semiconductor integrated circuit device with an increased thermal resistance.

[0043] Referring to FIGS. 4 and 5, the thermal resistance adjuster 8ais slantingly mounted on the middle of the radiation fin 5. Such a structure allows the cooling air to be smoothly flown.

[0044] FIG. 6 is a side view illustrating an example of a semiconductor integrated circuit device with a reduced thermal resistance, according to another embodiment of the present invention. Referring to FIG. 6, the thermal resistance adjuster 8bis slantingly mounted on the rear end of the radiation fin 5.

[0045] FIG. 7 is a front view illustrating a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 8 is a side view illustrating a semiconductor integrated circuit device according to another embodiment of the present invention. FIGS. 7 and 8 show an example of a high thermal resistance, with the air blocked. Referring to FIG. 8, the thermal resistance adjuster 9ais rotatably mounted on the middle of the heat dissipation so as to vary the angle thereof.

[0046] FIG. 9 is a side view illustrating a semiconductor integrated circuit device with a low thermal resistance, according to another embodiment of the present invention. Referring to FIG. 9, the thermal resistance adjuster 9battached on the middle of the radiation fin 5 is rotated to a horizontal level.

[0047] Since a LSI mounted on a board is fixed at the ambient temperature Ta, the screening can be performed with increased junction temperature of a low-dense, small power LSI.

[0048] According to the present invention, an item that is nearly defective can be initially rejected in a fabrication process so that the quality of the item at a working time can be improved. Moreover, the present invention can change the shape of the heat sink and can reduce the number of steps of attaching and detaching.

[0049] As described above, according to the present invention, the thermal resistance adjuster is mounted on the heat sink to cool an integrated circuit device and is a material having a thermal resistance equal to or more than that of the heat sink. Since the thermal resistance adjuster is used at a factory inspection and then removed in shipment, the quality of an item at a working time can be improved. Moreover, the present invention has the advantage of capable of changing the shape of a heat sink and reducing the number of steps of attaching and detaching.

[0050] The entire disclosure of Japanese Application No. 2000-177715 filed on Jun. 14, 2000 including specification, claims, drawings and summary are incorporated herein by reference in its entirely.