US 6,544,863 B1Grant
Method of fabricating semiconductor wafers having multiple height subsurface layers
Issue Date:2003-04-08
•13 Claims
•4 Drawing Sheets
Abstract
A method for fabricating semiconductor wafers as multiple-depth structure (i.e., having portions of varying height). The method includes patterning a first substrate and bonding a second substrate to the first. This process creates a subsurface patterned layer. Portions of the second substrate may then be etched, exposing the subsurface patterned layer for selective processing. For example, the layered structure may then be repeatedly etched to produce a multiple depth structure. Or, for example, exposed portions of the first substrate may have material added to them to create multiple-depth structures. This method of fabrication provides substantial advantages over previous methods.
Metadata
Assignee
- Calient Networks, Inc.
Inventors
- John M. Chong
- Paul Waldrop
- Tim Davis
- Scott Adams
Application Information
Application Number:US 09/934,783
Filing Date:2001-08-21
Priority Date:2001-08-21
Art Unit:7
Classifications
IPC:
H01L 2146H01L 21302
Field of Search:
438689438718438740438745438752438753257642216 2
Patent Drawings (4 sheets)
Description
Field of the Invention
[0002] This invention relates generally to the use of semiconductor substrates and more specifically to an improved method of fabricating a substrate having regions of varying height.
Background of the Invention
[0003] Semiconductor wafers can be formed in many shapes for a variety of uses. One important practical application for semiconductor substrates is in the fabrication of micro-electro-mechanical systems (MEMS) in the form of electrostatic actuators. In such devices and in other applications, it may be useful to have regions of the semiconductor with varying heights. Design flexibility is significantly increased by the ability to shape the semiconductor wafer. For example, when a fabricated silicon wafer is used as the substrate of an electrostatic actuator the electric field force can vary substantially due to the shape of the substrate.
[0004] Using current semiconductor fabrication processes, it is difficult to form a substrate having regions of varying height. Typically a semiconductor wafer, for example a silicon wafer, is fabricated through a process that includes deposition, masking, and etching. Deposition may include depositing a protective layer on top of the silicon substrate. The protective layer may be, for example, silicon dioxide, silicon nitride, a polymer, or other like material. The protective layer may be deposited or may be formed upon the substrate.
[0005] Masking includes placing a pattern upon the protective layer in a stencil-like fashion. The wafer is then selectively etched through an etching process that may be, for example, a reactive ion etching process or a wet chemical etching process, or some other etching process known in the art. The selective etching of the silicon wafer creates a structure as determined by the pattern as described above.
[0006] Typically the wafer is etched straight down. This process limits the design flexibility in terms of the shape of the fabricated wafer. That is, the three-dimensional structure created is a projection of the pattern. Typically, fabrication of wafers is done as a batch process. This allows a thousand, or more, devices to be fabricated at a time from a single large wafer. Throughout the process there is no physical machining of the wafer surface, no tools touch the wafer. It is not practical to address each device on the wafer, instead the entire wafer is subjected to the process described above. The sequence of operations of the process must be tailored to produce the desired device shape.
[0007] Using the method as described above it is difficult to vary the size of portions of the wafer. Methods such as undercutting or inverting the wafer provide a limited ability to vary the height of portions of the substrate, thus providing only minimal increase in design flexibility.
Summary of the Invention
[0008] A method is disclosed for creating a subsurface patterned layer and exposing the subsurface patterned layer to further processing. A first protective layer is formed upon a first substrate layer. The first protective layer is then selectively patterned such that patterned portions of the first protective layer are reduced. A second substrate layer is then bonded to the first protective layer such that a subsurface patterned layer is formed. A second protective layer is formed upon the second substrate layer and the second protective layer is then selectively patterned such that portions of the second substrate layer are exposed. The exposed portions of the second substrate layer are then etched such that the subsurface patterned layer is exposed.
[0009] Other features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description, that follows below.
Brief Description of the Drawings
[0010] The present invention is illustrated by way of example, and not limitation, by the figures of the accompanying drawings in which like references indicate similar elements and in which:
[0011] FIG. 1 illustrates a process flow diagram according to one embodiment of the present invention;
[0012] FIGS. 2A through 2I illustrate the fabrication of a multiple depth structure according to one embodiment of the present invention; and
[0013] FIGS. 3A through 3C illustrate examples of alternative embodiments of the process of the present invention.
Detailed Description
[0014] A method is described for fabricating semiconductor wafers having portions of varying height. The method includes patterning a semiconductor substrate and bonding to it one or more other patterned substrates creating a subsurface patterned layer. The subsurface patterned layer is then exposed for selective processing. For example, the layered structure may then be repeatedly etched to produce a multiple depth structure. This method of fabrication provides substantial advantages over previous methods.
[0015] An intended advantage of one embodiment of the present invention is to provide multiple depth semiconductor structures for use in MEMS devices. Another intended advantage is to provide and simplify the fabrication process of high resolution multiple depth structures. Another intended advantage is to allow the masking process for a subsurface feature to be effected upon a planar surface. Another intended advantage is to provide reliable bonding of semiconductor wafer layers. Another intended advantage is provide more uniform structures through the use of stop layers to address non-uniformities in the fabrication process.
[0016] As described in more detail below, one embodiment of the present invention is a method of fabricating semiconductor substrates having portions of varying height, i.e., multiple depth structures.
[0017] FIG. 1 is a process flow diagram according to one embodiment of the present invention. The process 100, shown in FIG. 1 begins at operation 105 in which a protective layer is formed or deposited upon a first substrate layer. In a preferred embodiment the substrate may be a semiconductor wafer, for example, a silicon wafer. In alternative embodiments the substrate material may be some other semiconductor material such as gallium arsenide, or may be glass or metal. In a preferred embodiment, the protective layer may be an oxide layer formed upon the substrate layer.
[0018] At operation 110 the protective layer is selectively patterned. The pattern depends upon the desired application. In a preferred embodiment the patterning may be accomplished through the deposition of a photosensitive layer that is then selectively exposed to light. The areas exposed to light are then removed through a development process. This leaves an opening in the photosensitive layer exposing a portion of the protective layer. The exposed portion of the protective layer is then etched (for example by a reactive ion etching process) thereby reducing the protective layer thickness in the exposed regions.
[0019] At operation 115 a second substrate layer is bonded to the patterned protective layer of the first substrate. In an alternative embodiment the second substrate layer may be deposited upon the first substrate layer. The second substrate layer may be the same material as the first substrate or may be another material or combination of material. A protective layer is formed or deposited upon the second substrate layer at operation 120 and the second substrate is selectively patterned at operation 125.
[0020] At operation 130 the second substrate layer is etched. The etching may be accomplished using one or more standard etching processes well known to those skilled in the art. For example, the etching may be a dry etching process such as reactive ion etching (RIE), or could be a wet chemical etching process. The patterned protective layer protects the substrate material below it and the exposed material is etched away. The etching of the second substrate layer exposes the patterned protective layer of the first substrate layer.
[0021] At operation 135 the patterned protective layer of the first substrate is subjected to etching. This may involve a two-part etching process. A first etch may be used to remove any residual protective material (e.g., oxide) from the patterned areas. A second etch may then be used to etch the exposed substrate material of the first substrate layer thus creating a structure of varying height.
[0022] In an alternative embodiment, the top side and back side of the second substrate is patterned to provide better alignment between the two patterned layers.
[0023] FIGS. 2A through 2I illustrate the fabrication of a multiple depth structure according to one embodiment of the present invention. FIG. 2A shows a substrate 201 that may be a semiconductor (e.g., silicon). The substrate may be other materials as well, such as glass or metal.
[0024] FIG. 2B shows the addition of a protective layer 202. In a preferred embodiment this protective layer may be a layer of silicon dioxide formed by subjecting a silicon substrate to heat and gases. In alternative embodiments the protective layer 202 may be other materials, and may be deposited upon the substrate 201. The protective layer 202 may be chosen for its mechanical or electrical characteristics depending upon the application.
[0025] FIG. 2C shows the protective layer 202 after a patterning and etching process. Patterning may typically be accomplished by applying a photosensitive layer, not shown, to protective layer 202. A stencil of the desired pattern may then be placed upon the photosensitive layer and light is applied. The material exposed to the light is then typically removed using an etching process. The stenciled pattern is impervious to the etching thereby leaving a stenciled pattern on protective layer 202. In a preferred embodiment, a thin portion 202aof protective layer 202 remains after the etching process. This thin portion 202amay function as an etch stop as described below in reference to FIG. 2G. In an alternative embodiment thin portions 202amay not used, leaving the substrate layer 201 exposed.
[0026] FIG. 2D shows the addition to the structure of a substrate layer 203. The substrate layer 203 may be the same material as the substrate layer 201, or may be a different material. Substrate layer 203 is bonded to the patterned side of protective layer 202. This creates a patterned subsurface layer that can be selectively processed when it is later exposed as described below. Protective layer 202 has a relatively planar surface that allows for a reliable bonding process.
[0027] FIG. 2E shows the combined substrates with an additional protective layer 204. Typically, for a silicon substrate, the structure is re-oxidized forming a layer upon the exposed substrate layer (i.e., substrate layer 203). The oxidation process is typically effected upon the entire structure. but adds only negligibly to the previous oxidation layer (i.e., protective layer 202). The protective layer 202 acts as insulation to further oxidation.
[0028] FIG. 2F shows protective layer 204 after a patterning and etching process. This process may be the same as that described above in reference to FIG. 2C or may another patterning and etching process. Some portion of the protective layer 204 has been removed so that etching of the substrate layer 203 can be effected.
[0029] FIG. 2G shows the result of the etching of the substrate layer 203. The directional etching etches vertically down and removes exposed portions of the substrate layer 203. The remaining portion of the protective layer 204 protects that portion of substrate layer 203 that is directly below it. The etching continues until the protective layer 202 is reached. Thin portions 202aact as an etch stop protecting the substrate layer 201. In practice the etching is not uniform, the etching is accelerated in the middle as compared with the edges. When the etch encounters thin portions 202athe etching in that area is stopped while the etching continues at the edges. This results in the uniform etching of substrate layer 203.
[0030] FIG. 2H shows the removal of thin portions 202aof protective layer 202. To remove thin portions 202a,a different etch may be used that can etch the protective layer. For example, an etch is used that can etch silicon dioxide. This etching process may remove some of the exposed patterned portion of protective layer 202 while removing thin portions 202a.At this point the buried patterned surface, as described above in reference to FIG. 2D, is exposed.
[0031] FIG. 2I shows the multiple level structure resulting from a final etching process. This etching process may be the same as that described above in reference to FIG. 2G, or may a different etching process.
[0032] FIGS. 3A though 3C show examples of alternative embodiments of the process of the present invention.
[0033] FIG. 3A shows a structure in which the final etching process, described in reference to FIG. 21 is not used to create a multiple level structure. Instead of the final etching process that would etch away exposed portions of substrate layer 201, a process is used to build up the exposed portions of substrate layer 201. The additional material 101aadded to substrate layer 101 may be the same as the material of substrate layer 101 or may be another material that adheres to the material of substrate layer 101. For example, if substrate layer 101 is silicon, the additional material 101amay be silicon or a metal such as tungsten that adheres to silicon, but not to silicon dioxide. The additional material 101amay be applied using an electroplating process, an electroless deposition or some other process.
[0034] FIG. 3B shows an exemplary structure using a different pattern than the one described in reference to FIG. 2F. This structure illustrates that the patterning process can be varied to form a variety of structure shapes.
[0035] FIG. 3C shows an exemplary structure created by reiterating the process of the present invention and varying the patterns. This structure illustrates that the process may be repeated to create structures having several different heights.
[0036] The method of the present invention may be applied to a variety of MEMS devices including micro-fluidic devices, inertial sensors, and RF devices, among others.
[0037] In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
Claims
What is claimed is:
1. A method comprising:
forming a first protective layer upon a first substrate layer;
selectively patterning the first protective layer such that patterned portions of the first protective layer are reduced;
bonding a second substrate layer to the first protective layer such that a subsurface patterned layer is formed;
forming a second protective layer upon the second substrate layer;
selectively patterning the second protective layer such that portions of the second substrate layer are exposed;
etching the exposed portions of the second substrate layer such that the subsurface patterned layer is exposed;
etching the subsurface patterned layer such that the patterned portions are removed, exposing portions of the first substrate layer; and
etching the exposed portions of the first substrate layer such that a multiple-depth structure is formed.
2. A method comprising:
forming a first protective layer upon a first substrate layer;
selectively patterning the first protective layer such that patterned portions of the first protective layer are reduced;
bonding a second substrate layer to the first protective layer such that a subsurface patterned layer is formed;
forming a second protective layer upon the second substrate layer;
selectively patterning the second protective layer such that portions of the second substrate layer are exposed;
etching the exposed portions of the second substrate layer such that the subsurface patterned layer is exposed;
etching the subsurface patterned layer such that the patterned portions are removed, exposing portions of the first substrate layer; and
adding material to the exposed portions of the first substrate layer such that a multiple-depth structure is formed.
3. The method of claim 1 wherein the first substrate and the second substrate are silicon wafers.
4. The method of claim 1 wherein the first substrate layer and the second substrate layer are different materials.
5. The method of claim 1 wherein the first substrate and the second substrate are composed of a material selected from the group consisting essentially of a semiconductor, glass, and metal.
6. The method of claim 1 wherein the etching is accomplished through use of an etching process selected from the group consisting of reactive ion etching, wet chemical etching, and laser ablation etching.
7. The method of claim 2 wherein the material is added through a process selected from the group consisting of an electroplating process, an electroless plating process, and a fill and planarize process.
8. The method of claim 7 wherein the first substrate layer is silicon and the material is tungsten.
9. The method of claim 1 wherein the first protective layer and the second protective layer are layers of silicon dioxide.
10. The method of claim 9 wherein the first protective layer and the second protective layer are formed upon the first substrate layer and the second substrate layer, respectively, through an oxidation process.
11. A method comprising:
forming a first protective layer upon a first substrate layer;
selectively patterning the first protective layer such that patterned portions of the protective layer on a top side of the first substrate layer are reduced;
bonding a second substrate layer to the top side of the first substrate layer such that a subsurface patterned layer is formed;
forming a second protective layer upon the second substrate layer;
selectively patterning the first protective,layer on a bottom side of the first substrate layer such that portions of the first substrate layer are exposed;
etching the exposed portions of the first substrate layer such that the subsurface patterned layer is exposed;
etching the subsurface patterned layer such that the patterned portions are removed, exposing portions of the second substrate layer; and
etching the exposed portions of the second substrate layer such that a multiple-depth structure is formed.
12. A method comprising:
forming a first protective layer upon a first substrate layer;
selectively patterning the first protective layer such that patterned portions of the first protective layer are reduced;
depositing a second substrate layer to the first protective layer such that a subsurface patterned layer is formed;
forming a second protective layer upon the second substrate layer;
selectively patterning the second protective layer such that portions of the second substrate layer are exposed;
etching the exposed portions of the second substrate layer such that the subsurface patterned layer is exposed;
etching the subsurface patterned layer such that the patterned portions are removed, exposing portions of the first substrate layer; and
etching the exposed portions of the first substrate layer such that a multiple-depth structure is formed.
13. A method comprising:
a) forming a protective layer upon a substrate layer;
b) selectively patterning the protective layer such that patterned portions of the protective layer are reduced;
c) bonding another substrate layer to the protective layer such that a subsurface patterned layer is formed;
d) repeating operations a-c as desired;
e) forming a final protective layer upon the final substrate layer;
f) selectively patterning the final protective layer such that portions of the final substrate layer are exposed;
g) etching the exposed portions of the final substrate layer such that a final subsurface patterned layer is exposed;
h) etching the exposed subsurface patterned layer such that the patterned portions are removed, exposing portions of a previous substrate layer;
i) etching the exposed portions of the previous substrate layer such that a previous subsurface patterned layer is exposed; and
repeating operations h-i such that a multiple-depth structure is formed.
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