Architecture and method for flushing non-transmitted portions of a data frame from a transmitted FIFO buffer

[0002] 1. Field of the Invention

[0003] The present invention relates to networks and more particularly, to a system and method of controlling network traffic data in a full-duplex switched network operating according to Ethernet (IEEE 802.3) protocol.

[0004] 2. Description of the Related Art

[0005] Switched local area networks use a network switch for supplying data frames between network stations or other network nodes, where each network node is connected to the network switch by a media. The switched local area network architecture uses a media access control (MAC) enabling a network interface within each network node and the network switch to access the media. The network switch stores and forwards data frames received from a transmitter node to a destination node based on header information and the data in the received frames, including source and destination address. An external memory, such as an SSRAM, is used by the network switch to temporarily store the data frames as they are passed through the switch. In particular, the network switch stores and fetches data frames in the external memory via an external memory bus.

[0006] Transmission and reception of a data frame in a network switch port typically involves receiving a data packet by a MAC, and transferring the received data packet to a first in first out (FIFO) buffer memory. Conversely, transmit data is stored in a (transmit) FIFO buffer memory prior to transmission on the network media by the MAC. When invalid data becomes stored in the transmit buffer, it needs to be eliminated in order to free up this area of the transmit buffer. However, a disadvantage with use of a FIFO memory for the transmit buffer is that there is no convenient way to “flush,” invalid data without eliminating the entire contents of the transmit buffer.

[0007] Another disadvantage with the use of a FIFO for transmit buffer (or receive buffer) is the increasing complexity associated with maintaining status information for each data frame stored in the FIFO buffer. If a stored data frame is to have corresponding status information, then an additional FIFO buffer would be required for storing the status information for each stored data frame. Moreover, additional synchronization logic would be required to maintain correspondence between the stored frame data and the corresponding status data, increasing the cost and complexity of the network switch.

[0008] There is a need, in a multi-port data communication switch, to conveniently and simply bypass or “flush” invalid data stored in the transmit FIFO buffer memory without eliminating the entire contents of the transmit buffer memory and without providing an additional FIFO buffer for storing status information for each stored data frame.

[0009] These and other needs are obtained by the present invention where a network switch port includes a transmit state machine and receive state machine for transmitting and receiving network data to and from a medium interface, and a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and respective buffers, based on prescribed interface protocol signals between the memory management unit and the transmit state machine and the receive state machine.

[0010] According to one aspect of the present invention, a network switch port in a network switch is configured for sending data packets between a medium interface and the network switch. The network switch port includes a transmit buffer for storing transmit data from the network switch, a transmit state machine for transmitting the transmit data onto the medium interface according to a prescribed network protocol, and a memory management unit. The memory management unit is configured for selectively transferring the transmit data to the transmit state machine based on prescribed interface protocol signals between the memory management unit and the transmit state machine. The transmit state machine outputs a flush transmit buffer signal to the transmit memory management unit in response to a detected error in transmitting the transmit data. The transmit memory management unit, in response to the flush transmit buffer signal, sets an incremented transmit buffer read pointer to a value corresponding to a next transmit data stored in the transmit buffer.

[0011] Another aspect of the present invention provides a method in a network switch port of transferring transmit data from a network switch to a medium interface. The method includes storing transmit data received from the network switch in a random access transmit buffer, selectively transferring the transmit data from the random access transmit buffer to a transmit state machine based on prescribed interface protocol signals between a transmit memory management unit and the transmit state machine, transmitting the transmit data onto the medium interface by the transmit state machine according to a prescribed network protocol, outputting a flush transmit buffer signal from the transmit state machine to the transmit memory management unit in response to a detected error in transmitting the transmit data, and directing the random access transmit buffer to flush the non-transmitted transmit data in response to the flush transmit buffer signal. Flushing the non-transmitted transmit data includes setting an incremented transmit buffer read pointer to a value corresponding to a next transmit data stored in the random access transmit buffer in response to the flush transmit buffer signal.

[0012] Additional advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

[0013] FIG. 1 is a block diagram of a packet switched network including a multiple port switch according to an embodiment of the present invention.

[0014] FIG. 2 is a block diagram of the multiple port switch of FIG. 1.

[0015] FIG. 3 is a block diagram illustrating in detail the switching subsystem of FIG. 2.

[0016] FIG. 4 is a block diagram illustrating one of the network switch ports of FIG. 3 according to an embodiment of the present invention.

[0017] FIG. 5 is a block diagram illustrating in detail the interface between the memory management unit and the transmit and receive state machines of FIG. 4 according to an embodiment of the present invention.

[0018] FIG. 6 is a diagram summarizing the transfer of transmit data from the transmit memory management unit to the transmit state machine of FIG. 5.

[0019] The present invention will be described with the example of a switch in a packet switched network, such as an Ethernet (IEEE 802.3) network. It will become apparent; however, that the present invention is also applicable to other packet switched systems, as described in detail below, as well as to other types of systems in general.

[0020] FIG. 1 is a block diagram of an exemplary system in which the present invention may be advantageously employed. The exemplary system 10 is a packet switched network, such as an Ethernet (IEEE 802.3) network. The packet switched network includes integrated multiport switches (IMS) 12 that enable communication of data packets between network stations. The network may include network stations having different configurations, for example twelve (12) 10 megabit per second (Mb/s) or 100 Mb/s network stations 14 (hereinafter 10/100 Mb/s) that send and receive data at a network data rate of 10 Mb/s or 100 Mb/s, and a 1000 Mb/s (i.e., 1 Gb/s) network node 22 that sends and receives data packets at a network speed of 1 Gb/s. The gigabit node 22 may be a server, or a gateway to a high-speed backbone network. Hence, the switches 12 selectively forward data packets received from the network nodes 14 or 22 to the appropriate destination based upon Ethernet protocol.

[0021] Each switch 12 includes a media access control (MAC) module 20 that transmits and receives data packets to and from 10/100 Mb/s physical layer (PHY) transceivers 16 via respective shared media independent interfaces (MII) 18 according to IEEE 802.3u protocol. Each switch 12 also includes a gigabit MAC 24 for sending and receiving data packets to and from a gigabit PHY 26 for transmission to the gigabit node 22 via a high speed network medium 28.

[0022] Each 10/100 Mb/s network station 14 sends and receives data packets to and from the corresponding switch 12 via a media 17 and according to either half-duplex or full duplex Ethernet protocol. The Ethernet protocol ISO/IEC 8802-3 (ANSI/IEEE Std. 802.3, 1993 Ed.) defines a half-duplex media access mechanism that permits all stations 14 to access the network channel with equality. Traffic in a half-duplex environment is not distinguished or prioritized over the medium 17. Rather, each half-duplex station 14 includes an Ethernet interface card that uses carrier-sense multiple access with collision detection (CSMA/CD) to listen for traffic on the media. The absence of network traffic is detected by sensing a deassertion of a receive carrier on the media. Any station 14 having data to send will attempt to access the channel by waiting a predetermined time after the deassertion of a receive carrier on the media, known as the interpacket gap interval (IPG). If a plurality of stations 14 have data to send on the network, each of the stations will attempt to transmit in response to the sensed deassertion of the receive carrier on the media and after the IPG interval, resulting in a collision. Hence, the transmitting station will monitor the media to determine if there has been a collision due to another station sending data at the same time. If a collision is detected, both stations stop, wait a random amount of time, and retry transmission.

[0023] The 10/100 Mb/s network stations 14 that operate in full duplex mode send and receive data packets according to the Ethernet standard IEEE 802.3u. The full-duplex environment provides a two-way, point-to-point communication link enabling simultaneous transmission and reception of data packets between each link partner, i.e., the 10/100 Mb/s network station 14 and the corresponding switch 12.

[0024] Each switch 12 is coupled to 10/100 physical layer (PHY) transceivers 16 configured for sending and receiving data packets to and from the corresponding switch 12 across a corresponding shared media independent interface (MII) 18. In particular, each 10/100 PHY transceiver 16 is configured for sending and receiving data packets between the switch 12 and up to four (4) network stations 14 via the shared MII 18. A magnetic transformer 19 provides AC coupling between the PHY transceiver 16 and the corresponding network medium 17. Hence, the shared MII 18 operates at a data rate sufficient to enable simultaneous transmission and reception of data packets by each of the network stations 14 to the corresponding PHY transceiver 16.

[0025] Each switch 12 also includes an expansion port 30 for transferring data between other switches according to a prescribed protocol. For example, each expansion port 30 can be implemented as a second gigabit MAC port similar to the port 24, enabling multiple switches 12 to be cascaded together as a separate backbone network.

[0026] FIG. 2 is a block diagram of the switch 12. The switch 12 contains a decision making engine 40 that performs frame forwarding decisions, a switching subsystem 42 for transferring frame data according to the frame forwarding decisions, a buffer memory interface 44, management information base (MIB) counters 48, and MAC (media access control) protocol interfaces 20 and 24 to support the routing of data packets between the Ethernet (IEEE 802.3) ports serving the network stations 14 and 22. The MIB counters 48 provide statistical network information in the form of management information base (MIB) objects to an external management entity controlled by a host CPU 32, described below.

[0027] The external memory interface 44 enables external storage of packet data in a synchronous static random access memory (SSRAM) 36 in order to minimize the chip size of the switch 12. In particular, the switch 12 uses the SSRAM 36 for storage of received frame data, memory structures, and MIB counter information. The memory 36 is preferably a pipelined burst SSRAM having a 64-bit wide data path, a 16-bit wide address path, and a memory size of at least 512 kbytes, capable of running at clock frequencies up to 66 MHz.

[0028] The switch 12 also includes a processing interface 50 that enables an external management entity such as a host CPU 32 to control overall operations of the switch 12. In particular, the processing interface 50 decodes CPU accesses within a prescribed register access space, and reads and writes configuration and status values to and from configuration and status registers 52.

[0029] The internal decision making engine 40, referred to as an internal rules checker (IRC), makes frame forwarding decisions for data packets received from one source to at least one destination station.

[0030] The switch 12 also includes an LED interface 54 that clocks out the status of conditions per port and drives external LED logic. The external LED logic drives LED display elements that are human readable.

[0031] The switching subsystem 42, configured for implementing the frame forwarding decisions of the IRC 40, includes a port vector first in first out (FIFO) buffer 56, a plurality of output queues 58, a multicopy queue 60, a multicopy cache 62, a free buffer queue 64, and a reclaim queue 66.

[0032] The MAC unit 20 includes modules for each port, each module including a MAC receive portion, a receive FIFO buffer, a transmit FIFO buffer, and a MAC transmit portion. Data packets from a network station 14 are received by the corresponding MAC port and stored in the corresponding receive FIFO. The MAC unit 20 obtains a free buffer location (i.e., a frame pointer) from the free buffer queue 64, and outputs the received data packet from the corresponding receive FIFO to the external memory interface 44 for storage in the external memory 36 at the location specified by the frame pointer.

[0033] The IRC 40 monitors (i.e., “snoops”) the data bus to determine the frame pointer value and the header information of the received packet (including source, destination, and VLAN address information). The IRC 40 uses the frame pointer value and the associated header information to determine which MAC ports will output the data packet stored at the location specified by the frame pointer. The decision making engine may thus determine that a given data packet should be output by either a single port, multiple ports, or all ports (i.e., broadcast). For example, each data packet includes a header having source and destination address, where the decision making engine 40 may identify the appropriate output MAC port based upon the destination address. Alternatively, the destination address may correspond to a virtual address that the appropriate decision making engine identifies as corresponding to a plurality of network stations. Alternatively, the received data packet may include a VLAN (virtual LAN) tagged frame according to IEEE 802.1d protocol that specifies another network (e.g., via a gateway 22) or a prescribed group of stations. The IRC 40 may also determine that the received data packet should be transferred to another switch 12 via the expansion port 30. Hence, the internal rules checker 40 will decide whether a frame temporarily stored in the buffer memory 36 should be output to a single MAC port or multiple MAC ports.

[0034] The internal rules checker 40 outputs a forwarding decision to the switch subsystem 42 in the form of a forwarding descriptor. The forwarding descriptor includes a port vector identifying each MAC port that should receive the data packet, priority class identifying whether the frame is high priority or low priority, VLAN information, Rx port number, Opcode, and frame pointer. The port vector identifies the MAC ports to receive the data packet for transmission (e.g., 10/100 MAC ports 1-12, Gigabit MAC port, and/or Expansion port). The port vector FIFO 56 decodes the forwarding descriptor including the port vector, and supplies the frame pointer to the appropriate output queues 58 that correspond to the output MAC ports to receive the data packet transmission. In other words, the port vector FIFO 56 supplies the frame pointer on a per-port basis. The output queues 58 fetch the data packet identified in the port vector from the external memory 36 via the external memory interface 44, and supply the retrieved data packet to the appropriate transmit FIFO of the identified ports. If a data packet is to be supplied to a management agent, the frame pointer is also supplied to a management queue 68, which can be processed by the host CPU 32 via the CPU interface 50.

[0035] The multicopy queue 60 and the multicopy cache 62 keep track of the number of copies of the data packet that are fetched from the respective output queues 58, ensuring that the data packet is not overwritten in the SSRAM 36 until the appropriate number of copies of the data packet have been output from the SSRAM 36. Once the number of copies corresponds to the number of ports specified in the port vector FIFO, the port vector is forwarded to the reclaim queue 66. The reclaim queue stores frame pointers that can be reclaimed by the free buffer queue 64 as free pointers. After being returned to the free buffer queue 64, the frame pointer is available for reuse by the MAC unit 20 or the gigabit MAC unit 24.

[0036] FIG. 3 depicts the switch subsystem 42 of FIG. 2 in more detail according to an exemplary embodiment of the present invention. Other elements of the multiport switch 12 of FIG. 2 are reproduced in FIG. 3 to illustrate the connections of the switch subsystem 42 to these other elements.

[0037] As shown in FIG. 3, the MAC module 20 includes a receive portion 20aand a transmit portion 20b. The receive portion 20aand the transmit portion 20beach include three (3) quad-MAC enhanced (QMACE) modules 70 configured for performing the corresponding receive or transmit function for four (4) switch ports according to IEEE 802.3 protocol. Hence, QMACE module 70aperforms receive MAC operations for 10/100 Mb/s switch ports 0, 1, 2, 3; module 70bperforms receive MAC operations for 10/100 Mb/s switch ports 4, 5, 6, 7; and module 70cperforms receive MAC operations for 10/100 Mb/s switch ports 8, 9, 10, and 11. The QMACE modules 70d, 70e, and 70fperform the transmit MAC operations for the 10/100 Mb/s switch ports complementary to modules 70a, 70b, and 70c, respectively.

[0038] The receive portions 24aand 30aof the gigabit MAC port 24 and the expansion port 30 also have receive MAC modules 72aand 72boptimized for the respective ports. The transmit portions 24band 30bof the gigabit MAC port 24 and the expansion port 30aalso have transmit MAC modules 72cand 72d, respectively. The MAC modules are configured for full-duplex operation on the corresponding port, and the gigabit MAC modules 72aand 72care configured in accordance with the Gigabit Proposed Standard IEEE Draft P802.3z.

[0039] Each of the receive MAC modules 70a, 70b, 70c, 72a, and 72binclude queuing logic 74 for transferring of receive data from the corresponding internal receive FIFO to the external memory 36 and the rules checker 40. Each of the transmit MAC modules 70d, 70e, 70f, 72c, and 72dinclude dequeuing logic 76 for transferring data from the external memory 36 to the corresponding internal transmit FIFO. The queuing logic 74 fetches frame pointers from the free buffer queue 64, and uses the fetched frame pointers to store receive data to the external memory 36 via the external memory interface controller 44. The frame buffer pointer specifies the location in external memory 36 where the received data frame will be stored by the receive FIFO. The queuing logic 74 issues a write request to the external memory interface 44.

[0040] The external memory interface 44 includes a scheduler 80 for controlling memory access by the queuing logic 74 or dequeuing logic 76 by any switch port to the external memory 36, and an SSRAM interface 78 for performing the read and write operations with the SSRAM 36. In particular, the switch 12 is configured to operate as a non-blocking switch, where network data is received and output from the switch ports at the respective wire rates of 10, 100, or 1000 Mb/s. Hence, the scheduler 80 controls the access by different ports to optimize usage of the bandwidth of the external memory 36.

[0041] Each receive MAC 24astores a data frame in an internal FIFO upon reception from the corresponding switch port. The corresponding queuing logic 74 obtains a frame pointer and sends a write request to the external memory interface 44. The scheduler 80 schedules the write request with other write requests or any read requests from the dequeuing logic 76, and generates a grant for the requesting queuing logic 74 to initiate a transfer at the scheduled event (i.e., slot). The frame data is then transferred over data bus 68afrom the receive FIFO to the external memory 36 in a direct memory access (DMA) transaction during the assigned slot. The frame is stored in the location pointed to by the free buffer pointer obtained from the free buffer pool 64, although a number of other buffers may be used to store a frame, as will be described.

[0042] The rules checker 40 also receives the frame pointer and the header information (including source address, destination address, VLAN tag information, etc.) by monitoring (i.e., snooping) the DMA write transfer on the bus 68a. The rules checker 40 uses the header information to make the forwarding decision and generate a forwarding instruction in the form of a forwarding descriptor that includes a port vector. The port vector has a bit set for each output port to which the frame should be forwarded. If the received frame is a unicopy frame, only one bit is set in the port vector generated by the rules checker 40. The bit that is set in the port vector corresponds to a particular one of the ports.

[0043] The rules checker 40 outputs the forwarding descriptor including the port vector and the frame pointer into the port vector FIFO 56. The port vector is examined by the port vector FIFO 56 to determine which particular output queue, e.g. at least one of the queues 58 or the management queue 68, should receive the associated frame pointer. The port vector FIFO 56 places the frame pointer into the top of the appropriate queue 58 and/or 68. This queues the transmission of the frame. The output queue 58 is processed separately by the host CPU 32 via the CPU interface 50.

[0044] As shown in FIG. 3, each of the transmit MAC units 70d, 70e, 70f, 72d, and 72chave an associated output queue 58a, 58b, 58c, 58d, and 58e, respectively. Each of the output queues 58 have a high priority queue for high priority frame pointers, and a low priority queue for low priority frame pointers. The high priority frame pointers are used for data frames that require a guaranteed access latency, e.g., frames for multimedia applications or management MAC frames. The frame pointers stored in the FIFO-type output queues 58 are processed by the dequeuing logic 76 for the respective transmit MAC units. At some point in time, the frame pointer reaches the bottom of an output queue 58, for example the output queue 58efor the gigabit transmit MAC 72c. The dequeuing logic 76 for the transmit gigabit port 24btakes the frame pointer from the corresponding gigabit port output queue 58e, and issues a request to the scheduler 80 to read the frame data from the external memory 36 at the memory location specified by the frame pointer. The scheduler 80 schedules the request, and issues a grant for the dequeuing logic 76 of the transmit gigabit port 24bto initiate a DMA read during the assigned slot. In response to the grant, the dequeuing logic 76 reads the frame data in a DMA transaction from the location in external memory 36 pointed to by the frame pointer, stores the frame data in the internal transmit FIFO for transmission by the transmit gigabit MAC 72c. If the frame pointer specifies a unicopy transmission, the frame pointer is returned to the free buffer queue 64 following writing the frame data into the transmit FIFO.

[0045] A multicopy transmission is similar to the unicopy transmission, except that the port vector has multiple bits set, designating the multiple ports from which the frame will be transmitted. The frame pointer is placed into each of the appropriate output queues 58 and transmitted by the appropriate transmit MAC units 20b, 24b, and/or 30b.

[0046] The free buffer pool 64, the multicopy queue 60, the reclaim queue 66, and the multicopy cache 62 are used to manage use of frame pointers and re-use of frame pointers once the frame has been transmitted to its designated output port(s). In particular, the dequeuing logic passes frame pointers for unicopy frames to the free buffer queue 64 after the buffer contents have been copied to the appropriate transmit FIFO.

[0047] For multicopy frames, the port vector FIFO 56 supplies multiple copies of the same frame pointer to more than one output queue 58, each frame pointer having a unicopy bit set to zero. The port vector FIFO also copies the frame pointer and the copy count to the multicopy queue 60. The multicopy queue writes the copy count to the multicopy cache 62. The multicopy cache is a random access memory having a single copy count for each buffer in external memory (i.e., each frame pointer).

[0048] Once the dequeuing logic 76 retrieves the frame data for a particular output port based on a fetched frame pointer and stores the frame data in the transmit FIFO, the dequeuing logic checks if the unicopy bit is set to 1. If the unicopy bit is set to 1, the frame pointer is returned to the free buffer queue 64. If the unicopy bit is set to zero indicating a multicopy frame pointer, the dequeuing logic 76 writes the frame pointer with a copy count of minus one (−1) to the multicopy queue 60. The multicopy queue 60 adds the copy count to the entry stored in the multicopy cache 62.

[0049] When the copy count multicopy cache 62 for the frame pointer reaches zero, the frame pointer is passed to the reclaim queue 66. Since a plurality of frame pointers may be used to store a single data frame in multiple buffer memory locations, the frame pointers are referenced to each other to form a linked-list chain of frame pointers to identify the entire stored data frame. The reclaim queue 66 traverses the chain of buffer locations identified by the frame pointers, and passes the frame pointers to the free buffer queue 64.

[0050] The foregoing description of the switch architecture provides an overview of the switch operations in a packet switched network. A more detailed description of the features of the present invention as embodied in the network switch 12 will now be provided.

[0051] FIG. 4 is a block diagram illustrating a network switch port 100 in the switch 12 configured for sending and receiving data packets between the switching subsystem 42 and the reduced media independent interface 18 according to an embodiment of the present invention. As described above, each MAC module 70 includes a 10/100 Mb/s switch port 100. However, the architecture of the network switch port 100 is also applicable to the gigabit MAC port 24 and the expansion port 30.

[0052] As shown in FIG. 4, the network switch port 100 includes the queuing block 74 and the dequeuing block 76, described above. The queuing block 74 is configured for transferring data packets received by the network switch port 100 to the external memory 36, and the dequeuing block 76 is configured for transferring transmit data from the external memory 36 for transmission by the network switch port 100.

[0053] The network switch port 100 also includes a MAC and FIFO subsystem 102 configured for transmitting and receiving data packets between the switching subsystem 42 and the reduced MII 18. In particular, the MAC and FIFO subsystem 102 includes reduced MII logic 104, a MAC core 106, and port registers 108. The reduced MII (RMII) logic 104 is configured for translating between a reduced MII protocol and the MII protocol by converting nibble-wide (4-bit) data on the MII interface to 2-bit wide data on the RMII 18, reducing the number of pins necessary for data transfer. The port registers 108 are configured for storing status and control configuration information for the switch port 100.

[0054] The MAC core 106 performs the basic operations of sending and receiving data packets according to IEEE 802.3 protocol, storing the transmit and receive data in transmit and receive buffers, and transferring the transmit and receive data into and out of the buffers. In particular, the MAC core 106 includes a memory management architecture that enables transfer of transmit data and receive data across multiple independent clock domains. The MAC core 106 includes a receive bus-side memory management unit (RB_MMU) 110, a transmit bus-side memory management unit (XB_MMU) 112, a receive MAC-side memory management unit (RM_MMU) 114, and a transmit MAC-side memory management unit (XM_MMU) 116. As described below, the RB_MMU 110, the (XB_MMU) 112, (RM_MMU) 114 and (XM_MMU) 116 form a memory management system configured for controlling transfer of data to and from the transmit random access buffer memory (TX_SRAM) 118 and the receive random access buffer memory (RX_SRAM) 120. The MAC core 106 also includes a transmit state machine (XM_MAC) 122 and a receive state machine (RM_MAC)124 configured for sending and receiving data packets according to IEEE 802.3 protocol, respectively.

[0055] The memory management unit architecture enables data packets to be transferred between the random access transmit buffer 118, and the random access receive buffer 120, across multiple clock domains without concern of synchronization issues between the clock domains. In particular, the XB_MMU 112 is configured for transferring data from the read bus 68bof FIG. 3 into the random access transmit buffer 118 under the control of the dequeuing block 76 and according to the clock domain of the read bus 68b. Similarly, the RB_MMU 110 transfers receive data from the random access receive buffer 120 onto the write bus 68aunder thee control of the queuing block 74 and according to the clock domain of the write bus 68a. Hence, the XB_MMU 112 and the RB_MMU 110 control transfer of data between the transmit buffer 118 and the receive buffer 120 according to the clock domains of the read bus 68band the write bus 68a, respectively.

[0056] The XM_MMU 116 is configured for transferring transmit data stored in the TX_SRAM 118 to the transmit MAC state machine 122 according to a prescribed interface protocol between the XM_MMU 116 and the XM_MAC 122, described below. Similarly, the RM_MMU 114 is configured for transferring receive data from the RM_MAC 124 to the RX_SRAM 120 according to a prescribed interface protocol between the RM_MAC 124 and the RM_MMU 114. As described below, the interface protocol between the memory management units and the transmit or receive state machines establishes a request/acknowledge based protocol, enabling the memory management units to transfer data to and from the respective random access buffer memories without creating synchronization issues with the transmit clock domain of the transmit state machine 122 or the receive clock of the receive state machine 124.

[0057] FIG. 5 is a diagram illustrating in detail the interface 130 between the memory management units 114 and 116, and the transmit and receive state machines 122 and 124 according to an embodiment of the present invention. As shown in FIG. 5, the interface 130 includes plurality of interface protocol signals that are exchanged between the RM_MMU 114 and the RM_MAC 124, and between the XM_MMU 116 and the XM_MAC 122. These interface protocol signals establish a hand shaking protocol between the memory management units and the transmit/receive state machines to control transfer of data to the respective random access buffer memory while avoiding synchronization problems that normally may be encountered due to different clock domains.

[0058] As shown in FIG. 5, the RM_MMU 114 is configured for outputting a receive buffer availability signal RM_REQ to the receive state machine 124. The receive memory management unit 114 outputs the receive buffer availability signal (RM_REQ) based on a determined availability of memory locations in the receive buffer 120, for example a minimum of 64 bytes. The receive buffer state machine 124, in response to receiving the receive buffer availability signal (RM_REQ), can begin to transfer receive data that is received in the form of data packets from the reduced MII 18. The receive state machine 124 transfers the receive data on a 64-bit wide receive MAC data path (RM_DATA), along with additional signals specifying whether the supplied data should be stored in a new memory location, overwritten over a previous location, or whether the data on the RM_DATA path corresponds to status data.

[0059] The receive memory management 124 initiates transfer of receive data by concurrently outputting a start of frame signal (RM_STF) and a receive buffer advance signal pulse (RM_ADV). The receive buffer advance signal pulse (RM_ADV) is asserted during one clock cycle in the receive MAC clock domain, and is used to advance a receive SRAM write pointer (RXP) stored in a register 132 in the RM_MMU 114. The receive memory management unit 114, in response to detecting the receive buffer advance signal pulse (RM_ADV), increments the write pointer (RXP) on the following clock cycle in the receive MAC clock domain.

[0060] The receive buffer advance signal pulse (RM_ADV) is typically asserted by the receive state machine 124 every 16 clock cycles in the receive MAC clock domain (RMCLK), resulting in a transfer of 8 bytes of receive data for each receive buffer advance signal pulse.

[0061] The interface 130 also includes a 3-bit receive MAC byte enable (RM_BE) representing a byte alignment value that indicates a number of valid bytes of the receive data on the receive data path (RM_DATA). The byte alignment value is encoded, such that the value “000” corresponds to 8 bytes of valid data, and “001” corresponds to only a single byte of valid data. Hence, the receive state machine 124 outputs the byte alignment value (RM_BE) for each transfer on the receive data path (RM_DATA).

[0062] The interface 130 also includes a receive buffer protect signal (RM_PROTECT), an end of frame signal (RM_ENF), a receive buffer pointer reload signal (RM_RELOAD), and a status signal (RM_STATUS) indicating data transfer to the receive memory management unit 114 corresponds to status data for a received data frame. The receive buffer protect signal (RM_PROTECT) is asserted by the receive state machine 124 when the receive byte count is less than 64. Hence, the receive state machine 124 deasserts the receive buffer protect signal in response to transferring the predetermined minimum number of bytes of the receive data (e.g., 64 bytes). Hence, the receive memory management unit, in response to deassertion of the receive buffer protect signal (RM_PROTECT), transfers the receive data from internal latches 134 to the random access receive buffer 120.

[0063] The receive buffer pointer reload signal (RM_RELOAD) is asserted by the receive state machine 124 based on a detected invalid condition in the receive data, for example due to a detected collision in a half duplex network, or due to an error signal (RXER) received from RMII 18. The receive memory management unit 114, in response to detecting the receive buffer pointer reload signal, reloads the receive memory pointer 132 with a stored pointer value (StoredP) corresponding a beginning of the data frame, enabling the erroneous data stored in the RX_SRAM to be overwritten. The receive state machine 124 outputs the end of frame signal (RM_ENF) in response to transfer of the receive data as a complete data frame. The end of frame signal is valid when concurrently asserted with the receive buffer advanced signal pulse (RM_ADV), and the end of frame signal is written into the receive SRAM 120 with the current receive data on the following clock of the receive MAC clock domain. A value of “1” written into the RX_SRAM 120 indicates that the RM_DATA is the last 8 bytes of the frame. The status signal (RM_STATUS) output by the receive state machine 124 indicates that the current data on the RM_DATA path is receive tag/status information. The status signal is asserted by the receive state machine 124 upon the deassertion of the end of frame signal (RM_ENF), and deasserts after 2 receive MAC clock cycles.

[0064] As further shown in FIG. 5, the receive memory management unit 114 includes logic 136 for controlling the transfer of receive data on the RM_DATA path from the latches 134 to the random access receive buffer memory 120, and for incrementing and reloading the receive buffer pointer 132 that points to a corresponding location in the buffer memory 120 for writing receive data or corresponding status data. Hence, the receive memory management unit 114 selectively transfers the receive data and selectively stores the receive data into the random access receive buffer based on the interface control signals output by the receive state machine 124.

[0065] The interface 130 includes similar interface control signals for the transmit data supplied from the random access transmit buffer 118 to the transmit state machine 122 under the control of the transmit memory management unit 116. The transmit memory management unit 116 includes a register 138 for storing a transmit buffer pointer value (TXP), latches 140 for temporarily storing the 64-bit wide data transferred from the random access transmit buffer 118 and output onto a 64-bit data path (XM_DATA), and logic 142 for selectively controlling the transmit buffer pointer (TXP) stored in register 138 and the transfer of data from the transmit SRAM 118.

[0066] As still further shown in FIG. 5, the transmit memory management unit 116 outputs a 64-bit wide transmit data signal, and encoded byte enable signal (XM_BE) that specifies a transmit byte alignment value indicating a number of valid bytes of the transmit data on the transmit data path (XM_DATA). The transmit memory management unit 116 also outputs a transmit request signal (XM_REQ) based on a determined minimum number of bytes (e.g., 64 bytes corresponding a minimum size data frame) stored in the random access transmit buffer 118. The transmit memory management unit 116 also outputs a 2-bit transmit status signal (XM_STAT), where the first bit is asserted to indicate a start of packet, and then deasserted to indicate the end of a packet. The second bit of the status where (XM_STAT) is used to specify to the transmit state machine 122 whether the transmit state machine 122 should append an error correction code, for example a frame check sequence (FCS).

[0067] The transmit state machine 122, in response to detecting the transmit request signal (XM_REQ), determines the status of the network condition on the medium interface (RMII) 18, for example whether the network media is idle in a half-duplex medium, or whether the link is active in a full duplex network. Based on the determined network condition on the medium interface 104, the transmit state machine 122 outputs a transmit buffer advance signal pulse (XM_ADV) according to the transmit MAC clock domain (XM_CLK). As described above with respect to the receiver buffer advance signal pulse (RM_ADV), the transmit buffer advance signal pulse (XM_ADV) is used to advance the transmit buffer pointer (TXP) in the register 138 by the logic 142. The transmit buffer advance signal pulse (XM_ADV) is typically asserted once every 16 clock cycles in the transmit clock domain (XM_CLK), resulting in a transfer of 8 bytes of transmit data for each transfer buffer advance signal pulse.

[0068] The transmit state machine 122 asserts a transmit buffer protect signal (XM_PROTECT) at the beginning of the frame, and is deasserted at either the end of the frame or the middle of the frame to signal the transmit memory management unit 116 that the corresponding memory locations in the transmit buffer 116 may be released to the XB_MMU 112 of FIG. 4. Hence, the transmit state machine 122 deasserts the transmit buffer protect signal (XM_PROTECT) in response to transmitting a prescribed minimum number of bytes of the transmit data onto the medium interface, for example a minimum number of data bytes that indicates to the transmit state machine 122 that the data packet can be successfully transmitted. The transmit state machine 122 also outputs a transmit buffer pointer reload signal (XM_RELOAD) for retransmission of the prescribed number of bytes. The logic 142, in response to detecting the transmit buffer pointer reload signal, reloads the register 138 with a stored transmit pointer corresponding to the beginning of the data frame, and initiates a second transfer of the transmit data from the transmit buffer 118.

[0069] The transmit state machine 122 outputs also a completion signal (XM_FRM_COMP) based on a successful transmission of the transmit data as the data frame. If an error is encountered while transmitting a data frame due, for example, to underflow, loss of carrier, late collision, etc., an error condition results and the portion of the data frame remaining in the transmit buffer after the error condition is encountered will not be transmitted. However, the remaining portion of the data frame needs to be “flushed” from the transmit buffer. In this case, the flush signal (XM_FLUSH) is used to indicate a decision by the transmit state machine 122 to “flush” the data frame. More specifically, if the logic 142 receives the flush signal (XM_FLUSH) while transmitting a data frame data, the logic 142 jumps to the next data frame based on the flush signal (XM_FLUSH), and updates the transmit buffer pointer value to the next data frame of transmit data, effectively “flushing” the non-transmitted portion of the data frame from the transmit FIFO buffer.

[0070] FIG. 6 is a diagram illustrating the interface protocol signals between the transmit memory management unit 116 and the transmit state machine 122. As shown in FIG. 6, the transmit memory unit 116 begins transfer of data from transmit memory buffer 118 to transmit state machine 122 for output to RMII 18 by outputting, to transmit state machine 122, a transmit data availability signal (XM_REQ) based on a determined availability of a prescribed number of bytes of transmit data in the transmit memory buffer 118, a start of (frame) pointer signal (XM_STAT), and an encoded byte alignment value (XM_BE) indicating the number of valid bytes on the transmit data path. Concurrently with these signals, begins the transfer of the first 8-bytes of transmit data (XM_DATA0) as 64-bit (8-byte) transfers during 16 clock cycles. In response to receipt of each 8-bytes of transmit data, the transmit state machine 122 asserts the transmit buffer advance signal (XM_ADV). Upon detection of the transfer of the last transmit data (e.g., XM_DATAN) on the transmit data path, the transmit state machine 122 outputs the frame completion signal (XM_FRM_COMP).

[0071] FIG. 6 illustrates an example of an error being encountered during transmission of FRAME 1 while the read pointer (RP) is at RP3. In this example, the transmit state machine 122 asserts the “flush” signal (XM_FLUSH) when the error is encountered and the transmit memory management unit 116 responds by jumping the read pointer from RP3 to RP10, the start of the next data frame (e.g., FRAME 2).

[0072] According to the disclosed embodiment, a memory management unit selectively transmits data and receive data to and from a transmit state machine and receive state machine based on prescribed interface protocols signals between the memory management unit and the transmit state machine, and between the memory management unit and the receive state machine. When a error is encountered during transmitting of a data frame, the transmit state machine asserts the “flush” signal and the transmit memory management unit responds by jumping the read pointer to the start of the next data frame, effectively “flushing” the non-transmitted portion of the data frame from the transmit FIFO buffer.

[0073] While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.