Method for fabricating shallow trench isolation

[0002] The present invention generally relates to a method for manufacturing semiconductor devices, and more particularly, to a method for fabricating shallow trench isolation in semiconductor devices.

[0003] With the fast developments of semiconductor process technology, the dimensions of integrated circuits (ICs) are rapidly scaled down into sub-micron level. Oxide isolation regions are usually incorporated with active areas of IC devices during the period of semiconductor processes. In general, a local oxidation (LOCOS) process is employed to form these oxide isolation regions, but the LOCOS process may induce a bird's beak structure such that the active areas of devices are unacceptably encroached. Therefore, shallow trench isolation (STI) process is widely used to form isolation regions between active areas. The conventional process of fabricating shallow trench isolation is shown in FIG. 1A to FIG. 1D.

[0004] Referring to FIG. 1A, a pad oxide layer 102 and a silicon nitride layer 104 are sequentially formed on a substrate 100, and then a shallow trench 106 is formed thereon by a photolithography and etching process. Afterward, a thermal oxidation process is carried out to form a lining oxide layer 110 on sidewall 108 of shallow trench 106.

[0005] Referring to FIG. 1B and FIG. 1C, an implant process is performed to form a siliconoxynitride (SiON) layer 112 on the lining oxide layer 110. Afterwards, a high-density plasma chemical vapor deposition (HDPCVD) process is carried out to deposit a silicon oxide layer 120 on the silicon nitride layer 104 and inside the trench. The excess silicon oxide over the silicon nitride layer 104 is removed away by a chemical mechanical polishing (CMP) process.

[0006] Generally, a thicker lining oxide layer 110 is necessary to be deposited in conventional process. Thereafter, a siliconoxynitride (SiON) layer 112 is formed by a nitrogen-implanted process (114,116,118).

[0007] However, the thicker lining oxide layer 110, on one hand, will consume a large amount of substrate 100 material such that the trench 106 easily encroach outwardly on the active areas (not shown) resulting in worse trench topography. On the other hand, if the lining oxide layer 110 is thinner, the crystalline structure of trench sidewall 108 may be damaged by a large number of ions induced by high-density plasma at the start-up period of the process. Furthermore, the isolation effect of the shallow trench 106 will be severely downgraded after the silicon oxide plug is entirely generated.

[0008] In addition, the implant angles for operating ion implanter must be switched frequently to adapt to various processes so that the manufacturing time and cost of trench will considerably increase.

[0009] Referring to FIG. 1D, the silicon nitride layer 104 is stripped by hot phosphoric acid (H₃PO₄) and the pad oxide layer 102 is etched away by hydrofluoric acid (HF). At the time, a silicon oxide plug 122 is left inside the shallow trench 106. While the pad oxide layer 102 is being removed, the silicon oxide plug 122 and the lining oxide layer 110 are also simultaneously etched.

[0010] Generally speaking, the etch rate of the pad oxide layer 102 formed by thermal oxidation is smaller than that of the silicon oxide plug 122 formed by HDPCVD process when using HF as an etchant. Consequently, after the lining oxide layer 110 is removed, the corroded edge of silicon oxide plug 122 may result in current leakage. The thicker siliconoxynitride layer 112 is deposited, the more severe the silicon oxide plug 122 is damaged. Since a long time of etching process is implemented, thus the silicon oxide plug 122 is strictly encroached, making the edge recess of the silicon oxide plug 122 acutely, which evokes many problems, such as sub-threshold voltage and current leakage.

[0011] In view of the problems encountered with the foregoing conventional shallow trench isolation, for example, there are some degree of substrate overuse, plasma damage of crystalline structure of trench, and edge recess of the silicon oxide plug.

[0012] As a result, the primary object of the present invention is, before the HDPCVD process is implemented, that the trench is implanted by nitrogen ions to form silicon nitride, followed that the siliconoxynitride layer is formed by thermal oxidation process. During the thermal oxidation process, the siliconoxynitride layer can be formed with ease by a small amount of substrate, correspondingly increasing the regions of the active area.

[0013] Another object is using the siliconoxynitride layer to prevent the crystalline structure of the trench from high-density plasma damages.

[0014] Still another object is utilizing the siliconoxynitride so as to prohibit the silicon oxide plug form recess.

[0015] In the preferred embodiment of the present invention, a pad oxide layer and a mask layer is sequentially formed on a substrate. Afterwards, an opening is formed through the mask layer and the pad oxide layer such that regions of the substrate are exposed. Thereafter, the exposed regions are etched to form trenches inside the substrate. Next, nitrogen ions are implanted into the sidewall of the trenches to form a silicon nitride layer, and then a siliconoxynitride layer is formed inside the sidewall of the trenches. Subsequently, a silicon oxide layer is formed on the siliconoxynitride layer and on the mask layer. The excess portion of the silicon oxide layer over said mask layer is removed to expose the mask layer, and then the mask layer is removed away. Finally, the pad oxide layer is removed by using hydrofluoric acid (HF).

[0016] In summary, the silicon nitride layer is formed prior to the formation of the silicon oxide. Thereafter, the siliconoxynitride layer is formed by the thermal oxidation process, which can effectively prevent the crystalline structure of trench from high-density plasma damage to reduce the probability of current leakage. At the same time, the siliconoxynitride layer is utilized for protecting the silicon oxide plug.

[0017] The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

[0018] FIGS. 1A-1D illustrate cross-sectional views of a conventional process for forming shallow trench isolation; and

[0019] FIGS. 2-8 illustrate cross-sectional views of a process for forming shallow trench isolation according to the preferred embodiment of the present invention.

[0020] The present invention provides a method for forming shallow trench isolation. A siliconoxynitride is formed on sidewall of the trench to generating a better trench topography.

[0021] As shown in FIGS. 2-8, these figures illustrate cross-sectional views of a process for forming shallow trench isolation in accordance with the present invention.

[0022] Referring FIG. 2, a pad oxide layer 202 is formed on a substrate 200, and then a mask layer 204 is deposited on the pad oxide layer 202 wherein the mask layer 204, such as silicon nitride (SiN) formed by low pressure chemical vapor deposition (LPCVD), is used as a etching mask. The pad oxide layer 202 is used to prevent stress damage when the mask layer 204 is deposited thereon.

[0023] Referring FIG. 3, the mask layer 204 and the pad oxide layer 202 are patterned and expose a portion of substrate 200. The exposed portion of the substrate 200 is subsequently etched to form a shallow trench 300 wherein the patterned mask layer 204 is served as an etching mask.

[0024] Referring to FIG. 4, after the dopant is ionized, the concentration and the distribution of the dopant are controlled precisely during the period of implant process. The ionized dopant is implanted into the trench 300 sidewall 302 of the substrate 200 by accelerator to form silicon nitride (SiN) layer 400, wherein the thickness of silicon nitride layer 400 is between about 25 and 200 angstroms. In the preferred embodiment of the present invention, the nitrogen atoms is used as dopant, such as NO, N₂and NH₃, wherein the energy 402 of the implant process is between about 1 keV and about 10 keV. Additionally, the nitrogen ionized dosage for implanting is between about 1E15/cm³and 1E17/cm³. The tilt angle of implant process is between about 7° and 30°, and the twist angle is 90°. Therefore, the wafer is readily rotated with four times (360° of a cycle) to complete the whole implant process.

[0025] As a result, in the present invention, only a fixed twist angle is used to effortlessly finish the whole implant process of the trench 300. On the contrary, in the conventional process, ions implant process is completed by various tilt angles during an implant process. Further, the present invention can implant various aspect ratio of trench 300 by merely adjusting the tilt angles, which is more suitable for small dimension scale so as to increase the integrity of the ICs.

[0026] Referring to FIG. 5, the siliconoxynitride layer 500 is formed on the silicon nitride layer 400 by a thermal oxidation process, wherein the thickness of the siliconoxynitride layer 500 is between about 25 and 200 angstroms, and the operation temperature of thermal oxidation process is between about 650° C. and 900° C. Since only a small amount of substrate 200, when the thickness of silicon nitride layer 400 is at least 25 angstroms, is needed to form the siliconoxynitride layer 500 so that the time of manufacture process is diminished and the probability of the trench 300 encroachment on the active regions (not shown) is further reduced. Furthermore, the siliconoxynitride layer 500 is a good kind of passivation material, since the siliconoxynitride layer 500 can alleviate the interface stress and better resistance proof from away moisture and defects.

[0027] Referring to FIG. 6, a silicon oxide layer 600 is deposited on substrate 200 and inside the trench 300 by a HDPCVD process wherein the thickness of the silicon oxide layer 600 is between about 3000 and 14000 angstroms. The silicon nitride layer 400 is generally formed prior to the deposition of the silicon oxide layer 600. Thereafter, the siliconoxynitride layer 500 is formed by the thermal oxidation process, which can effectively inhibit the crystalline structure of trench 300 from high-density plasma damage.

[0028] Referring to FIG. 7, the excess silicon oxide over the siliconoxynitride layer 500 is removed by using etch back process or CMP method.

[0029] Referring to FIG. 8, the mask layer 204, such as silicon nitride, may be stripped by hot phosphoric acid (H₃PO₄) and the pad oxide layer 202 is etched away by hydrofluoric acid (HF). At the time, a silicon oxide plug 800 is left inside the shallow trench 300. Usually, the etch rate of the pad oxide layer 202 formed by thermal oxidation is smaller than that of the silicon oxide plug 800 formed by HDPCVD process when HF is used as an etchant. While the lining layer 202 is removing, the siliconoxynitride layer 500 serves as a protection layer of the silicon oxide plug 800 to avoid the recess edge of the silicon oxide plug 800.

[0030] According to the above-mentioned, the silicon nitride layer 400 is formed prior to the formation of the silicon oxide. Thereafter, the siliconoxynitride layer 500 is formed by the thermal oxidation process, which can effectively prevent the crystalline structure of trench 300 from high-density plasma damage to reduce the probability of current leakage. At the same time, the siliconoxynitride layer 500 is utilized for protecting the silicon oxide plug 800.

[0031] As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrated of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.