Capacitor for semiconductor memory device and method of manufacturing the same

[0002] The present invention relates to a capacitor for semiconductor memory device and a method of manufacturing the same, and more particularly to a capacitor for semiconductor memory device with a dielectric layer having low leakage current and high dielectric constant and method of manufacturing the same.

[0003] Along with the recent progress in the semiconductor manufacturing technology, the demand for memory device has increased dramatically. Consequently, a memory device having higher capacitance per small dimension is required. Capacitance of the capacitor is increased by using an insulator having high dielectric constant or enlarging the surface area of a lower electrode. Those conventional capacitors have used Ta₂O₅layer having a dielectric constant higher than that of nitride-oxide(NO) layer as a dielectric, thereby forming the lower electrode having 3-Dimensional structure.

[0004] FIG. 1 is a cross-sectional view showing a capacitor in a conventional semiconductor memory device. Referring to FIG. 1, a gate electrode 13 including a gate insulating layer 12 at a lower portion thereof is formed by a known technique on an upper part of a semiconductor substrate 10 which a field oxide layer 11 is formed at a selected portion thereof. A junction region 14 is formed on the semiconductor substrate 10 at both sides of the gate electrode 13, thereby forming an MOS transistor. A first interlevel insulating layer 16 and a second interlevel insulating layer 18 are formed on the upper part of the semiconductor substrate 10 on which the MOS transistor has been formed. A storage-node contact hole h is formed in the first and the second interlevel insulating layers 16 and 18 so that the junction region 14 is exposed. A cylinder type lower electrode 20 is formed by a known technology in a storage-node contact hole h to be contact with the exposed junction region 14. A hemi-Spherical grain(HSG) layer 21 is formed on the surface of the lower electrode 20 in order to increase the surface area of the lower substrate 20. A Ta₂O₅layer 23 is formed on the surface of the HSG layer 21. At this time, the Ta₂O₅layer 23 is formed as follows. First, a surface of the HSG layer 21 is cleaned before the Ta₂O₅layer 23 is formed, and then the RTN(rapid thermal nitridation) process is performed ex situ, thereby forming a silicon-nitride layer 22 on the surface of the HSG layer 21. Next, a first Ta₂O₅layer is formed at a temperature of approximately 400˜450° C. to thickness of 53˜57 Å. Afterward, an annealing process is performed at low temperature, and then a second Ta₂O₅layer is formed to the same thickness and by the same process as in the first Ta₂O₅layer. Annealing processes at low temperature and at high temperature are continued in series, thereby forming a single Ta₂O₅layer 23. An upper electrode 24 is deposited on upper parts of the Ta₂O₅layer 23 and the second interlevel insulating layer 18, thereby completing the formation of a capacitor.

[0005] However, the conventional capacitor formed according to the above method using the Ta₂O₅layer as a dielectric layer has the following problems.

[0006] First, a difference in the composition rate of Ta and O is generated since the general Ta₂O₅layer has unstable stoichiometry. As a result, substitutional Ta atoms, i.e. vacancy atoms, are generated in the thin film. Since those vacancy atoms are oxygen vacancies, leakage current is generated. The amount of vacancy atoms can be controlled depending on the contents and the bond strength of components in the Ta₂O₅layer; however, it is difficult to eliminate them completely.

[0007] In order to stabilize the unstable stoichiometry of the Ta₂O₅layer, the Ta₂O₅layer is oxidized so as to remove the substitutional Ta atoms in the Ta₂O₅layer. However, when the Ta₂O₅layer is oxidized, the following problems occur. That is, the Ta₂O₅layer has high oxide reaction with an upper electrode and a lower electrode formed of polysilicon or TiN and so forth. Therefore, in an oxide process to oxidize the substitutional Ta atoms, an oxide layer having a low dielectric constant is formed at an interface since the Ta₂O₅layer and the upper electrode or the lower electrode react to one another, and oxygen moves to the interface between the Ta₂O₅layer and the lower electrode, thereby deteriorating the homogeneity of the interface.

[0008] Further, since an organic substance such as Ta(OC₂H₅)₅used as a precursor has a large amount of carbon components, impurities such as carbon atoms C, carbon compounds(CH₄, C₂H₄) and H₂O result in the Ta₂O₅layer. These impurities increase leakage current in the capacitor and degrade the dielectric characteristics of the Ta₂O₅layer. Accordingly, a capacitor having a large capacitance is difficult to obtain.

[0009] Moreover, using the Ta₂O₅layer as a dielectric layer increases extra ex-situ steps, i.e. one before formation of Ta₂O₅layer and one after the cleaning step. Also, two steps of Ta₂O₅deposition should be applied to the formation of the Ta₂O₅layer, and two thermal processes at low and high temperatures are performed after the Ta₂O₅layer has been formed. Therefore, forming a dielectric layer with Ta₂O₅using the conventional method is cumbersome.

[0010] Accordingly, it is one object of the present invention to provide a capacitor for semiconductor device capable of obtaining a great capacitance by providing a dielectric layer having low leakage current and high dielectric constant.

[0011] Furthermore, the other object of the present invention is to provide a method of manufacturing capacitor for semiconductor device capable of simplifying manufacturing process thereof.

[0012] According to one embodiment of the present invention, a capacitor on a semiconductor substrate includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the upper part of the dielectric layer, wherein the dielectric layer is an amorphous TaON layer.

[0013] In another aspect of the present invention, the present invention provides a method of forming a capacitor for semiconductor memory device including the steps of: forming a lower electrode on the semiconductor substrate; depositing an amorphous TaON layer as a dielectric layer on the upper part of the lower electrode; thermal-treating the amorphous TaON layer in a range of maintaining the amorphous state; and forming an upper electrode on the upper part of the TaON layer.

[0014] Still another aspect of the present invention, the present invention provides a method of forming a capacitor for semiconductor memory device including the steps of: forming a lower electrode on the semiconductor substrate; surface-treating the lower electrode; depositing an amorphous TaON layer as a dielectric layer on the upper part of the lower electrode; thermal-treating the amorphous TaON layer in a range of maintaining the amorphous state; and forming an upper electrode on the upper part of the TaON layer, wherein the amorphous TaON layer is formed by a wafer surface chemical reaction of a Ta chemical vapor obtained from a precursor, O₂gas and NH₃gas with pressure of 0.1 to 100 Torr at a temperature of 300 to 600° C. in an LPCVD chamber.

[0015] FIG. 1 is a cross-sectional view for showing a conventional capacitor for semiconductor device.

[0016] FIGS. 2A to 2C are cross-sectional views of each process for describing a method of manufacturing a capacitor for semiconductor device according to the present invention.

[0017] Referring to FIG. 2A, a field oxide layer 31 is formed according to a known method at a selected portion of a semiconductor substrate 30 having a selected conductivity. A gate electrode 33 having a gate insulating layer 32 at a lower portion thereof is formed at a selected portion of the upper part of the semiconductor substrate 30, and a spacer 34 is formed according to a known method at both side-walls of the gate electrode 33. A junction region 35 is formed on both sides of the gate electrode 33 of the semiconductor substrate 30, thereby forming an MOS transistor. A first interlevel insulating layer 36 and a second interlevel insulating layer 38 are formed at the semiconductor substrate 30 in which the MOS transistor is formed. Afterward, the second and the first interlevel insulating layers 38,36 are patterned so that a selected portion of the junction region 35 is exposed, thereby forming a storage node contact hole H. A lower electrode 40 of cylinder type or stack type is formed to be in contact with the exposed junction region 35. An HSG layer 41 for enlarging the surface area of the lower electrode 40 is formed according to a known method on the surface of the lower electrode 40. Afterwards, to prevent a low dielectric oxide layer from generating on the surface of the HSG layer 41, i.e. the interface between the lower electrode 40 including the HSG layer 41 and a dielectric layer(not illustrated) which will be formed later, the lower electrode 40 and the second interlevel insulating layer 38 are cleaned by using HF vapor, HF solution and a compound containing HF. This cleaning-treatment can be performed in situ or ex situ. In addition, the surface of the HSG layer 41 can be interface-treated by using NH₄OH, or H₂SO₄and so forth to improve the homogeneity of the interface before or after cleaning a naturally generated low dielectric oxide layer.

[0018] Referring to FIG. 2B, as a dielectric, an amorphous TaON layer 43 is formed on the upper part of the lower electrode 40. The amorphous TaON layer 43 in the present invention is formed in the LPCVD chamber maintaining 300 to 500° C. with pressure of less than 100 torr. The amorphous TaON layer 43 is formed by a chemical reaction of Ta chemical vapor, O₂gas and NH₃gas on the wafer surface in a state of restraint of gas phase reaction in order to minimize residue impurities therein. Here, the Ta chemical vapor is formed by evaporating an organic metal precursor including tantalum such as Ta(OC₂H₅)₅(tantalum ethylate) and Ta(N(CH₃)₂)₅(penta-dimethyl-amino-tantalum). That is, an amount of the precursor selected using a flow controller such as MFC (mass flow controller) is flowed and evaporated in an evaporizer or evaporation tube including an orifice or a nozzle, thereby generating the Ta chemical vapor. At this time, the temperature of a conduit coupled to the chamber that is a flow path of the evaporizer or Ta vapor, is preferably maintained at 150 to 200° C. so as to prevent condensation of the Ta chemical vapor, and it is appropriate that the amount of the precursor supplied in the evaporizer or evaporation tube is 50 to 300 mg/min. And, O₂gas and NH₃gas are adjusted depending on the Ta chemical vapor, but preferably supplied to flow amount of approximately 5 to 500 sccm. Especially, O₂gas is, as a variable which adjusts dielectric constant of the TaON layer 43, supplied by adjusting dielectric constant appropriately in a range of 30 to 100. The amorphous TaON layer 43 is formed to a thickness of approximately 50 to 150 Å. At this time, when depositing the amorphous TaON layer 43, the TaON layer 43 can be deposited in series at atmosphere thereof after supplying first NH₃gas and then nitrifying the surface of the lower electrode 40. Then, the interfacial oxidation of the TaON layer is prevented by nitrifying the surface of the lower electrode 40, thereby increasing interface affinity. At this time, a nitride thin film(not illustrated) is formed on the surface of the lower electrode 40 by the nitrifying step.

[0019] Afterwards, as illustrated in FIG. 2C, the amorphous TaON layer 43 is thermal-treated in a range of not changing the amorphous state, i.e. at a temperature of 300 to 600° C. to improve the property thereof. At this time, the thermal-treatment can be annealed at an atmosphere of plasma gas including nitrogen, for example NH₃, N₂, N₂/H₂plasma gas or at an atmosphere of plasma gas including oxygen, for example N₂O or O₂gas. Structural defects and structural heterogeneity like micro cracks and pin holes on the surface of the TaON layer 43 are improved due to this plasma annealing process. At this time, when annealing, the TaON layer is maintained in an amorphous state because of the following reasons. A TaON layer in a crystalline state is generally is accompanied with a high thermal process, thereby increasing oxygen contents in the TaON layer while a TaON layer in an amorphous state is not accompanied with a high thermal process and therefore nitrogen contents in the TaON layer is relatively high. Consequently, dielectric constant in the amorphous state of relatively high nitrogen contents is higher than that in the crystalline state of relatively high oxygen contents. Accordingly, the thermal-treatment is performed without changing the amorphous state to ensure higher dielectric constant. Next, an upper electrode 44 is formed on the upper part of the TaON layer 43 to a selected thickness. Herein, the upper electrode 44 can be formed of a doped-polysilicon or a metal layer. At this time, one among TiN, TaN, W, WN, WSi, Ru, RuO₂, Ir, IrO₂and Pt can be used as the metal layer. And, this metal layer 44 can be formed by a technique among LPCVD, PECVD, and RF magnetic sputtering technique. At this time, a barrier metal layer(not illustrated) can be additionally interposed before forming the upper electrode 44.

[0020] And, before depositing the amorphous TaON layer, a surface treatment of the lower electrode can be replaced with a plasma NH₃gas annealing process or RTN process.

[0021] According to the present embodiment, as the amorphous TaON layer(∈=30˜100) having high dielectric constant against the crystalline TaON layer(∈=20˜26) is applied as a dielectric of a capacitor, capacitance of memory device is drastically increased.

[0022] And, the amorphous TaON layer has a stable bonding structure of Ta—O—N, thereby having a stable stoichiometry against the tantalum oxide layer. Therefore, the TaON layer 43 is has a superior tolerance against external electrical impacts and high breakdown voltage and very low leakage current. In addition, since the TaON layer has a stable structure, the oxide reaction between the lower electrode and the upper electrode is hardly generated. Accordingly, the thickness of an equivalent dielectric layer can be controlled to less than 35 Å thin.

[0023] In the aspect of manufacturing method, the TaON layer is formed in a single layer and only an annealing process is performed to stabilize the TaON layer after the deposition thereof. Consequently, the manufacturing process of this embodiment is simpler than that of the conventional tantalum oxide layer.