Electrical parameter tester having decoupling means

[0002] The present application is based upon co-pending provisional application Serial. No. 60/176,882 filed Jan. 19, 2000, which is hereby incorporated herein in its entirety by reference.

[0003] The present invention relates to the field of electronic circuits, and, more particularly, to a tester and method for testing electrical parameters of circuit paths including at least one electronic circuit device.

[0004] Integrated circuits (ICs) are well known and are used in a variety of telecommunications, computer, and other electronic devices. It is important to detect defects and/or design limitations of such integrated circuits during their design and testing phase. This is so that these problems may be corrected before large scale manufacturing takes place. Furthermore, is may also be important to monitor electrical properties or parameters of such ICs over their lifetime to detect problems that may arise in certain applications so that these problems may be corrected in future designs.

[0005] One method for testing ICs for latent defects or other problems is stress testing. Stress testing involves applying a stress voltage to an integrated circuit and measuring the effects that the stress voltage has on certain electrical parameters. For example, the stress voltage may be used to accelerate degradation of semiconductor device layers due to hot carrier injection. The effects of such hot carrier degradation or aging may then be determined using parametric analyzers or other measurement devices, as will be appreciated by those of skill in the art.

[0006] One example of a stress tester is disclosed in an article entitled “Novel Self-Stressing Test Structures for Realistic High-Frequency Reliability Characterization” by Snyder et al., 1993 IEEE Intl. Reliability Physics Symposium Proceedings, pp. 57-65. The article discloses a self-stressing test structure that may be used for reliability failure measurements caused by hot carriers, electromigration, and oxide breakdown, for example. The test structure includes a high-frequency on-chip oscillator having a frequency controlled by an external DC voltage. A high frequency, oscillating (i.e., an alternating current (AC)) test signal is produced thereby and may be routed to various circuit elements. The test signal may be electronically isolated to allow DC measurement of the various circuit elements.

[0007] While the above AC self-stressing test structure may be useful for determining the effects of high frequency operation on an integrated circuit, other factors may also effect electrical parameters. For example, overshoots or undershoots of an input voltage to a circuit may also cause hot carrier injection or other problems independent of operating frequencies. Additionally, it may be desirable to measure the effects of voltage overshoots or undershoots, for example, over a circuit path including a plurality of circuit devices rather than on a single device.

[0008] In view of the foregoing background, it is therefore an object of the invention to provide a tester and related methods for testing a circuit path which tests not only the effects of high frequency operation but also the effects of voltage overshoots and undershoots.

[0009] This and other objects, features, and advantages in accordance with the present invention are provided by a tester for a circuit path including a voltage controlled oscillator (VCO) for generating a controllable frequency oscillating test signal and having a controllable amplitude defined between first and second voltages, a multiplexer for selectively connecting one of the oscillating test signal, the first voltage, and the second voltage to the circuit path, and a selector for selectively connecting the multiplexer to the circuit path. Moreover, at least one of the first and second voltages may be controllable so that the VCO generates the oscillating test signal to selectively have one of an amplitude greater than, less than, and equal to an amplitude of an output of the circuit path. The circuit path may include a plurality of electronic circuit devices connected together.

[0010] More particularly, the circuit path, the VCO, the multiplexer, and the selector may be integrated on a circuit chip. Additionally, the VCO, the multiplexer, and the selector may be fabricated using complementary metal oxide semiconductor (CMOS) components. The plurality of electronic circuit devices may be at least one of analog circuit devices, digital circuit devices, and mixed signal devices. Furthermore, the VCO may control the frequency of the oscillating test signal based upon one of the first and second voltages.

[0011] A method for testing a circuit path according to the invention includes generating first and second voltages, generating a controllable frequency oscillating test signal having a controllable amplitude defined between the first and second voltages using a voltage controlled oscillator (VCO), and selectively connecting one of the oscillating test signal, the first voltage, and the second voltage to the circuit path. At least one of the first and second voltages may be controlled so that the VCO generates the oscillating test signal to selectively have one of an amplitude greater than, less than, and equal to an amplitude of an output of the circuit path. Also, the circuit path may include a plurality of electronic circuit devices connected together.

[0012] Moreover, the method may also include measuring at least one electrical parameter of the circuit path. Measuring may include measuring the at least one parameter using a parametric analyzer. Additionally, the at least one electrical parameter may include at least one of transconductance, maximum current drive, and threshold voltage. The method may also include disconnecting the oscillating test signal, the first voltage, and the second voltage from the circuit path prior to measuring. Furthermore, the method may include controlling the frequency of the oscillating test signal based upon one of the first and second voltages.

[0013] FIG. 1 is a schematic block diagram of a tester for a circuit path according to the present invention.

[0014] FIGS. 2-4 are graphs illustrating transconductance (g_m) and maximum current drive (I_dsat) degradation over time for a circuit path tested according to the present invention under various operating conditions.

[0015] FIG. 5 is a graph illustrating variations in the controllable frequency oscillating test signal of the present invention with voltage.

[0016] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

[0017] Referring now to the schematic block diagram of FIG. 1, an integrated circuit (or circuit chip) 10 including a tester according to the present invention for testing a circuit path 11 of the integrated circuit is now described. The tester includes a voltage controlled oscillator (VCO) 12 for generating a controllable frequency oscillating test signal. The oscillating test signal has a controllable amplitude defined between first and second voltages V_DD, V_SS.

[0018] At least one of the first and second voltages V_DD, V_SSmay be controllable so that the VCO 12 generates the oscillating test signal to selectively have one of an amplitude greater than, less than, and equal to an amplitude of an output VBULK of the circuit path 11. Making the amplitude of the oscillating test signal greater than the output VBULK of the circuit path 11 provides a voltage overshoot thereto during a stressing portion of the testing.

[0019] Likewise, making the amplitude of the oscillating test signal less than the output of the circuit patch provides a voltage undershoot thereto. Furthermore, the VCO 12 also controls the frequency of the oscillating test signal based upon one of the first and second voltages V_DD, V_SS. As such, the circuit path 11 may be stressed using voltage overshoots and undershoots with or without frequency variations according to the present invention.

[0020] The tester may further include a multiplexer 13 for selectively connecting one of the oscillating test signal, the first voltage V_DD, and the second voltage V_SSto the circuit path 11. The multiplexer 13 thereby allows predetermined testing patterns to be applied to the circuit path 11 using the oscillating test signal, the first voltage V_DD, and the second voltage V_SS, as will be appreciated by those of skill in the art. A selector 14 selectively connects the multiplexer 13 to the circuit path 11 so that the circuit path 11 may be decoupled after the stressing has taken place. This allows various electrical parameters to be measured, as will be discussed further below.

[0021] The selector 14 may provide the selective connection responsive to an external signal V_GMEASURE, for example. That is, the testing patterns are applied to the circuit path 11 during stressing thereof and decoupled therefrom during measurement of the electrical parameters responsive to the signal V_GMEASURE. The circuit path 11 is supplied with a stress voltage V_Dand the second voltage V_SSduring the stressing and measurement, which will be discussed further below.

[0022] The circuit path 11, the VCO 12, the multiplexer 13, and the selector 14 may be integrated on the circuit chip 10, as schematically illustrated in FIG. 1. The VCO 12, the multiplexer 13, and the selector 14 may be fabricated using complementary metal oxide semiconductor (CMOS) components, for example, as will be discussed further below. Also, those of skill in the art will appreciate that the tester of the present invention may be used with electronic circuit devices such as analog circuit devices, digital circuit devices, and/or mixed signal devices. The circuit path 11 may include a single electronic circuit device or a plurality of such devices connected together.

[0023] A method for testing the circuit path 11 according to the invention includes generating the first and second voltages V_DD, V_SS, generating the oscillating test signal having a controllable amplitude defined between the first and second voltages using the VCO 12, and selectively connecting one of the oscillating test signal, the first voltage V_DD, and the second voltage V_SSto the circuit path. At least one of the first and second voltages V_DD, V_SSmay be controlled so that the VCO 12 generates the oscillating test signal to selectively have one of an amplitude greater than, less than, and equal to the amplitude of the output of the circuit path 11.

[0024] Moreover, the method may also include measuring at least one electrical parameter of the circuit path. Measuring may include measuring the at least one electrical parameter using a parametric analyzer (not shown). Additionally, the at least one electrical parameter may include at least one of transconductance (g_m), maximum current drive (I_dsat), and threshold voltage (V_t). The method may also include disconnecting the oscillating test signal, the first voltage V_DD, and the second voltage V_SSfrom the circuit path 11 prior to measuring the at least one electrical parameter, as described above.

[0025] The following example is provided to further illustrate stressing of the circuit path 11 and measurement of the above described electrical parameters according to the invention.

[0026] In this example, the effect of input voltage swing on device aging in an inverter (hereafter “device under test” or “DUT”) was measured, and the results are compared to those of individual transistors. The use of a circuit path 11 having a single circuit element (i.e., the DUT) provides for ease of illustration of the present invention. Of course, those of skill in the art will appreciate that the present invention may easily be extended to study the aging behavior of devices in other configurations by replacing the DUT with a circuit path including a plurality of electronic circuit devices.

[0027] The amplitude of the oscillating test signal during stressing was varied over a voltage range from −2 to +2 V. Of course, a larger voltage range may also be used according to the present invention. This variable amplitude allows the effects of clock undershoot and overshoot to be quantitatively estimated on device aging at the gate level. The VCO 12 used was a voltage-controlled ring oscillator which generated the oscillating test signal over a frequency range of 15-400 MHZ.

[0028] The DUT used was a single stage inverter and was stressed in a frequency range of about 25-30 MHZ. Channel metal oxide semiconductor (NMOS) transistor parameters, such as transconductance (g_m), maximum current drive (I_dsat), and threshold voltage (V_t), were measured by an external parametric analyzer, as will be understood by those of skill in the art. A twin-tub, dual poly-silicon (n+ and p+) gate, 0.18 CMOS technology with a 42 Å thick gate oxide was used to fabricate the stressing test circuit (i.e., the VCO 12, multiplexer 13, and selector 14) described above.

[0029] The effects of applying a constant gate stress voltage and frequency while varying the stress voltage applied to the DUT are shown in FIG. 2. The variation of transconductance (g_m) was monitored as a function of stress time. For a constant ring oscillator frequency, the rise and fall transitions are fixed and aging occurs over the same time period for each stress voltage. It is known that pulsed DC aging behavior of individual NMOS transistors varies with bias conditions, and degradation is faster when the gate voltage swing is below the source-drain stress voltage. See, e.g., Snyder et al., noted above. Faster aging is attributed to increased hot carrier aging at lower gate-source voltages (V_GS). A similar behavior was observed in the present example. At large V_DD/VBULK values, higher electric fields at the drain edge significantly accelerated hot carrier aging of the NMOS device and led to faster g_mdegradation.

[0030] The input frequency was also varied by changing the first supply voltage V_DD. The total aging time (T_AC) is expressed as:

[0031] T_AC=f*t_eff  (1)

[0032] T_ACincreases at higher frequencies (f), i.e., at a higher first voltage V_DD. The parameter t_effis the effective aging time during a clock cycle. The frequency of an n-stage ring oscillator circuit is defined by: $\begin{array}{cc}f=\frac{1}{2*n*\left(t_r+t_f\right)}& \left(2\right)\end{array}$

[0033] and depends on the rise (t_r) and fall (t_f) times of the inverters, for example, that make up the oscillator. At higher V_DDvalues, the charging/discharging current increases and the inverters switch more rapidly, leading to faster oscillating test signal frequencies. Since hot carrier aging occurs mostly during the rise and fall transitions, the effective aging time t_effwill decrease with faster switching times.

[0034] Turning now to FIGS. 3 and 4, results obtained using the tester of the present invention for two different bias and input conditions will now be discussed. The input voltage VIN swing to the DUT was varied between ±0.5 V relative to the output voltage VBULK swing for these examples. Interestingly, a strong input dependence for low values of VBULK (<4.0) was observed, as shown in FIG. 2. NMOS aging is more pronounced for smaller values of VIN, i.e., lower stress frequencies. In contrast, for large values of VBULK (>4.0 V) the aging characteristics are identical irrespective of the input voltage VIN swing, as shown in FIG. 4.

[0035] For a constant input frequency, t_effis invariant and aging is accelerated at higher values of the stress voltage V_Ddue to increased hot carrier aging. However, if input swing is modified by changing V_DD, both the ring oscillator frequency and t_effare altered and there is some inconsistency in the results between the low and high V_D/VBULK values, as seen in FIGS. 3 and 4. The reason for this discrepancy is explained below. Ring oscillator frequency improves by 18% with supply voltage (V_DD), i.e., up to 4.5 V, as illustrated in FIG. 6. When VD equals 3.8 V, higher V_DDvalues increase the input frequency, and faster aging is expected according to equation (1). However, t_effdecreases at higher frequencies, as defined by equation (2), and thus dictates the hot carrier aging process. This leads to lower degradation at high V_DD/VIN values. At smaller V_DDvalues, t_effincreases and accelerates aging.

[0036] For a large V_Dof 4.5 V, the ring oscillator frequency and t_efftends to saturate for all values of V_DDbetween 4.0-5.0 V, and aging becomes independent of VIN for a constant V_D. These results suggest that if rise and fall times of the input signal are not altered, voltage over/under shoots of ±0.5 V in input clock signals do not significantly change the aging characteristics of NMOS devices in circuits. Such conditions occur when the input clock feeds through the gate-drain capacitance during circuit operation. For cases when the input rise/fall times are altered, e.g., voltage overshoot due to interconnect cross-capacitance, device aging will be determined by changes to the effective aging time t_eff.

[0037] Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed, and that other modifications and embodiments are intended to be included within the scope of the appended claims.