Semiconductor device and method of fabricating the same

[0002] This application is a Divisional of application Ser. No. 09/065,692 filed Apr. 24, 1998.

[0003] 1. Field of the Invention

[0004] The present invention relates to a semiconductor device utilizing a semiconductor thin film and to techniques for fabricating such a semiconductor device and, more particularly, to TFTs (thin-film transistors) utilizing a crystalline film containing silicon.

[0005] The semiconductor device referred to herein embraces every kind of device that functions by making use of a semiconductor. That is, the semiconductor device includes electrooptical devices (such as liquid crystal displays) and electronic devices on which such electrooptical devices are packed, as well as active components such as TFTs and MOSFETs (IGFETs). To make a clear distinction between two kinds of semiconductor devices, they will be referred to as the semiconductor device and as the display device, respectively.

[0006] 2. Description of the Prior Art

[0007] In recent years, techniques for fabricating semiconductor circuits with TFTs (thin-film transistors) formed on substrates have evolved rapidly. Especially, an active matrix display using a crystalline silicon film (polysilicon film) as a thin-film semiconductor and having a common substrate on which both peripheral circuits and a pixel matrix circuit are packed have reached a practical level.

[0008] Among various kinds of active matrix displays, the active matrix liquid crystal display (AMLCD) is being actively developed as a display device adapted for use in a notebook computer, projector, or other mobile device. According to the mode of operation, AMLCDs are classified into two major groups: transmissive LCD and reflective LCD.

[0009] Presently, high information content, bright liquid crystal displays are being urgently developed. Structures have been developed in which each pixel is as small as less than 30 μm in square to meet the XGA standard (1024×768 pixels) or the SXGA standard (1280×1024 pixels).

[0010] In the aforementioned AMLCD, a voltage applied to the liquid crystal layer changes the optical response characteristic, thus turning on and off light. An auxiliary capacitor is usually added to each pixel to compensate for leakage of electric charge held on the liquid crystal layer.

[0011] We have already disclosed a method of obtaining a crystalline silicon film by making use of a catalytic element (typified by nickel) for promoting crystallization, to form a crystalline film containing silicon (see Japanese Unexamined Patent Publication No. 130652/1995). In particular, regions crystallized by direct introduction of a catalytic element (hereinafter referred to as the vertically grown regions) and crystallized regions (hereinafter referred to as the laterally grown regions) around the regions in which the catalytic element has been introduced are formed.

[0012] However, almost all catalytic elements are metal elements and so if the catalytic elements are left after the crystallization, the reliability of the finished TFTs will be impaired.

[0013] It is an object of the present invention to provide a simplified process sequence for fabricating a semiconductor device, the process sequence including a process step for effectively removing or reducing the catalytic element.

[0014] A method of fabricating a semiconductor device in accordance with the present invention starts with maintaining a catalytic element in contact with the whole surface or parts of an amorphous silicon film containing silicon. Otherwise, the catalytic element is introduced in the amorphous silicon film. The catalytic element promotes crystallization of the silicon. Then, the amorphous silicon film is heat treated to crystallize those portions of the amorphous silicon film that should become active components. A chemical element selected from group VB (group 15) of the periodic table is introduced into regions adjacent to the portions becoming the active components and also into regions becoming the lower electrodes of auxiliary capacitors. Finally, a heat treatment is made to getter the catalytic element into the regions doped with the group VB (group 15) element.

[0015] Another method of fabricating a semiconductor device in accordance with the present invention starts with maintaining a catalytic element with the whole surface or parts of an amorphous silicon film containing silicon. Otherwise, the catalytic element is introduced into the amorphous silicon film. The catalytic element promotes crystallization of the silicon. Then, the amorphous silicon film is heat-treated to crystallize those portions of the amorphous silicon film that should become active components. A chemical element selected from group VB (group 15) of the periodic table is introduced into regions adjacent to the portions becoming the active components and also into regions becoming the lower electrodes of auxiliary capacitors. The regions containing group VB (group 15) element is heat-treated to getter the catalytic element into the regions doped with group VB (group 15) element. Finally, a heat treatment is performed in an ambient containing a halogen element to getter the catalytic element into the ambient.

[0016] A main object of the invention is to provide a simplified process sequence for gettering a catalytic element out of a crystalline film after an amorphous film containing silicon is crystallized using the catalytic element.

[0017] A method of gettering the catalytic element is now described briefly. One feature of the invention is to use the gettering effect of an element selected from group VB (group 15) of the periodic table. Another feature of the invention is to employ the combination of the gettering effect of the group VB (group 15) element and the gettering effect of a halogen element.

[0018] The typical examples of the above-described catalytic element include nickel (Ni), cobalt (Co), iron (Fe), palladium (Pd), platinum (Pt), copper (Cu), and gold (Au). Our experiment has shown that nickel is the optimum element.

[0019] Examples of the group VB (group 15) element that getters the catalytic element include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). The element that exhibits the most conspicuous effect is phosphorus (P).

[0020] As a typical example, nickel is used as the catalytic element, and phosphorus is used as the gettering element belonging to group VB (group 15). A heat treatment around 600° C. results in the phosphorus and nickel being stably bonded. At this time, they can assume bonded states Ni₃P, Ni₅P₂, Ni₂P, Ni₃P₂, Ni₂P₃, NiP₂, and NiP₃.

[0021] Examples of the halogen element that getters the catalytic element described above include fluorine (F), chlorine (Cl), and bromine (Br). Especially, where nickel is used as the catalytic element, chlorine is liberated as volatile nickel chloride into a gas phase.

[0022] Where nickel is used as the catalytic element that accelerates the crystallization of the amorphous film containing silicon as described above, the catalytic element in the crystalline film can be removed or reduced by the gettering effect of the group VB (group 15) element.

[0023] Furthermore, the catalytic element can be removed or reduced by the gettering effect either of a group VB (group 15) element or of a halogen element. Where both gettering effects are used, greater advantages can be obtained.

[0024] Other objects and features of the invention will appear in the course of the description thereof, which follows.

[0025] FIGS. 1A-1C are cross-sectional views of a semiconductor device, illustrating a process sequence for fabricating the device in accordance with the present invention;

[0026] FIGS. 2A-2B are cross-sectional views of a semiconductor device, illustrating another process sequence for fabricating the device in accordance with the present invention;

[0027] FIGS. 3A-3D are cross-sectional views of a semiconductor device, illustrating a further process sequence for fabricating the device in accordance with the present invention;

[0028] FIGS. 4A-4C are cross-sectional views of a semiconductor device, illustrating a still other process sequence for fabricating the device in accordance with the present invention;

[0029] FIGS. 5A-5C are cross-sectional views of a semiconductor device, illustrating a yet other process sequence for fabricating the device in accordance with the present invention;

[0030] FIGS. 6A-6C are cross-sectional views of a semiconductor device, illustrating an additional process sequence for fabricating the device in accordance with the present invention;

[0031] FIGS. 7A-7C are cross-sectional views of a semiconductor device, illustrating a yet further process sequence for fabricating the device in accordance with the present invention;

[0032] FIGS. 8A-8C are cross-sectional views of a semiconductor device, illustrating a still further process sequence for fabricating the device in accordance with the present invention;

[0033] FIGS. 9A-9C are cross-sectional views of a semiconductor device, illustrating a yet additional process sequence for fabricating the device in accordance with the present invention;

[0034] FIGS. 10A-10B are cross-sectional views of a semiconductor device, illustrating another process sequence for fabricating the device in accordance with the present invention;

[0035] FIGS. 11A-11C are cross-sectional views of a semiconductor device, illustrating another process sequence for fabricating the device in accordance with the present invention;

[0036] FIGS. 12A-12C are cross-sectional views of a semiconductor device, illustrating another process sequence for fabricating the device in accordance with the present invention;

[0037] FIGS. 13A-13C are cross-sectional views of a semiconductor device, illustrating another process sequence for fabricating the device in accordance with the present invention;

[0038] FIGS. 14A-14C are cross-sectional views of a semiconductor device, illustrating another process sequence for fabricating the device in accordance with the present invention;

[0039] FIG. 15 is a top plan view of a pixel region of a semiconductor device in accordance with the invention;

[0040] FIG. 16 is a top plan view of a pixel region of another semiconductor device in accordance with the invention;

[0041] FIG. 17 is a fragmentary cross section of a liquid crystal display in accordance with the invention;

[0042] FIG. 18 is a perspective view of an active matrix display substrate in accordance with the invention; and

[0043] FIGS. 19A-19F are views illustrating commercial products to which the invention is applied.

[0044] A method of fabricating a reflective liquid crystal display in accordance with the present invention is now described by referring to FIG. 1. In this first embodiment of the invention, a CMOS circuit and a pixel matrix circuit 2 are fabricated on the same substrate. The CMOS circuit is a fundamental circuit forming a peripheral circuit 1.

[0045] Note that the peripheral circuit 1 and the pixel matrix circuit 2 are not drawn to scale, for the sake of preparation of the figure. Rather, the pixel matrix circuit 2 is drawn in exaggerated size.

[0046] The peripheral circuit contains driver circuits typified by shift registers. Furthermore, the peripheral circuit contains logic circuits performing other signal processing. For instance, memories, D/A converters, operational amplifiers, pulse generators, and so on are contained in the logic circuit.

[0047] First, a glass substrate is prepared as a substrate 101 having an insulating surface. A silicon oxide film or the like is deposited as a buffer film on the substrate 101. Instead of the glass substrate, a silicon substrate or a ceramic substrate may be used.

[0048] Then, an amorphous silicon film 102 is formed to a thickness of 10 to 75 nm (preferably 15 to 45 nm) by plasma-enhanced CVD or LPCVD. Besides the amorphous silicon film, an amorphous semiconductor film containing silicon such as Si_XGe_1−X(0<X<1) may be employed.

[0049] Thereafter, the amorphous silicon film 102 is crystallized, using the technique disclosed in Japanese Unexamined Patent Publication No. 78329/1996. This technique is characterized in that a catalytic element is selectively introduced into an amorphous silicon film to obtain crystalline regions (laterally grown regions) grown substantially parallel to the substrate.

[0050] Specifically, a mask insulator film 103 consisting of a silicon oxide film is formed to a thickness of 50 to 150 nm on the amorphous silicon film 102. Then, the mask insulator film 103 is patterned to form first openings 104 and 105 in regions in which nickel will be introduced.

[0051] These first openings 104 and 105 are so created that the vicinities of regions becoming active components (TFTs in the present embodiment) will be exposed later. That is, the laterally grown regions are just formed in the regions becoming the active components.

[0052] Subsequently, a thin oxide film (not shown) is formed on the exposed surface of the amorphous silicon film. This process step may be UV-light irradiation in an oxygen ambient. This oxide film will improve the wetting characteristics during the next solution application step.

[0053] Thereafter, a solution (e.g., a solution of nickel acetate or nickel nitrate) containing 100 ppm by weight of a catalytic element (nickel in the present specification) that promotes crystallization of silicon is applied to the amorphous silicon film 102 and to the mask insulator film 103. A nickel-containing layer 106 is formed by spin coating (FIG. 1A).

[0054] Where this technique disclosed in the above-cited Patent Publication is used, approximately 2×10¹⁴atoms/cm²of nickel is held on the surfaces of those portions of the amorphous silicon film which are exposed through the first openings 104 and 105.

[0055] Under this condition, a heat treatment is performed for crystallization. This treatment is effected at a temperature of 500 to 700° C. (typically 550 to 650° C.) for 4 to 24 hours (typically 8 to 15 hours). This processing diffuses nickel into the film, forming regions of crystallized silicon film 107-110 (FIG. 1B).

[0056] The regions 107 and 108 are very heavily doped with nickel. The regions 109 and 110 are laterally grown regions in which crystallization has progressed laterally. The regions 109 and 110 contain about 5×10¹⁸to 1×10¹⁹atoms/cm³of nickel. The regions not crystallized are left amorphous.

[0057] These laterally grown regions take a crystalline structure in which needle-like or columnar crystals are arrayed regularly in a certain direction. The needle-like crystals are grown substantially parallel to each other. Macroscopically, they are grown in the same direction.

[0058] The mask insulator film 103 is again patterned to form a second opening 111, for forming an electrode portion that will become the lower electrode of an auxiliary capacitor later. It is also possible to form a resist mask having openings after removing the mask insulator film 103 completely.

[0059] Then, phosphorus (P) ions are introduced by ion implantation or plasma doping. Instead of the P ions, arsenic (As) ions may be advantageously used (FIG. 1C).

[0060] In the ion implantation step according to the present embodiment, the accelerating voltage is 5 to 25 kV, and the dose is 1×10¹³to 8×10¹⁵atoms/cm²(preferably 5×10¹³to 1×10¹⁵atoms/cm²). Because of these settings, the exposed portions of the amorphous silicon film are implanted with P ions at a dopant concentration of 5×10¹⁹to 2×10²¹ions/cm³.

[0061] The present embodiment is characterized in that the first openings 104 and 105 permitting introduction of nickel enable introduction of phosphorus. Phosphorus-doped regions 112 and 113 under the first openings 104 and 105 act also as gettering regions for collecting nickel.

[0062] A phosphorus-doped region 114 formed under the second opening 111 becomes the lower electrode of the auxiliary capacitor having N-type conductivity. At the same time, the P-doped region 114 serves as a gettering region for collecting nickel.

[0063] In this way, the process step for introducing P ions in order to form gettering regions acts also as a process step for forming the lower electrode of the auxiliary capacitor. This constitutes one of the most important features of the present invention.

[0064] After the implantation step, the mask insulator film 103 is removed, followed by thermal processing conducted at 400 to 700° C. (typically 550 to 600° C.) in a nitrogen ambient for 2 to 24 hours (typically 8 to 12 hours). This moves nickel from the laterally grown regions 109 and 110 toward P-doped regions 112-114 (FIG. 2A).

[0065] This process step may be carried out before the removal of the mask insulator film 103. It is also advantageous to disperse the phosphorus through the silicon film by performing laser annealing prior to the thermal processing. Where this laser annealing is effected, it is advantageous to perform the laser annealing after the removal of the mask insulator film 103. The laser light can be emitted by an excimer laser using an exciting gas of KrF, ArF, XeCl, or the like, a CO₂laser, or a YAG laser.

[0066] Thus, the nickel remaining in the laterally grown regions 109 and 110 is moved into the P-doped regions 112-114 by the gettering effect. This results in laterally grown regions 115 and 116 less doped with phosphorus. The gettering step using phosphorus element is disclosed by the present applicant in Japanese Unexamined Patent Publication No. 94607/1997 (FIG. 2A).

[0067] Although the P-doped regions 112-114 are made amorphous by the P-ion implantation step, this thermal processing recrystallizes these P-doped regions. We have confirmed by SIMS (secondary ion mass spectrometry) that the nickel concentration of the laterally grown regions 115 and 116 after the process step shown in FIG. 2A has decreased at least below 5×10¹⁷atoms/cm³, i.e., lower than the detection limit.

[0068] At this time, nickel is gettered and collected into the phosphorus-doped regions 112-114 and so these regions are heavily doped with nickel. Analysis by SIMS has revealed that the nickel concentration is as high as 1×10¹⁸to 1×10²⁰atoms/cm².

[0069] However, if nickel is left in the phosphorus-doped region 114 that will act as the lower electrode of the auxiliary capacitor later, no problems will take place provided it serves as the electrode. The phosphorus-doped regions 112 and 113 are not used at least in a channel region but can be used as source/drain regions. Essentially, the phosphorus-doped regions are removed when an active layer is formed. Hence, there arise no problems irrespective of whether the nickel is present or not.

[0070] After obtaining the state of FIG. 2A, the silicon film is patterned to form islands of active layer 117-119. The islands of active layer 117 and 118 mainly form N-type and P-type TFTs, respectively, of a CMOS circuit forming a peripheral circuit. The island of active layer 119 becomes a pixel TFT (N-type TFT in the present embodiment) forming a pixel matrix circuit.

[0071] Then, an oxide (not shown) formed on the silicon film surface is removed. Since contaminants in the silicon film are incorporated into the oxide on the surface, a clean silicon film surface can be obtained by removing the oxide.

[0072] Immediately thereafter, a silicon oxide film 120 becoming the gate insulator film is deposited to a thickness of 10 to 150 nm by plasma-enhanced CVD. Of course, low-pressure thermal CVD or sputtering may be used instead. Furthermore, ECR plasma CVD or high-density plasma CVD is used to advantage (FIG. 2B).

[0073] Then, islands of metallization layer 121-124 consisting only or chiefly of aluminum are formed. These islands of metallization layer 121-124 will form the gate electrode of a CMOS circuit or a pixel TFT. The island 124 will form the upper electrode of the auxiliary capacitor.

[0074] In the present embodiment, a triple-gate TFT is used as the pixel TFT and so the metallization layer 123 becoming electrodes are shown to be split into three. In practice, however, the metallization layer 123 is a continuously extending electrode.

[0075] After deriving the state of FIG. 3A, the two anodic oxidation steps are carried out. The following process steps between the anodization step and the ion implantation step depend on the techniques described by the present applicant in Japanese Unexamined Patent Publication No. 135318/1995. Therefore, for details of the conditions, see this Japanese Patent Publication.

[0076] After building up the islands of metallization layer 121-124, anodic oxidation is carried out within a 3% aqueous solution of tartaric acid to form porous islands of anodic oxide film 125-128. Subsequently, anodic oxidation is performed within an ethylene glycol solution containing a 3% tartaric acid, resulting in islands of non-porous anodic oxide film 129-132. After these two anodization steps, gate electrodes 133-135 and the upper electrode 136 of the auxiliary capacitor are defined.

[0077] Then, after deriving the state of FIG. 3B, using the gate electrode and the porous anodic oxide film as a mask, the gate insulator film 120 is etched by dry-etching techniques. This gives rise to islands of gate insulator film 137-140. The island of gate insulator film 140 acts as the insulating film of an auxiliary capacitor (FIG. 3C).

[0078] Then, as shown in FIG. 3D, the porous anodic oxide film, 125-128, is removed. A high-energy P ion implantation and a low-energy P ion implantation are performed. As a result, the source region 141 and the drain region 142 of an N-type TFT, a pair of lightly doped (LDD) regions 143, and a channel region 144 are formed.

[0079] In the present embodiment, in order to fabricate the pixel TFT from an N-type TFT, the source region 145 and the drain region 146 of a pixel TFT, a pair of lightly doped regions 147-149, and channel regions 150-152 are formed.

[0080] At this time, P ions are also introduced into the active layer of the P-type TFT. In consequence, regions 153 and 154 doped with P ions at the same concentration as the source/drain regions described above and a region 155 doped with P ions at the same concentration as the lightly doped regions are formed. No P ions are implanted into a region 156 at all; rather the P ion concentration is maintained. However, this region is substantially integrated with the pixel TFT and with the drain region 146.

[0081] Then, a resist mask 157 is placed to expose only the P-type TFT. A high-energy B ion implantation and a low-energy B ion implantation are carried out. This processing step converts all the P ion-doped regions 153-155 shown in FIG. 3D into the P-type, forming the source region 158 and the drain region 159 of a P-type TFT, a pair of lightly doped regions 160, and a channel region 161 (FIG. 4A).

[0082] Where the ion implantation steps described above are exploited, the source/drain regions of the N-type TFT and the P-type TFT can be fabricated with only one patterning step.

[0083] After the resist mask 157 has been removed, the implanted P and B ions are activated by furnace annealing, laser annealing, lamp annealing, or a combination thereof. At the same time, the crystallinity of the active layer deteriorated by the ion implantation is healed.

[0084] Then, a laminate film consisting of a silicon oxide layer and a silicon nitride layer is formed as a first interlayer dielectric film 162. Contact holes are created, and then source electrodes 163-165 and drain electrodes 166, 167 are formed (FIG. 4B).

[0085] An organic resinous film of polyimide, polyamide, polyimidamide, acrylic resin, or the like is formed as a second interlayer dielectric film 168 to a thickness of 0.5 to 3 μm (preferably 1.5 to 2.5 μm). The greatest feature of the organic resinous film is that it has a relative dielectric constant of about 2.0 to 3.4. Hence, the parasitic capacitance between adjacent conducting lines can be reduced greatly. That is, in a circuit that is required to be operated at high speeds such as a logic circuit, drops in operating speed can be effectively suppressed.

[0086] Thereafter, a contact hole is formed in the second interlayer dielectric film 168, and a pixel electrode 169 is formed. In the present embodiment, the pixel electrode 169 consists only or chiefly of aluminum.

[0087] Finally, the obtained TFT is totally heat-treated in a hydrogen ambient to perform hydrogen termination. Thus, the dangling bonds in the active layer are reduced. In this way, as shown in FIG. 4C, an active matrix display substrate on which both a CMOS circuit and pixel TFTs are packed is completed.

[0088] Then, a liquid crystal layer is sandwiched between the above-described active matrix display substrate and a counter substrate by a well-known cell assembly step, thus completing a reflective liquid crystal display.

[0089] The manufacturer may appropriately determine the fabricational parameters such as the kind of the liquid crystal material and the cell gap. In the present embodiment, a black mask is formed on the counter substrate. It may also be formed in required locations on the active matrix display substrate.

[0090] Another method of fabricating a reflective liquid crystal display in accordance with the invention is next described by referring to FIGS. 11A-11C. This method constitutes a second embodiment of the invention. In the present embodiment, a CMOS circuit and a pixel matrix circuit 2 are formed on the same substrate. The CMOS circuit is a fundamental circuit forming a peripheral circuit 1.

[0091] First, a quartz substrate 1101 is prepared as a substrate having an insulating surface. A buffer layer consisting of a silicon oxide film or the like may be deposited on the quartz substrate 1101. Instead of the quartz substrate, a silicon substrate or a ceramic substrate may be employed.

[0092] Then, an amorphous silicon film 1102 is formed to a thickness of 10 to 75 nm (preferably 15 to 45 nm) by plasma-enhanced CVD or LPCVD. It is also possible to use an amorphous semiconductor film containing silicon, such as Si_XGe_1−X(0<X<1), instead of the amorphous silicon film.

[0093] Thereafter, the amorphous silicon film 1102 is crystallized, using the technique disclosed in Japanese Unexamined Patent Publication No. 78329/1996. This technique is characterized in that a catalytic element is selectively introduced into an amorphous silicon film to obtain crystalline regions (laterally grown regions) grown substantially parallel to the substrate.

[0094] Specifically, a mask insulator film 1103 consisting of a silicon oxide film is formed to a thickness of 50 to 150 nm on the amorphous silicon film 1102. Then, the mask insulator film 1103 is patterned to form first openings 1104 and 1105 in regions into which nickel will be introduced.

[0095] These first openings 1104 and 1105 are so created that the vicinities of regions becoming active components (TFTs in the present embodiment) will be exposed later. That is, the laterally grown regions are just formed in the regions becoming the active components.

[0096] Subsequently, a thin oxide film (not shown) is formed on the exposed surface of the amorphous silicon film. This process step may be UV-light irradiation in an oxygen ambient. This oxide film will improve the wetting characteristics during the next solution application step.

[0097] Thereafter, a solution (e.g., a solution of nickel acetate or nickel nitrate) containing 100 ppm by weight of a catalytic element (nickel in the present specification) that promotes crystallization of silicon is applied to the amorphous silicon film 1102 and to the mask insulator film 1103. A nickel-containing layer 1106 is formed by spin coating (FIG. 11A).

[0098] Where this technique disclosed in the above-cited Patent Publication is used, approximately 2×10¹⁴atoms/cm²of nickel is held on the surfaces of those portions of the amorphous silicon film which are exposed through the first openings 1104 and 1105 formed in the mask insulator film.

[0099] Under this condition, a heat treatment is performed for crystallization. This treatment is effected at a temperature of 500 to 700° C. (typically 550 to 650° C.) for 4 to 24 hours (typically 8 to 15 hours). This processing diffuses nickel into the film, forming regions of crystalline silicon film 1107-1110 (FIG. 11B).

[0100] The regions 1107 and 1108 are very heavily doped with nickel. The regions 1109 and 1110 are laterally grown regions in which crystallization has progressed laterally. The regions 1109 and 1110 contain about 5×10¹⁸to 1×10¹⁹nickel atoms/cm³. The regions not crystallized are left amorphous.

[0101] These laterally grown regions take a crystalline structure in which needle-like or columnar crystals are arrayed regularly. The needle-like crystals are grown substantially parallel to each other. Macroscopically, they are grown in the same direction.

[0102] The mask insulator film 1103 is again patterned to form a second opening 1111, for forming an electrode portion that will become the lower electrode of an auxiliary capacitor later. It is also possible to form a resist mask having openings after removing the mask insulator film 1103 completely.

[0103] Then, phosphorus (P) ions are introduced by ion implantation or plasma doping. Instead of the P ions, arsenic (As) ions may be advantageously used (FIG. 11C).

[0104] In the ion implantation step according to the present embodiment, the accelerating voltage is 5 to 25 kV, and the dose is 1×10¹³to 8×10¹⁵atoms/cm²(preferably 5×10¹³to 1×10¹⁵atoms/cm²). Because of these settings, the exposed portions of the amorphous silicon film are implanted with P ions at a dopant concentration of 5×10¹⁹to 2×10²¹atoms/cm³.

[0105] The present embodiment is characterized in that the first openings 1104 and 1105 permitting introduction of nickel enable introduction of phosphorus. Phosphorus-doped regions 1112 and 1113 under the first openings 1104 and 1105 act also as gettering regions for collecting nickel.

[0106] A phosphorus-doped region 1114 formed under the second opening 1111 becomes the lower electrode of the auxiliary capacitor having N-type conductivity. At the same time, the P-doped region 1114 serves as a gettering region for collecting nickel.

[0107] In this way, the process step for introducing P ions to form gettering regions acts also as a process step for forming the lower electrode of the auxiliary capacitor. This constitutes one of the most important features of the present invention.

[0108] After the implantation step, the mask insulator film 1103 is removed, followed by thermal processing conducted at 400 to 700° C. (typically 550 to 600° C.) in a nitrogen ambient for 2 to 24 hours (typically 8 to 12 hours). This moves nickel from the laterally grown regions 1109 and 1110 toward P-doped regions 1112-1114 (FIG. 12A).

[0109] This process step may be carried out before the removal of the mask insulator film 1103. It is also advantageous to disperse the phosphorus through the silicon film by performing laser annealing prior to the thermal processing. Where this laser annealing is effected, it is advantageous to perform the laser annealing after the removal of the mask insulator film 1103. The laser light can be emitted by an excimer laser using an exciting gas of KrF, ArF, XeCl, or the like, a CO₂laser, or a YAG laser.

[0110] Thus, the nickel remaining in the laterally grown regions 1109 and 1110 is moved into the P-doped regions 1112-1114 by the gettering effect. This results in laterally grown regions 1115 and 1116 less doped with nickel. The gettering step using phosphorus element is disclosed by the present applicant in Japanese Unexamined Patent Publication No. 94607/1997 (FIG. 12A)

[0111] Although the P-doped regions 1112-1114 are made amorphous by the P-ion implantation step, this thermal processing recrystallizes these P-doped regions.

[0112] After obtaining the state of FIG. 12A, thermal processing is performed in an ambient containing a halogen element. In the present embodiment, the ambient consists of oxygen O₂containing 0.5 to 10% (typically 3%) by volume of hydrogen chloride (HCl) (FIG. 12B).

[0113] Besides the HCl, one or more compounds selected from the group consisting of HF, NF₃, HBr, Cl₂, ClF₃, BCl₃, F₂, Br₂, and other components containing a halogen can be used. In addition, hydrogenated halogens can be used.

[0114] Preferably, this thermal processing is performed above 700° C. (typically 800 to 1000° C., 950° C. in the present embodiment) to carry out gettering of nickel, using chlorine, effectively. This processing exhaustively removes nickel from the whole crystalline silicon film or reduces the nickel concentration.

[0115] Prior to this thermal processing, the phosphorus-doped regions 1112-1114 have been crystallized. Therefore, the thermal diffusion of the P ions can be minimized though the thermal processing is effected at a high temperature.

[0116] We have confirmed by SIMS (secondary ion mass spectrometry) that the nickel concentration of the laterally grown regions 1117 and 1118 after the process step shown in FIG. 12B has decreased at least below 5×10¹⁷atoms/cm³, i.e., lower than the detection limit.

[0117] At this time, nickel is gettered even from the phosphorus-doped regions 1112-1114. Although these are heavily doped with nickel, the concentration can be decreased below 5×10¹⁷atoms/cm³in the same way as the laterally grown regions, depending on the gettering processing conditions in an ambient containing a halogen element.

[0118] A large amount of nickel is gettered and collected into the phosphorus-doped region 1119 becoming the lower electrode of the auxiliary capacitor. Therefore, it is considered that even if gettering is effected using a halogen element, the lower electrode of the auxiliary capacitor for the finished TFT is more heavily doped with nickel than the channel region.

[0119] If nickel is left in the lower electrode of the auxiliary capacitor, no problems will take place provided it serves as the electrode. The phosphorus-doped regions 1112 and 1113 are not used at least in a channel region but can be used as source/drain regions. Essentially, the phosphorus-doped regions 1112 and 1113 are removed when an active layer is formed. Hence, the presence or absence of the nickel poses no problems.

[0120] Because of this thermal processing, the halogen element is incorporated into the laterally grown regions. Therefore, in the final active layers (laterally grown regions), the halogen element exists at a concentration of 1×10¹⁵to 1×10²⁰atoms/cm³.

[0121] Our analysis by TEM (transmission electron microscopy) has shown that these laterally grown regions 1117 and 1118 take a crystalline structure in which rodlike or flat rodlike crystals are arrayed regularly in a given direction.

[0122] This crystal structure is similar in features to the aforementioned laterally grown regions. However, our various analyses had led us to estimate that the boundaries between the rodlike microcrystallites (that may be referred to as needle-like crystals) consist of continuous lattices, show very good matching, and are electrically inactive, because the electrical characteristics of a TFT using an active layer consisting of a crystalline silicon film of such a crystal structure are better than those of a MOSFET fabricated on a single-crystal silicon. Details of this crystal structure are described by the present applicant in Japanese Patent Application No. 335152/1996, filed on Nov. 29, 1996.

[0123] After obtaining the state of FIG. 12B, the silicon film is patterned to form islands of active layer 1120-1222. The islands of active layer 1120 and 1121 mainly form N- and P-type TFTs, respectively, of a CMOS circuit forming a peripheral circuit. The island of active layer 1122 becomes a pixel TFT (N-type TFT in the present embodiment) forming a pixel matrix circuit.

[0124] Then, an oxide (not shown) formed on a surface of the silicon film is removed. Since contaminants in the silicon film are incorporated into the oxide on the surface, a clean silicon film surface can be obtained by removing the oxide.

[0125] Immediately thereafter, a silicon oxide film 1123 becoming the gate insulator film is deposited to a thickness of 10 to 150 nm by plasma-enhanced CVD. A thermal treatment is made again above 700° C. Preferably, this processing is performed in an ambient containing a halogen element as described above. In this case, the conditions can be made the same as the above-described conditions (FIG. 12C).

[0126] The film quality of the gate insulator film 1123 can be effectively improved by performing a heat treatment in an inert ambient as the final step of this thermal processing.

[0127] It can be expected that this thermal processing will further remove the nickel remaining in the active layer. A thermal oxide film is formed at the interface between the active layer, 1120-1122, and the gate insulator film 1123. In consequence, a good active layer-gate insulator film interface having less interface levels can be obtained.

[0128] Then, the same process steps as the steps of the first embodiment illustrated in FIGS. 3 and 4 are carried out to complete the semiconductor device.

[0129] A third embodiment of the invention provides a method of forming a crystalline silicon film by means different from those used in the first and second embodiments. The process sequence of this third embodiment is similar to the process sequence of the first and second embodiments except for the steps illustrated in FIGS. 1A, 1B, 1C (the first embodiment) or the steps illustrated in FIGS. 11A, 11B, 11C (the second embodiment), i.e., the steps performed prior to the gettering step using phosphorus element. Therefore, only these different steps are next described.

[0130] In the present embodiment, the method of forming vertically grown regions as described in Japanese Unexamined Patent Publication No. 130625/1995 is utilized as a means for crystallizing the amorphous silicon film.

[0131] In FIG. 5A, there are shown a substrate 501 and an amorphous silicon film 502. Where the second embodiment is used, the substrate 501 is a quartz substrate. Where a vertically grown region is formed, any mask insulator film as used in the first or second embodiment is not necessary. A nickel-containing layer 503 is formed over the whole surface of the amorphous silicon film 502.

[0132] The nickel concentration of the solution containing nickel is 10 ppm by weight. At the surface of the amorphous silicon film, the concentration is about 3×10¹³atoms/cm².

[0133] Under this condition, a heat treatment is made to crystallize the amorphous film. In the present embodiment, the heat treatment is performed at 600° C. for 4 hours. As a result, the whole amorphous silicon film 502 is crystallized. Thus, a crystalline silicon film 504 that is known as a vertically grown region is obtained (FIG. 5B).

[0134] Then, a resist mask 505 is formed. Openings 506-508 permitting introduction of P ions are formed in the resist mask 505. This is followed by implantation of P ions. Consequently, phosphorus-doped regions 509-511 are formed (FIG. 5C).

[0135] At this time, the regions 509 and 510 in which P ions are introduced from the openings 506, 507 act as gettering regions that collect nickel. If these gettering regions are spaced too remotely from the portions where active components should be fabricated, the gettering effect decreases. Therefore, the gettering regions are preferably adjacent to the portions where the active components should be fabricated.

[0136] The region 511 in which the P ions are introduced from the opening 508 acts as the lower electrode of the auxiliary capacitor. Of course, the region serves as a gettering region as well.

[0137] As a result, a state as shown in FIG. 5C is obtained. Then, the process sequence is carried out in the same way as in the first or second embodiment described above, thus completing a semiconductor device.

[0138] A fourth embodiment of the invention gives an example in which vertically grown regions and laterally grown regions are separately used on the same substrate in manufacturing a semiconductor device. The process sequence of this fourth embodiment is similar to the process sequences of the first, second, and third embodiments except up to the process step for performing gettering using phosphorus element. Therefore, only the characteristic step is described below.

[0139] Referring to FIG. 6A, there are shown a substrate 601 and an amorphous silicon film 602. Where the second embodiment described above is employed, the substrate 601 is a quartz substrate. In the present embodiment, a peripheral circuit is composed of laterally grown regions. A pixel matrix circuit is composed of vertically grown regions. Therefore, a mask insulator film 603 is not formed in regions 2 becoming the pixel matrix circuit. Openings 604 are formed at required locations in regions 1 becoming the peripheral circuit.

[0140] A solution containing nickel is applied and a nickel-containing layer 605 is formed by spin coating. At this time, the nickel concentration of the solution is set to 100 ppm by weight in the same way as in the first and second embodiments described above. If the concentration is less than this value, there is the possibility that the growth distance of the laterally grown regions does not reach a desired length (FIG. 6A).

[0141] Under this condition, a heat treatment is performed for crystallization. In the present embodiment, the heat treatment is made at 600° C. for 8 hours to achieve sufficient lateral growth. Thus, in regions becoming peripheral circuits, a nickel-doped region (that can also be referred to as a vertically grown region) 606 and a laterally grown region 607 are formed. In regions becoming the pixel matrix circuit, the whole surface of the amorphous silicon film 602 is crystallized, thus forming a vertically grown region 608 (FIG. 6B).

[0142] After removing the mask insulator film 603, a resist mask 609 provided with openings 610-612 is formed. P ions are implanted to form P-doped regions 613-615 (FIG. 6C).

[0143] In the same way as in the first, second, and third embodiments, the phosphorus-doped regions 613 and 614 act as gettering regions that collect nickel. The phosphorus-doped region 615 serves as the lower electrode of an auxiliary capacitor. Of course, the phosphorus-doped region 615 acts also as a gettering region. As a result, a state as shown in FIG. 6C is obtained. Subsequently, the process sequence is carried out in the same way as in the first and second embodiments to manufacture a semiconductor device.

[0144] A fifth embodiment of the present invention is now described. In this embodiment, vertically grown regions and the laterally grown regions are used for separate purposes with a structure different from the structure of the fourth embodiment. The process sequence is described again only up to the gettering step using phosphorus element.

[0145] Referring to FIG. 7A, there are shown a substrate 701 and an amorphous silicon film 702. Where the second embodiment is used, the substrate is a quartz substrate. In the present embodiment, a peripheral circuit is composed of vertically grown regions. A pixel matrix circuit is composed of laterally grown regions. Therefore, a mask insulator film 703 is not formed in regions 1 becoming the peripheral circuit. Openings 704 are formed at required locations in regions 2 becoming the pixel matrix circuit.

[0146] A solution containing nickel is applied and a nickel-containing layer 705 is formed by spin coating. At this time, the nickel concentration of the solution is set to 100 ppm by weight in the same way as in the fourth embodiment described above (FIG. 7A).

[0147] Under this condition, a heat treatment is performed for crystallization. In the present embodiment, the heat treatment is made at 600° C. for 8 hours to achieve sufficient lateral growth. Thus, in regions becoming a pixel matrix circuit, a vertically grown region 706 and a laterally grown region 707 are formed, using introduction of nickel. In regions becoming the peripheral circuits, the whole surface of the amorphous silicon film 702 is crystallized, thus forming a vertically grown region 708 (FIG. 7B).

[0148] After removing the mask insulator film 703, a resist mask 709 provided with openings 710-712 is formed. P ions are implanted to form P-doped regions 713-715 (FIG. 7C).

[0149] In the same way as in the first through fourth embodiments, the phosphorus-doped regions 713 and 714 act as gettering regions that collect nickel. The phosphorus-doped region 715 serve as the lower electrode of an auxiliary capacitor. Of course, the phosphorus-doped region 715 acts also as a gettering region. As a result, a state as shown in FIG. 7C is obtained. Subsequently, the process sequence is carried out in the same way as in the first or second embodiment to manufacture a semiconductor device.

[0150] A sixth embodiment of the present invention gives an example in which the region forming the lower electrode of the auxiliary capacitor is exploited as a nickel-doped region. The process sequence of the present embodiment is described again up to the gettering step using phosphorus element.

[0151] Referring to FIG. 8A, there are shown a substrate 801 and an amorphous silicon film 802. Where the second embodiment is used, the substrate is a quartz substrate. A mask insulator film 803 is formed on the amorphous silicon film 802. Openings 804 and 805 are formed in the mask insulator film 803. The present embodiment is characterized in that the opening 805 is formed in a region that will become the lower electrode of the auxiliary capacitor later.

[0152] A solution containing nickel is applied and a nickel-containing layer 806 is formed by spin coating. At this time, the nickel concentration of the solution is set to 100 ppm by weight in the same way as in the fourth and fifth embodiments described above (FIG. 8A).

[0153] Under this condition, a heat treatment is performed for crystallization. In the present embodiment, the heat treatment is made at 570° C. for 14 hours. The crystallization temperature is lowered to 560° C. in this way, whereby crystallization due to spontaneous nucleation can be prevented sufficiently; otherwise lateral, crystal growth would be stopped there.

[0154] In regions becoming peripheral circuits, this thermal treatment produces a nickel-doped, vertically grown region 807 and a nickel-doped, laterally grown region 808. In addition, in the regions becoming the pixel matrix circuit, a nickel-doped vertically grown region 809 and a laterally grown region 810 are produced (FIG. 8B).

[0155] Then, as shown in FIG. 8C, P ions are implanted while using the mask insulator film 803 as a mask intact. Thus, phosphorus-doped regions 811 and 812 are formed. Then, the process sequence is performed in the same way as in the first and second embodiments described above to manufacture a semiconductor device.

[0156] In the present embodiment, the mask insulator film 803 already used for introduction of nickel can be used intact as a mask for a phosphorus implant. Consequently, the manufacturing process can be simplified.

[0157] A seventh embodiment of the invention gives an example in which no nickel is introduced into the pixel matrix circuit at all. In this configuration, the peripheral circuit may be made either of vertically grown regions or of laterally grown regions. In the present embodiment, the peripheral circuit consists of laterally grown regions.

[0158] Referring to FIG. 9A, there are shown a substrate 901, an amorphous silicon film 902, and a mask insulator film 903. In the present embodiment, in regions 1 becoming peripheral circuits, openings 904 are formed in the mask insulator film 903. No openings are formed in regions 2 becoming the pixel matrix circuit.

[0159] A solution containing nickel is applied and a nickel-containing layer 905 is formed by spin coating. At this time, the nickel concentration of the solution is set to 100 ppm by weight (FIG. 9A).

[0160] Under this condition, a heat treatment is conducted for crystallization. In the present embodiment, this crystallization step is performed at 560° C. for 20 hours. This heat treatment forms a vertically grown region 906 and a laterally grown region 907 owing to nickel implants. An amorphous region 908 is left in regions becoming the pixel matrix circuit because no nickel is implanted at all (FIG. 9B).

[0161] After removing the mask insulator film 903, a resist mask 909 provided with openings 910 and 911 is formed. P ions are introduced to form phosphorus-doped regions 912 and 913. At this time, these phosphorus-doped regions 912 and 913 are once rendered amorphous (FIG. 9C).

[0162] Then, a heat treatment is made at 600° C. for about 24 hours to carry out a gettering step using phosphorus element. This process step getters the nickel contained in the laterally grown region 914 into a phosphorus-doped region 915 (FIG. 10A).

[0163] The phosphorus-doped region 915 becoming a gettering region is recrystallized by the heat treatment. In addition, a phosphorus-doped region 916 acting as the lower electrode of an auxiliary capacitor later is recrystallized by this heat treatment.

[0164] Spontaneous nucleation promotes the crystallization of the amorphous region 908, which in turn becomes a crystalline region 917. In this way, the phosphorus-doped region 916 becoming the lower electrode of the auxiliary capacitor does not act as a gettering region and so this region 916 contains almost no nickel.

[0165] After obtaining the state of FIG. 10A, the film is patterned to etch away unnecessary portions. In this manner, islands of active layer 918-920 are formed. Then, a gate insulator film 921 is formed by process steps described in the first embodiment. The resulting state is shown, in FIG. 10B. Thereafter, a semiconductor device is manufactured by process steps similar to those of the first embodiment.

[0166] An eighth embodiment of the present invention gives an example in which no nickel is implanted at all into the pixel matrix circuit. In this configuration, the peripheral circuit may be made either of vertically grown regions or of laterally grown regions. In the present embodiment, the peripheral circuit consists of laterally grown regions.

[0167] Referring to FIG. 13A, there are shown a quartz substrate 1301, an amorphous silicon film 1302, and a mask insulator film 1303. In the present embodiment, in regions becoming peripheral circuits, openings 1304 are formed in the mask insulator film 1303. No openings are formed in regions becoming the pixel matrix circuit.

[0168] A solution containing nickel is applied and a nickel-containing layer 1305 is formed by spin coating. At this time, the nickel concentration of the solution is set to 100 ppm by weight (FIG. 13A).

[0169] Under this condition, a heat treatment is conducted for crystallization. In the present embodiment, the crystallization step is performed at 560° C. for 20 hours. This heat treatment forms a vertically grown region 1306 and a laterally grown region 1307 owing to nickel implants in the regions 1 becoming the peripheral circuits. An amorphous region 1308 is left in regions 2 becoming the pixel matrix circuit because no nickel is implanted at all (FIG. 13B).

[0170] After removing these mask insulator film 1303, a resist mask 1309 provided with openings 1310 and 1311 is formed. P ions are introduced to form phosphorus-doped regions 1312 and 1313. At this time, these phosphorus-doped regions 1312 and 1313 are once rendered amorphous (FIG. 13C).

[0171] Then, a heat treatment is made at 600° C. for about 8 to 24 hours to carry out a gettering step using phosphorus element. This process step getters the nickel contained in the laterally grown region 1314 into a phosphorus-doped region 1315 (FIG. 14A).

[0172] The phosphorus-doped region 1315 becoming a gettering region is recrystallized by the heat treatment. In addition, a phosphorus-doped region 1316 acting as the lower electrode of an auxiliary capacitor later is recrystallized by this heat treatment.

[0173] The crystallization of the amorphous region 1308 progresses and this region becomes a crystalline region 1317. The extent to which the amorphous region crystallizes varies according to the heat treatment conditions. However, it may be considered that if the heat treatment is effected at 600° C. for more than 12 hours, the amorphous region crystallizes almost totally.

[0174] Then, a heat treatment is made in an ambient containing a halogen element. The action of the halogen element getters nickel. The conditions of this heat treatment are described in the first embodiment. At this time, the phosphorus-doped regions 1315 and 1316 have been already crystallized and, therefore, the thermal diffusion of phosphorus element is not large enough to induce problems (FIG. 14B).

[0175] A laterally grown region 1318 obtained by this process step has a peculiar crystal structure consisting of rodlike or flat rodlike crystals as described in the first embodiment. This region 1318 is a crystalline silicon film having excellent crystallinity.

[0176] The nickel collected in the phosphorus-doped region 1319 by the gettering step using the phosphorus element is almost fully gettered into a gaseous phase. Hence, this region 1319 is almost free of nickel.

[0177] A region 1320 has been already crystallized by the aforementioned heat treatment. Therefore, the crystallinity is improved greatly by a heat treatment at an elevated temperature. Experiment has proved that if the amorphous region is directly heat-treated as illustrated in FIG. 14B, the crystallinity of the resulting crystalline region is very poor. That is, where TFTs are fabricated, their electrical characteristics are poor.

[0178] After obtaining the state of FIG. 14B, the film is patterned to etch away portions excluding required portions. In this manner, islands of active layer 1321-1323 are formed. Then, a gate insulator film 1324 is formed by process steps described in the first embodiment. The resulting state is shown in FIG. 14C. Thereafter, a semiconductor device is manufactured by process steps similar to those of the second embodiment.

[0179] A ninth embodiment of the present invention gives an example in which lamp annealing is used as a heating method during the gettering step using phosphorus element as illustrated in FIG. 2A or 12A. RTA (rapid thermal annealing) is known as thermal processing using lamp annealing. In this technique, infrared light emitted by a halogen lamp or the like is directed at a sample to heat a thin film.

[0180] Where RTA is used as the thermal processing during the gettering step, a high-temperature annealing at 700 to 1100° C. can be completed in a short time of several seconds to several minutes. Since the temperature can be elevated compared with the case of furnace annealing, the gettering effect of the catalytic element is improved. Also, the processing time is much shorter. As a consequence, the throughput is improved greatly.

[0181] Additionally, the thermal treatment at high temperatures of 700 to 1100° C. realigns the silicon atoms existing near the grain boundaries in the crystalline silicon film. This promotes the passivation of the grain boundaries. That is, the crystal defects such as dangling bonds are reduced greatly, and fewer carriers are captured. As a whole, the crystallinity is improved drastically.

[0182] A tenth embodiment of the present invention gives an example in which ion implantation is employed in introducing a catalytic element (typically nickel). Preferably, the dose is adjusted to 0.5×10¹³to 1×10¹⁴atoms/cm²(preferably 2×10¹³to 2×10¹⁴atoms/cm²).

[0183] Where a catalytic element is implanted by ion implantation as in the present embodiment, the width, or the shorter side, of each opening is approximately 0.01 to 5 μm (typically 0.25 to 2 μm). That is, a sufficient amount of nickel can be introduced into the openings delineated by a fine-line pattern. Therefore, the area occupied by the implanted catalytic element that forms a dead space in designing the circuitry can be reduced greatly. This increases the number of degrees of freedom in designing the circuitry.

[0184] In the first and second embodiments described above, the gate electrode consists only or mainly of aluminum. An eleventh embodiment of the invention gives an example in which the gate electrode uses a crystalline silicon film having one conductivity type. In addition, the gate electrode may be made of a metal material (such as titanium, tantalum, tungsten, or molybdenum) or a silicide of such a metal material, i.e., a compound of silicon.

[0185] In the first through eleventh embodiments, a planar TFT is used as a typical TFT structure. The invention can also be applied to a bottom-gate type TFT such as inverted-staggered TFT. Furthermore, the invention is applicable to MOSFETs fabricated on a silicon wafer, as well as to ordinary TFTs. In this way, the invention can be applied to every kind of semiconductor device, regardless of its structure. The invention is not limited to semiconductor devices of certain structures.

[0186] A thirteenth embodiment of the present invention gives an example of pixel array forming a pixel matrix circuit. This example is shown in FIG. 15. However, for simplicity, the pixel electrodes are not shown.

[0187] Referring to FIG. 15, an active layer 11 corresponds to the active layer 119 shown in FIG. 2C and to the active layer 1122 of FIG. 12C. In the present embodiment, the drain side of the active layer 11 extends throughout each pixel and acts also as the lower electrode 12 of an auxiliary capacitor.

[0188] A gate line 13 is located over the active layer 11 via a gate insulator film. The gate line 13 corresponds to the gate electrode 135 of FIG. 3B. Apart from the gate line 13, the upper electrode 14 of the auxiliary capacitor is formed and corresponds to the upper electrode 136 of FIG. 3B.

[0189] The pattern of the upper electrode 14 substantially conforms to the pattern of the active layer becoming the lower electrode. The upper electrode 14 forms the auxiliary capacitor occupying an area substantially equal to the area occupied by the pixel. The upper electrode 14 is electrically connected between adjacent pixels. The upper electrode 14 is connected in a parallel relation to the gate line so as not to cross the gate line. That is, the upper electrode of the auxiliary capacitor is maintained at the same potential for every pixel.

[0190] Then, a source electrode (source line) 15 and a drain electrode 16 are formed over the gate line 13 and over the upper electrode 14 of the auxiliary capacitor via a first interlayer dielectric film. These electrodes correspond to the source electrode 165 and the drain electrode 167, respectively, of FIG. 4B.

[0191] Thereafter, the interlayer dielectric film 168 and pixel electrodes 169 are formed as shown in FIG. 4C. Then, a well-known cell assembly step is carried out. In this way, a reflective liquid crystal display is completed. The structure according to the present embodiment makes it possible to secure sufficient capacitance by making a maximum use of the pixel area even if this area is reduced.

[0192] A fourteenth embodiment of the invention gives an example in which the present invention is applied to a transmissive liquid crystal display. The process sequence for fabricating TFTs is fundamentally the same as the process sequence described in the first and second embodiments and so detailed description of this process sequence is omitted.

[0193] In the first and second embodiments described above, the pixel electrode consists mainly of aluminum. In the present embodiment, however, an ITO film is made of a transparent conductive film. For the transmissive type, it is important to have a large aperture ratio. Therefore, the electric field-shielding film and the black matrix may be formed only in required locations in minimum size.

[0194] FIG. 16 is a top plan view of a transmissive liquid crystal display according to the present embodiment. For ease of understanding, in this top plan view, source/drain electrodes are shown to be formed. Accordingly, the pixel electrodes, the field-shielding film, the black matrix, and so on are omitted.

[0195] Referring to FIG. 16, an active layer 21 has a drain region where the lower electrode 22 of an auxiliary capacitor is formed. A gate electrode (gate line) 23 overlies the active layer 21. The upper electrode 24 of the auxiliary capacitor is located on the lower electrode 22. Since the lower electrode 22 is covered with the upper electrode 24, the lower electrode 22 is indicated by the broken lines. Of course, a gate insulator film is held between the lower electrode 22 and the upper electrode 24 to form an auxiliary capacitor.

[0196] A source electrode (source line) 25 is formed so as to intersect the gate electrode 23 and the upper electrode 24. This source electrode 25 is electrically connected with the source region of the active layer 21 in a contact portion 26.

[0197] In practice, a black matrix is formed so as to shield the active layer and the various conducting lines. Otherwise, an electric field-shielding film is formed between the upper and lower layers of metallization. A pixel electrode (not shown) is electrically connected with the drain region of the active layer 21 in a contact portion 27. The structure described thus far permits fabrication of a transmissive liquid crystal display. Obviously, the invention is not limited to the structure shown in FIG. 16.

[0198] A fifteenth embodiment of the invention is a simplified form of the reflective liquid crystal display described in the first or second embodiment. A cross section of this simplified display is shown in FIG. 17. Since the active matrix display device has been already described in the first and second embodiments, other structures are described below.

[0199] Referring to. FIG. 17, there are shown a transparent substrate 31 and a transparent conductive film 32. Color filters, an orientation film, and a black matrix (none of which are shown) may be formed on the transparent substrate 31. This subassembly is referred to, as the counter substrate.

[0200] A liquid crystal material 34 is sandwiched between the counter substrate and the active matrix display substrate and surrounded by a seal material 33. Since the present invention can accommodate every mode of operation such as ECB mode and guest-host mode, the liquid crystal material may be changed accordingly. Depending on the mode of operation, color filters may be necessary. Furthermore, depending on the mode of operation, polarizers may be needed.

[0201] In the present embodiment, no liquid crystal layer is disposed over the peripheral circuit to prevent parasitic capacitance between the peripheral circuit and the opposite transparent conductive film 32. Of course, a liquid crystal layer may be formed over the whole surface of the substrate.

[0202] FIG. 18 shows one example of arrangement of various circuits formed on the active matrix display substrate. There are shown a substrate 41, a buffer film 42, a pixel matrix circuit 43,a source driver circuit 44, a gate driver circuit 45, and a logic circuit 46.

[0203] The reflective liquid crystal display has been outlined. The transmissive liquid crystal display is essentially identical in structure with this reflective liquid crystal display. In this way, the invention can be applied to any liquid crystal display structure.

[0204] A sixteenth embodiment of the invention is an electrooptical device different from a liquid crystal display. Examples of this electrooptical device include electroluminescent device and electrochromic display.

[0205] A seventeenth embodiment of the present invention gives examples of commercial products using electrooptical devices. These examples are shown in FIGS. 19A-19F. Examples of commercial products utilizing the present invention include video camera, still camera, projector, head mount display, car navigational system, personal computer, portable intelligent terminals (such as mobile computers and portable telephones).

[0206] Referring next to FIG. 19A, there is shown a mobile telephone whose body is indicated by 2001. The body 2001 has a speech output portion 2002, a speech input portion 2003, a display device 2004, and operation switches 2005. An antenna 2006 is attached to the body 2001. The present invention can be applied to the display device 2004.

[0207] Referring to FIG. 19B, there is shown a video camera whose body is indicated by 2101. This body 2101 has a display device 2102, a speech input portion 2103, operation switches 2104, batteries 2105, and an image pickup portion 2106. The invention can be applied to the display device 2102.

[0208] Referring to FIG. 19C, the body of a mobile computer is indicated by 2201. This body 2201 has a display device 2205. A camera portion 2202 having both an image pickup portion 2203 and an operation switch 2204 is attached to the body 2201. The invention is applied to the display device 2205.

[0209] Referring to FIG. 19D, the body of a head mount display is indicated by 2301 and has display devices 2302. A band portion 2303 is attached to the body 2301. The invention is applied to the display devices 2302.

[0210] Referring to FIG. 19E, there is shown a rear projection system whose body is indicated by 2401. The body 2401 has a light source 2402, a display device 2403, a polarizing beam splitter 2404, and reflectors 2405, 2406. A screen 2407 is positioned on the body 2401. The invention is applied to the display device 2403.

[0211] Referring to FIG. 19F, there is shown a front projection system comprising a display body 2501 and a screen 2505 located in front of it. This body 2501 has a light source 2502, a display device 2503, and optics 2504. The invention is applied to the display device 2503.

[0212] As described thus far, the present invention can find quite extensive application and is applicable to display media in every technical field. Especially, where a liquid crystal display is used in a projection display such as a projector, very high resolution is required. In such cases, the invention provides very useful techniques.

[0213] In the present invention, the step for forming regions for gettering a catalytic element is made common with the step for forming the lower electrode of the auxiliary capacitor. This simplifies the manufacturing process. In consequence, the throughput and the yield are improved. This is economically advantageous.

[0214] Furthermore, a crystalline film produced by making use of the present invention has excellent crystallinity by the effect of a catalytic element. The gettering effect removes or reduces the catalytic element. Therefore, where the crystalline film is used as the active layer of a semiconductor device, excellent electrical characteristics and high reliability are imparted to the semiconductor device.