Pulse-width-modulated DC-DC converter with a ramp generator

[0002] This invention relates to DC-DC converters, and in particular to a pulse-width modulated (PWM) DC-DC converter.

[0003] PWM DC-DC converters are widely used, see for example Maxim data sheet MAX 731/MAX 752, 19-4672; Rev 2; dated February, 1993. To generate a constant output voltage, the output voltage is fed back through a voltage divider, compared with a ramp voltage from a ramp generator via an error amplifier and the comparator, and applied to a switching transistor to adjust the duty cycle for the constant output voltage. Connected between the comparator and the switching transistor is a flip-flop to which the clock frequency of a clock is applied for activating the switching transistor.

[0004] The stability limit of the feedback DC-DC voltage converter is a function of the current through an inductor and the inverse of the input voltage. The inductor current is a function of the load current and the input voltage. The loop gain is influenced by the inductor current and the inverse of the input voltage. It increases with increasing inductor current, whereas the poles of the system, i.e., the phase shifts of the loop gain, remain unchanged. This results in a reduction of the phase margin and thus produces instability.

[0005] To compensate for this effect, capacitors are connected in parallel with the voltage divider which influence the frequency response in such a way that sufficient stability is achieved for a particular range of load currents and of the input voltage. Since the poles, which are determined by the smoothing capacitor and the inductor, are located at very low frequencies, very large compensation capacitors are necessary. These are not suitable for monolithic integration.

[0006] Another measure to stabilize the DC-DC converter is to add a voltage proportional to the inductor current to the ramp voltage from the ramp generator with an adder. Use is made of a voltage proportional to the current through the switching transistor. Thus, at high inductor currents, the comparator switches earlier, so that the on time of the switching transistor and the loop gain are reduced. This compensation has the disadvantage that an additional, accurate adder is needed to compensate the ramp generator. Another disadvantage is that at a high inductor current, the loop gain is reduced already at the beginning of the turn-on cycle. As a result, the gain is also reduced at high input voltages, which adversely affects the accuracy of the output voltage.

[0007] An object of the invention is to provide an improved pulse-width-modulated DC-DC converter.

[0008] Briefly, according to the present invention, a PWM DC-DC converter comprises a series combination of a switching transistor and an inductor, with the switching transistor shunted by a smoothing capacitor in series with a switching element, so that an input voltage applied to the series combination of the switching transistor and the inductor is converted into a higher output voltage appearing across the smoothing capacitor; an error amplifier having its first input connected to a voltage divider, to which the output voltage can be applied, and having its second input connected to a reference voltage source; and a comparator having its first and second inputs connected, respectively, to the output of the error amplifier and to a ramp generator compensated a signal proportional to the current through the inductor, and having its output coupled to the gate electrode of the switching transistor. The compensated ramp generator provides an output voltage having a sawtooth waveform with a concave voltage, wherein the signal proportional to the current through the inductor is superimposable on the ramp voltage.

[0009] Through the concave rise of the ramp voltage generated by the compensated ramp generator, a higher slew rate of the ramp voltage is attained. As a result, the gain of the feedback DC-DC converter is reduced only at high inductor currents and low input voltages. Consequently, the frequency response of the DC-DC converter can be held constant despite changes in operating conditions, particularly despite changes in input voltage and load current. A smaller loop gain at high input voltages, and thus a loss of accuracy of the output voltage of the DC-DC converter, is prevented.

[0010] In one preferred embodiment of the invention, the ramp generator is designed so that the sum of a correction current, which is proportional to the inductor current, and a constant reference current is integrable in the ramp generator, so that the output voltage of the ramp generator rises quadratically. By this design of the ramp generator, a frequency response of the DC-DC converter independent of the operating conditions is achieved in a simple manner. It is not necessary to use a device occupying a large area, such as an accurate adder.

[0011] In another preferred embodiment of the invention, the integration of the sum of the correction current and the constant reference current is accomplished by supplying the correction current and the constant reference current to a capacitor which can be discharged by a parallel-connected switching element at the frequency of the signal applied to the gate electrode of the switching transistor. A quadratic rise of the ramp voltage is thus obtained in a simple manner.

[0012] To generate the correction current, a first amplifier may advantageously be provided, to whose input a voltage proportional to the inductor current can be applied, and whose output is connected through a resistor to a first node of constant potential, to which the correction current can be supplied. For the amplifier, a unity-gain buffer can be used. It can be implemented with a feedback operational amplifier. The operational amplifier may have an output stage that includes a first reference current source in series with a first transistor connected in common-source configuration.

[0013] To generate the constant node potential in the first node, a second operational amplifier may be provided. The first input of the second operational amplifier is connected to a first constant reference voltage source, and the second input is connected to the first node. The first node makes the constant node potential available over a low-resistivity path and is connected to the output of the second operational amplifier. The output stage of the second operational amplifier may include a second reference current source in series with a second transistor connected in common-source configuration. Thus, the sum of the correction current and the constant reference current can flow into the node.

[0014] In yet another preferred embodiment of the invention, a current mirror is provided which mirrors the sum of the correction current and the constant reference current produced at the node onto the capacitor. The current mirror can be formed from the first and second operational amplifiers and a third transistor connected in common-source configuration. The gate of the third transistor is connected to the gate of the first transistor, and the drain of the third transistor is connected to the capacitor. In another embodiment, the gate of the third transistor is connected to the gate of the second transistor, and the drain of the third transistor is connected to the capacitor via a second current mirror.

[0015] The first transistor and the second transistor may have a fixed relationship to each other in terms of their electrical characteristics. In the case of MOSFET transistors, this is achieved by fixed W/L (width/length) ratios of the transistors. With the first and second reference current sources, currents having a fixed relationship to each other may be generable. If the reference current sources generate equal currents, and the first and second transistors have the same electrical characteristics, equal conditions exist in the circuit, so that a good match of the individual circuit elements is obtained, whereby electrical influences and influences of temperature or of mask alignment errors are avoided.

[0016] The signal proportional to the inductor current can be determined from the voltage drop across the switching transistor. This is possible since the switching transistor is operated in the triode region, so that it behaves as a resistor. Methods of determining the inductor current are known from the prior art, for example from German patent application P 198 12 299.3. Advantageously, the circuit is implemented using monolithic integrated circuit technology.

[0017] These and other objects, features and advantages of the present invention will become apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.

[0018] FIG. 1 is a schematic circuit diagram of a pulse-width-modulated DC-DC converter in accordance with the invention;

[0019] FIG. 2 is a schematic circuit diagram of a compensated ramp generator in accordance with the invention;

[0020] FIGS. 3aand 3bare plots of inductor current as a function of time and voltage of the ramp generator of FIG. 2 as a function of time, respectively;

[0021] FIG. 4 is a schematic circuit diagram of one embodiment of a compensated ramp generator in accordance with the invention; and

[0022] FIG. 5 is a schematic circuit diagram of another embodiment of a compensated ramp generator in accordance with the invention.

[0023] FIG. 1 is a schematic illustration of a pulse-width modulated (PWM) DC-DC converter 1 according to the invention. The DC-DC converter 1 comprises a series combination of a switching transistor 2 and a inductor 3. Connected in parallel with the switching transistor 2 is a smoothing capacitor 4 in series with a switching element 5. With the DC-DC converter 1, an input voltage V_inapplied to the series combination of the switching transistor 2 and the inductor 3 is converted into a higher output voltage V_out, which appears across the smoothing capacitor 4. The output voltage V_outis fed back to the DC-DC converter 1 via a voltage divider 6, which includes two resistors. An error amplifier 7 is provided which has its first and second inputs connected to the voltage divider 6 and a reference voltage source V_ref, respectively. A comparator 8 has its first input connected to the output of the error amplifier 7; its second input is connected to a ramp generator 9, which is compensated by means of a signal proportional to the current I_Drosselthrough the inductor 3, and the output of the comparator 8 is coupled to the gate of the switching transistor 2. The compensated ramp generator 9 is designed to generate an output voltage having a sawtooth waveform with a concave rise. This voltage waveform is obtained by superimposing the ramp voltage from the ramp generator 9 on the signal proportional to the current through the inductor 3.

[0024] The output of the comparator 8 is connected through a flip-flop 20 to the gate of the switching transistor 2. The flip-flop 20 is controlled with a signal of frequency f_clockfrom a clock. It is an R-S (reset-set) flip-flop with a reset input R, a set input S, and an active output Q, which is connected to the gate of the switching transistor 2. The frequency f_clockof the signal from the clock is adapted to the frequency of the signal from the ramp generator 9. The output signal of the comparator 8 determines the frequency for switching the switching transistor 2.

[0025] Through the feedback provided around the pulse-width-modulated DC-DC converter, the duty cycle of the switching transistor is adjusted, whereby the output voltage V_outis regulated. At an excessive output voltage V_out, the output voltage V_errorof the error amplifier is reduced. This reduces the on time T_Eof the switching transistor and, thus, the output voltage V_outof the DC-DC converter.

[0026] FIG. 2 illustrates the basic operation of the compensated ramp generator 9. A capacitor 10 receives the sum of the correction current I_corrand the constant reference current I_refis fed. Connected in parallel with the capacitor 10 is a switching element 11 by which the capacitor 10 can be discharged at the frequency of the signal applied to the gate of the switching transistor 2.

[0027] FIG. 3ais a plot of inductor current I_Drossel, to which the correction current I_corris proportional, as a function of time. The characteristic for a low inductor current is designated 1, and that for a high inductor current is designated 2. FIG. 3bshows the output voltage of the ramp generator V_Rampfor the two current characteristics 1 and 2 of FIG. 3a. The voltage waveform is parabolic, so that the zero of the output voltage of the ramp generator V_Rampremains unchanged. Also shown is the output voltage V_Errorof the error amplifier as a function of time. With the comparator 8, the respective intersection of V_Errorand V_Rampis determined. By these intersections, the clock frequency at which the switching transistor 2 is controlled is determined. A higher inductor current results in a shorter on time T_E. Compared with a noncompensated ramp generator, whose output voltage V_Rampis linear, the ramp generator compensated in accordance with the invention has a shorter on time T_Efor all inductor currents, i.e., also for lower inductor currents. As can be seen in FIG. 3b, the slew rate of the output voltage of the compensated ramp generator 9 increases with increasing inductor currents (2). The inductor current increases both with increasing output current and at a constant output current with decreasing input voltage. Consequently, the loop gain of the feedback DC-DC converter 1 is reduced only at large inductor currents and low input voltages. Thus, the frequency response of the overall system can be held constant over a very wide range despite changes in input voltage and load current. In this manner, a smaller loop gain at high input voltages, and thus a loss of accuracy of the DC-DC converter, is avoided.

[0028] FIG. 4 illustrates one embodiment of the compensated ramp generator 9. The correction current I_corris generated in a first node K1 of constant potential. To this end, a first amplifier 12 is provided, whose input is connected to a voltage V_Dproportional to the inductor current I_Drossel. The output of the first amplifier 12 is connected through a resistor 13 to the first node K1. The first amplifier 12 is a feedback operational amplifier and may have a gain factor of one. Also provided are a first reference current source 14 in series with a first transistor 15 connected in common-source configuration, which form an output stage of the amplifier 12. Coupled to the node K1 is the output of a second operational amplifier 17. One input of the second operational amplifier 17 is connected to a second reference voltage source V_ref1, and the other input is connected to the node K1. The output stage of the second operational amplifier 17 is formed by the series combination of the second transistor 18 and a second reference current source 16. At the node K1, the sum of the correction current I_corrand the constant reference current I_refis formed.

[0029] A third transistor 19, the first operational amplifier 12, and the output stage of the latter, which includes the first reference current source 14 and the first transistor 15, form a current mirror. The gate of the third transistor 19 is connected to the gate of the first transistor 15, and the drain of the third transistor 19 is connected to the capacitor 10. The first transistor 15 and the second transistor 18 have a fixed relationship to each other in terms of their electrical characteristics. Currents having a fixed relationship to each other are generated with the first and second reference current sources 14, 16. The first transistor 15 and the second transistor 18 may have the same electrical characteristics, and the first and second reference current sources 14, 16 may generate equal currents. In that case, particularly good matching of the overall system is achieved. Errors due to mismatches are avoided. The overall circuit can be implemented using monolithic integrated technology. The signal proportional to the inductor current I_Drosselcan be determined from the voltage drop across the switching transistor 2.

[0030] FIG. 5 illustrates another embodiment of the compensated ramp generator, where elements corresponding to those of FIG. 4 are designated by like reference characters. Unlike the embodiment of FIG. 4, the gate of the third transistor 18 is connected to the gate of the second transistor 18. The drain of the third transistor 19 is connected to the capacitor 10 through a second current mirror 21. This embodiment uses n-channel MOS transistors, whereas the embodiment shown in FIG. 4 uses p-channel MOS transistors. The second current mirror 21 causes a reversal of the potential conditions. Accordingly, in the embodiment of FIG. 5, the connections of the circuit elements to the reference voltage V_refand the input voltage V_Dare interchanged as compared to the embodiment of FIG. 4, so that, taking into account the second current mirror 21, the circuits in the two embodiments have the same control direction.

[0031] Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.