Column transistor for semiconductor devices

[0002] 1. Field of the Invention

[0003] The present invention relates to an improved column transistor configuration for use in semiconductor devices and, more particularly, to a column transistor in a semiconductor memory device, which transmits data on a bit line to a local data line or vice versa, having an improved and more efficient layout that allows increased device packing density.

[0004] 2. Background of the Related Art

[0005] In semiconductor memory devices, the layout area of the sense amplifier usually depends on the size of a memory cell. For this reason, as the packing density of the memory device increases, the size of each memory cell is also decreased. This reduction in memory cell size requires that the size of the sense amplifier, which senses and amplifies the data from the memory cell, must be reduced in proportion to the size reduction of the memory cell. This reduction in the size of the sense amplifier lowers the driving performance of the sense amplifier as well. It is very important, however, to increase or at least maintain the operating frequency of the memory device to correspond to the increased operating frequencies obtained by advanced microprocessors.

[0006] The present invention provides a method for enhancing the driving performance of the sense amplifier as one of method for increasing the operating frequency of the memory device. The present invention also provides a method for providing a more efficient and effective layout for column transistors that are located between the bit lines and the local data lines to maximize the area of the sense amplifiers located between the bit lines.

[0007] FIG. 1 illustrates a circuit diagram of for conventional prior art column transistors, showing an example of the column transistors each with a width of 2.28 μm. A plurality of paired bit lines Biti, BitBi, Bitj, and BitBj are arranged in one direction, and a plurality of local data (bus) lines LDBi, LDBBi, LDBj, and LDBBj that are arranged in a generally perpendicular relation to the bit lines and connected to the column transistors (CT1˜CT8). As shown, the data on the bit line Biti is transferred to the local data line LDBj through nodes N1 and N2 by the column transistors CT1 and CT5, the data on the bit line Bitj is transferred to local data line LDBBj through nodes N3 and N4 by the column transistors CT2 and CT6. Similarly the data on the bit line BitBi is transferred to the local data line LDBBi through nodes N5 and N6 by the column transistors CT3 and CT7, and the data on the bit line BitBj is transferred to local data line LDBj through nodes N7 and N8 by the column transistors CT4 and CT8. That is, there are data transmission paths of Biti→CT1→LDBi, Bitj→CT2→LDBBj, BitBi→CT3→LDBBi, and BitBj→CT4→LDBj.

[0008] The physical layout of such column transistors will be discussed with reference to FIGS. 2 and 3. Rectangular shaped active regions 10 are arranged on a semiconductor substrate in a regular check pattern with groups of four adjacent active regions 10 constituting one set of active regions. Each active region 10 is crossed twice by a gate electrode 12, to produce an effective gate width of approximately twice the width of the active region (1.14 μm) for a total width of 2.28 μm. A single gate electrode 12 structure overlaps a set of active regions 10 to form a set of four column transistors, for example CT1˜CT4. Bit lines 14, Biti, Bitj, BitBi, and BitBj, are arranged sequentially in one direction across a set of active regions, with each bit line contacting a separate one of the adjacent active regions 10 via a pair of contacts BC. Local data lines 16, LDBi, LDBBj, LDBBi, LDBj, are arranged in a direction perpendicular to the bit lines 14 and overlapping two of the adjacent active regions 10. Each of the local data lines 16 is in contact with a separate one of the set of active regions 10, and consequently a separate one of the column transistors CT1˜CT4, via a local data line contact LDBC. The gate electrodes 12 for the column transistors CT1˜CT4 are connected by metal lines via metal contacts MC. This basic structure is then repeated for each set of active regions across the semiconductor device.

[0009] Because the prior art methods for forming the column transistor can not effectively reduce the area of the column transistors connected to the sense amplifiers, the prior art methods are generally unsuitable for improving the efficiency of the sense amplifier layout within a given area. In light of these deficiencies, previous attempts to produce devices having both extremely high packing densities and enhanced operating performance have failed.

[0010] Accordingly, the present invention is directed toward a column transistor arrangement in a semiconductor device that substantially reduces or eliminates one or more of the limitations and disadvantages of the prior art arrangements.

[0011] The claimed inventions provide column transistors for semiconductor devices that include a sense amplifier connected to a local data line and a bit line having shared active regions. More specifically, each of the active areas constitutes either a source or a drain region for a pair of adjacent column transistors that are separate sets of column transistors.

[0012] The configuration of the gate electrode structures is modified to remain more substantially within the column transistor, thereby increasing the effective width of the resulting transistor. With the gate electrodes bent to form a ¤ character form, all the gate electrodes of corresponding column transistors are connected to a single sense amplifier, the gate electrode for each set of column transistors contacts metal wiring at only one point, and each active region is in contact with two bit lines and one local data line. In another aspect of the present invention, a semiconductor device can be fabricated in which the column transistors are arranged in an orthogonal matrix comprising a plurality of sets of four square active regions, a gate electrode having a bent portion overlapped with the set and being connected to a sense amplifier along with a plurality of other column transistors. Further the column transistors according to the present invention are arranged with four bit lines running over each one of the active regions, with only two the bit lines making contact with any single active region, and four local data lines running in a direction perpendicular to the bit lines, with only two of the data lines running over any single active region, only one of which will be in contact with a specific active region.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

[0014] The accompanying figures are included to provide a further understanding of the present invention and illustrate specific embodiments of the invention and supplement the description of the invention.

[0015] FIG. 1 is a circuit diagram illustrating related art sense amplifier column transistors;

[0016] FIG. 2 is a layout illustrating the circuit in FIG. 1;

[0017] FIG. 3A is a layout illustrating the active regions and the gate electrodes in FIG. 2;

[0018] FIG. 3B is a bit line layout in FIG. 2;

[0019] FIG. 3C is a local data busline layout in FIG. 2;

[0020] FIG. 4 is a circuit diagram illustrating a sense amplifier column transistor in accordance with a preferred embodiment of the present invention;

[0021] FIG. 5 is a layout illustrating the circuit in FIG. 4;

[0022] FIG. 6A is a layout illustrating the active regions and the gate electrodes in FIG. 5;

[0023] FIG. 6B is a bit line layout in FIG. 5; and,

[0024] FIG. 6C is a layout illustrating the local data busline in FIG. 5.

[0025] A detailed description of the present invention with appropriate references to the related Figures is provided below.

[0026] The circuit diagram corresponding to an arrangement of column transistors according to the present invention provided in FIG. 4 and is similar in many respects to the circuit diagram relating to the prior art provided in FIG. 1. The circuit diagram provided in FIG. 4 does, however, reflect a rearrangement in the a layout of local data lines to an order of LDBi, LDBBj, LDBBi, LDBj, a layout that is a characteristic of the present invention.

[0027] FIG. 5 illustrates a possible layout of the circuit in FIG. 4. FIG. 6A illustrates the layout of the active regions and the gate electrodes corresponding to FIG. 5. Similarly, FIG. 6B illustrates the bit line layout, and FIG. 6C illustrates the layout of the local data lines, as illustrated in FIG. 5.

[0028] Four adjacent column transistors constitute one set to share active regions 20, and the active regions 20 of adjacent two sets of column transistors CT1˜CT4 and CT5˜CT8 are formed to share source/drain regions with adjacent sense amplifier column transistors. Each gate electrode 22, having a shape such as an “∩”, “∪”, or “”, is arranged over portions of four adjacent active regions 20, to provide the gate electrode for four separate column transistors such as CT1˜CT4. Bit lines 24, Bitj, BitBj, BitBi, and Biti, are arranged in one direction above the active regions 20 overlapping therewith, and local data lines 26 are arranged in the sequential order LDBi, LDBBj, LDBBi, and LDBj and in a direction perpendicular to the bit lines 24. A metal wire 28 is formed over a portion of the device between adjacent active regions 20 in a direction parallel to the bit lines 24.

[0029] The bit lines 24 are each connected to one active region 20 through two bit line contacts BC, and the local data line 26 is connected to one active region 20 through one local data line contact LDC, with gate electrode for each set of four column transistors being connected to the metal wiring 28 through a metal wiring contact MC. The basic structure of the present invention is four adjacent active regions that are repeatedly arranged in a check pattern, with each active region connected to two bit lines from adjacent sets of column transistors and one local data line, the data line contact being made inside the “∩” shape of gate electrode 22. Thus, two column transistors share either one source or drain region.

[0030] According to the foregoing layout, a gate electrode the would provide a width of 1.14 μm (crossing twice to reach 2.28 μm) in the prior art configuration can produce an effective gate width of approximately 3.35 μm. Without changing the basic design rules, therefore, the present invention can increase the width of the column transistors by approximately 47%, while simultaneously reducing the necessary cell area by eliminating contacts used in the prior art configuration.

[0031] As described above, the sense amplifier column transistors according to the present invention provide the same basic orthogonal matrix of sets of active regions, bit lines and local data lines running perpendicular to each other, but with each active region being connected to two bit lines and one local data line, and a gate electrode having a bent portion that increases the effective width of the transistor. By increasing the effective width of the transistor, while simultaneously reducing the number of contacts required, the present invention allows the sets of column transistors to be fabricated in a smaller area, thereby increasing the area available for the sense amplifier. Further, by forming the transistors according to the present invention, improvements in design tolerance as well as a fabrication tolerances relating to the formation of the contacts can be realized, results that are favorable for high density device packing and enhancing a device operation performance and lifetime.

[0032] It will be apparent to those skilled in the art that various modifications and variations can be made to the method of forming column transistors according to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention not be limited to the specific disclosure provided but instead cover any insubstantial modifications and variations to the method defined by the following claims.