Multi-chip package-type semiconductor device

[0002] This application claims the priority benefit of Japanese Patent Application No. 2000-314988, filed Oct. 16, 2000, the entire disclosure of which is incorporated herein by reference.

[0003] 1. Field of the Invention

[0004] This invention relates to a semiconductor device, and more particularly, to a multi-chip package-type semiconductor device in which more than one IC chip can be packaged.

[0005] 2. Description of the Related Art

[0006] In the related art, there are several types of multi-chip packages in which more than one IC chip can be packaged. One typical multi-chip package is a stack-type multi-chip package that packages at least two IC chips in a stacked manner.

[0007] In the stack-type multi-chip package, the semiconductor device includes an insulating substrate on which conductive patterns are formed, a first semiconductor chip, and a second semiconductor chip mounted on the first semiconductor chip. Each of the semiconductor chips includes terminal pads in a peripheral area on its main surface. An adhesive material is formed on the main surface of the first semiconductor chip except for the terminal pad in order to fix the second semiconductor chip on the first semiconductor chip. More concretely, a back surface of the second semiconductor chip is adhered to a center of the main surface of the first semiconductor chip.

[0008] In such a device, after the second semiconductor chip is mounted on the first semiconductor chip, each terminal pad of each of the first and second semiconductor chips is connected to one of the conductive patterns formed on the insulating substrate by a bonding wire so that each semiconductor chip is connected electrically to the insulating substrate. Further, the semiconductor chips and bonding wires are encapsulated by a sealing material, such as a resin.

[0009] Therefore, in such a multi-chip package-type semiconductor device, since the second semiconductor chip is directly mounted on the first semiconductor device, the size of the second semiconductor chip should be smaller than that of the first semiconductor chip. That is, the second semiconductor is mounted in the center area of the main surface of the first semiconductor device so that the terminal pads of the first semiconductor device are exposed for connection to bonding wires. Further, the surface of the remainder of the peripheral area also is exposed. Therefore, the size of the second semiconductor chip should not only be smaller than that of the first semiconductor chip, but also be determined by the size of the peripheral area of the first semiconductor chip.

[0010] As a result, according to the above described multi-chip package-type semiconductor device, it is almost impossible to stack first and second semiconductor chips having the same size because the first semiconductor chip should have an exposed peripheral area that is not covered by the second semiconductor chips.

[0011] To overcome this limitation, some others have been introduced. One typical example is disclosed in Japanese Patent Publication 60-245291. A multi-chip package-type semiconductor device disclosed in that publication includes an insulating substrate having an opening and first and second semiconductor chips stacked with their back surfaces. The first and second semiconductor chips are placed in the opening. In this type of the multi-chip package-type semiconductor device, since the first and second semiconductor chips are connected to each other at their back surfaces, they may be of the same size. However, according to that reference, an adhesive tape are formed on the main surface of one of the semiconductor chips on which a circuit is formed, and then, the adhesive tape is removed for the following steps. Therefore, this step of removing the adhesive tape formed on the circuit may cause damage to the circuit.

[0012] It is therefore an object of the invention to resolve the above-described problems in a multi-chip package-type semiconductor device and provide a multi-chip package-type semiconductor device having two stacked, same size semiconductor chips.

[0013] The object is achieved by a multi-chip package-type semiconductor device including a first insulating substrate, a second insulating substrate, a first semiconductor chip, a second semiconductor chip of approximately the same size as the first semiconductor chip and bonding wires.

[0014] The first insulating substrate includes a first surface and the second surface opposite to the first surface wherein the first insulating substrate has a recess at the first surface. The second insulating substrate includes a first surface and the second surface opposite to the first surface wherein the second insulating substrate further has on the first surface an opening that is larger than the recess, and conductive patterns. Further the second insulating substrate is on the first substrate wherein the opening encompasses the recess. The first semiconductor chip formed in the recess includes a first surface and the second surface opposite to the first surface wherein the first semiconductor chip includes on the first surface a first terminal pad and a first circuit, which is connected to the first terminal pad. The second semiconductor chip includes a first surface and a second surface opposite to the first surface wherein the second semiconductor chip further has on the first surface a second terminal pad and a second circuit, which is connected to the second terminal pad. Further, the second semiconductor chip is supported by the first insulating substrate in an area of the first surface, which is exposed by the opening. The bonding wires connect the first terminal pad to one of the conductive patterns, and for connecting the second terminal pad to another one of the conductive patterns.

[0015] The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and accompanying drawings.

[0016] FIG. 1A is a plan view of a multi-chip package-type semiconductor device according to a first embodiment of the invention;

[0017] FIG. 1B is a sectional view of the multi-chip package-type semiconductor device of FIG. 1;

[0018] FIG. 1C is a sectional view of the multi-chip package-type semiconductor device according to an alternative of the first embodiment of the invention;

[0019] FIG. 2 is a sectional view of a multi-chip package-type semiconductor device according to a second embodiment of the invention;

[0020] FIG. 3A is a plan view of a supporting member, which is used in the process of forming the multi-chip package-type semiconductor device according to the second embodiment;

[0021] FIG. 3B is a cross-sectional view taken on line I—I of FIG. 3A;

[0022] FIGS. 4A-4E are sectional views showing successive stages of the manufacture of the multi-chip package-type semiconductor device according to the second embodiment;

[0023] FIG. 5 is a sectional view of a multi-chip package-type semiconductor device according to a third embodiment of the invention;

[0024] FIGS. 6A-6E are sectional views showing successive stages of the manufacture of the multi-chip package-type semiconductor device according to the third embodiment; and

[0025] FIG. 6F is a sectional view of a multi-chip package-type semiconductor device according to an alternative of the third embodiment.

[0026] Referring to FIGS. 1A and 1B, a multi-chip package-type semiconductor device 100 includes a multi-stacked substrate 2 having a first insulating substrate 1aand a second insulating substrate 1bformed on the first insulating substrate 1a, a first semiconductor chip 6aand a second semiconductor chip 6b. The multi-stacked substrate 2 is formed of a glass epoxy resin. The first insulating substrate la includes a main surface and a back surface. First conductive patterns 3aare formed on the main surface, and back surface conductive patterns 13 are formed on the back surface. The second insulating substrate 1bincludes a main surface and a back surface, and second conductive patterns 3bare formed on the main surface. The first and second semiconductors are formed on the multi-stacked substrate 2. The first semiconductor chip 6aincludes first terminal pads 8ain a peripheral area of the main surface, which are arranged in a line along one of the sides of the first semiconductor chip 6a, and includes second terminal pads 8bin the same area on the same surface, which are arranged in a line along the same side. The first terminal pad 8ais located closer to the side than the second terminal pad 8b. The first semiconductor chip 6aalso includes a first circuit 21aon the main surface. Similarly, the second semiconductor chip 6bincludes first terminal pads 9ain its peripheral area on the main surface, which are arranged in a line along one of the sides of the second semiconductor chip 6b, and includes second terminal pads 9bin the same area on the same surface, which are arranged in a line along the same side. The first terminal pad 9ais located closer to the side than the second terminal pad 9b. The first and second terminal pads 8a, 8bof the first semiconductor chip 6aare opposite to the first and second terminal pads 9a, 9bof the second semiconductor chip 6b. The second semiconductor 6balso includes a second circuit 21bon the main surface.

[0027] The first and second semiconductor chips 6a, 6bmay be or may not be of the same kind. However, the size of the first semiconductor chip 6ais almost the same as that of the first semiconductor chip 6b. Therefore, if the first and second semiconductor 6a, 6bare of the same size, then, in accordance with the first embodiment of the invention, the first semiconductor chip 6acan be a memory and the second semiconductor chip 6bcan be a logic circuit.

[0028] The first insulating substrate 1aincludes a recess 11 in the main surface that is larger than the first semiconductor chip 6a. The first semiconductor chip 6ais fixed in the recess 11 by an insulative adhesive material 7asuch as an epoxy resin or an epoxy tape, wherein the back surface of the first semiconductor chip 6ais facing the bottom of the recess 11. The second insulating substrate 1bincludes an opening 12 is larger than the second semiconductor chip 6band than the recess 11. As described above, although the second insulating substrate 1bis placed on the first insulating substrate 1a, the peripheral area of the first insulating substrate 1ain which the first terminal pads 8aare formed, is not covered by the second insulating substrate 1bbecause the opening 12 formed in the second insulating substrate 1bis larger than the recess 11 formed in the first insulating substrate 1a. The second semiconductor chip 6bis placed in the opening 12 and fixed on the first insulating substrate 1aby an insulative adhesive material 7bsuch as an epoxy resin or an epoxy tape wherein the back surface of the second semiconductor chip 6bis facing the main surface of the first insulating substrate 1a. Since the second semiconductor chip 6bis supported by the first insulating substrate 1aonly in an area on the main surface which is exposed by the opening 12, there is a space between the first and second semiconductor chip 6a, 6b.

[0029] The first terminal pads 8aof the first semiconductors chip 6aare connected to the first conductive pattern 3aof the first insulating substrate 1aby bonding wires 4a, and the second terminal pads 8bof the first semiconductor chip 1aare connected to the second conductive pattern 3bof the second insulating substrate 1bby bonding wires 4b. The first terminal pads 9aof the second semiconductors chip 6bare connected to the first conductive pattern 3aof the first insulating substrate 1aby bonding wires 5a, and the second terminal pads 9bof the second semiconductor chip 6bare connected to the second conductive pattern 3bof the second insulating substrate 1bby bonding wires 5b. The first and second semiconductor chips 6a, 6band the bonding wires 4a, 4b, 5a, 5bare encapsulated completely by a sealing material 10 such as an epoxy resin. The location of the top surface of the sealing material 10 is higher than the top location of a loop of the bonding wire 4aor 5bby 50 μm. Since the sealing material 10 is extended into the space between the first and second semiconductor chip 6a, 6b, the second semiconductor chip 6bis finally supported by the sealing material 10 and the first insulating substrate 1a.

[0030] According to the multi-chip package-type semiconductor device 100 of the first embodiment, the multi-stacked substrate 2 having a step formed by the first and second insulating substrate 1a, 1b, is used, the second semiconductor chip 6bcan be placed in a location that is shifted from a location at which the first semiconductor chip 6ais placed. Therefore, the first and the second semiconductor chips used in the multi-chip package-type semiconductor device 100 may be of the same size.

[0031] Further, the second semiconductor chip 6bis not located above the peripheral area of the first semiconductor chip 6ain which the first and second terminal pads 8aand 8bare formed. Further, the first and second terminal pads 8aand 8bof the first semiconductor chip 1a, the first and second terminal pads 9aand 9bof the second semiconductor chip 1b, the first conductive patterns 3aof the first insulating substrate 1aand the second conductive pattern 3bof the second insulating substrate 1bcan be located on the same side if the first and second semiconductor chip 6a, 6bare of the same size. Therefore, each terminal pad 8a, 8b, 9a, 9bcan be connected to one of conductive patterns 3a, 3bin a single wire bonding process.

[0032] Moreover, the first and second terminal pads 8a, 8bof the first semiconductor chip 6ais quite opposite to the first and second terminal pads 9a, 9bof the second semiconductor chip 6b. According to this arrangement, it is possible to avoid unnecessary contact between the bonding wires 4a, 4bthat connect the first semiconductor chip 6ato the multi-stacked substrate 2 and the bonding wires 5a, 5bthat connect the second semiconductor chip 6band the multi-stacked substrate 2.

[0033] When the multi-chip package-type semiconductor device 100 of the first embodiment is connected to an external device, a bump electrode acting as a terminal pad for the external device may be formed on the conductive patterns 3a, 3b.

[0034] Further, since the second semiconductor chip 6bis supported by the first insulating substrate 1bbefore an encapsulating process is performed by using the sealing material 10, the main surface of the first semiconductor chip 6adoes not contact the back surface of the second semiconductor chip 6b. As described above, the first circuit 21ais formed on the main surface of the first semiconductor chip 6a. Since the main surface of the first semiconductor chip 6adoes not contact the back surface of the second semiconductor chip 6b, the first circuit 21ais not damaged.

[0035] In the multi-chip package-type semiconductor device 100 of the first embodiment, although the first conductive patterns 3aand the back surface conductive patterns 13 are formed on the first insulating substrate 1b, the first conductive patterns 3acan be formed on the main surface of the second insulating substrate 1band conductive patterns corresponding to the back surface conductive patterns 13 also can be formed on the main surface of the second insulating substrate 1b. In this case, the first and second insulating substrate 1a, 1bcan be formed as a single integral structure 2aas shown in FIG. 1C. Further, the first and second conductive patterns 3a, 3bcan be connected to each other by an internal conductive pattern, which is formed in the second insulating substrate 1b.

[0036] In the multi-chip package-type semiconductor device 100 of the first embodiment, the second semiconductor chip 6bis fixed on the first insulating substrate 1bby the adhesive material 7abefore the encapsulating process is performed by using the sealing material 10. In such a structure, it is better to avoid flowing the adhesive material onto the main surface of the first semiconductor chip 6abecause the first circuit 21ais formed thereon. Therefore, the adhesive material is preferably of high viscosity or is an the epoxy tape.

[0037] However, when high tackiness cannot be obtained by the adhesive material having high viscosity or the epoxy tape, in order to support the second semiconductor chip 6b, an extra adhesive material may be formed on the main surface of the first semiconductor chip 6ato support the second semiconductor chip 6bby the first semiconductor chip 6a. The extra adhesive material may be formed on the entire area except for the periphery in which the first bonding pads 8aare formed, or be formed on a particular area on the main surface of the first semiconductor chip 6acorresponding to the edge of the second semiconductor chip 6b. In this case, since the adhesive material is formed on the first circuit 21aof the first semiconductor chip 6adirectly, it is necessary not to make damage to the circuit of the first semiconductor chip 6awhen the extra adhesive material is formed.

[0038] FIG. 2 shows a multi-chip package-type semiconductor device 200 according to a second embodiment, In the second embodiment, the same reference numbers in FIGS. 1A and 1B designate the same or similar components in FIG. 2.

[0039] Referring to FIG. 2, the multi-chip package-type semiconductor device 200 includes an insulating substrate 22 having an opening 29, a first semiconductor chip 6aand a second semiconductor chip 6b. The insulating substrate 22 is formed of a glass epoxy resin. The first semiconductor chip 6ahas a main surface 80aand a back surface 80b, and first circuits 21aand first terminal pads 18 having first bump electrodes 15, which is connected to the first circuits 21a, are formed on the main surface 80a. The second semiconductor chip 6bhas a main surface 81aand a back surface 81b, and second circuits 21band second terminal pads 19, which are connected to the second circuits 21b, are formed on the main surface 81a. The first and second semiconductor chips 6a, 6bhave approximately the same size, and they are fixed to each other at their back surfaces 80b, 81bby an adhesive material 7 such as an epoxy resin having an insulating characteristic. The opening 29 is formed larger than the first and second semiconductor 6a, 6bso that the first and second semiconductor chips can be placed in the opening 29 of the insulating substrate 22.

[0040] The insulating substrate 22 having a main surface 22aand back surface 22bincludes a conductive pattern 23 formed on the main surface 22aand third terminal pads 27 having second bump electrodes 16 on the back surface 22b. The insulating substrate 22 further includes through-holes 25aand internal conductive patterns 25bformed in the through-holes 25a. Therefore, the conductive pattern 23 is connected to the third terminal 27 by the internal conductive patterns 25b.

[0041] Each second terminal pad 19 of the second semiconductor chip 6bis connected to one of the conductive patterns 23 by the bonding wire 24. The second semiconductor chip 6band the bonding wire 24 are encapsulated completely by a sealing material 10. The second semiconductor chip 6bis fixed to the insulating substrate 22 by the sealing material 10, which is extended into a space formed between a side surface of the second semiconductor chip 6band a side surface of the insulating substrate 22. Further, an unillustrated passivation layer, such as an epoxy resin, is formed on the entire main surface 80aof the first semiconductor device 6aexcept for on the first terminal pad in order to protect the circuits 21aformed on the main surface 80aof the first semiconductor device 6a.

[0042] The multi-chip package-type semiconductor device 200 is mounted on and connected to an external device 30 such as a motherboard having a circuit pattern 32 by the well-known face-down bonding. By contacting the first bump electrodes 15 on terminal pad 18 and the second bump electrodes 16 on the third terminal pad 27 to the circuit pattern 32 on the external device 30, the electrical connection between the multi-chip package-type semiconductor device 200 and the external device 30 is made. To make a fine connection between the multi-chip package-type semiconductor device 200 and the external device 30, it is essential to form the tops of the first and second bump electrodes 15, 16 to be located in the same horizontal plane. Since the first semiconductor chip 6ais projected from the insulating substrate 22, the size of each first bump electrode 15 should be smaller than that of the second bump electrode 16 in order to adjust the tops of the first and second bump electrodes 15, 16 in the same horizontal plane.

[0043] In the second embodiment, although the third terminal pads 27 are formed on the back surface 22bof the insulating substrate 22, some conductive patterns can be formed on the back surface 22bof the insulating substrate 22 as well as on the main surface 22a. In this case, by forming some extra terminal pads and some extra bump electrodes on the conductive patterns, it is possible to connect the conductive patterns to the external device via the extra terminal pads and the extra bump electrodes.

[0044] According to the second embodiment, since the first and the second semiconductor chips 6a, 6b, which are stacked at their back surfaces 80b, 81b, are placed in the opening 29 of the insulating substrate 22, the second semiconductor chip 6bis not mounted on the first circuits 21aformed on the first semiconductor chip 6a. Therefore, the shape of the second semiconductor chip 6bis not restricted by the first terminal pads 18 of the first semiconductor chip 6a. As a result, the first and the second semiconductor chips 6a, 6bhaving the same size can be stacked to each other. Further, since the first and the second semiconductor chips 6a, 6b, which are stacked to each other at their back surfaces 80b, 81b, are placed in the opening 29 of the insulating substrate 22, the first circuits 21aformed on the main surface 80aof the first semiconductor chip 6aare not damaged.

[0045] Further, comparing the first embodiment, since the first and the second semiconductor chips 6a, 6b, having the same size is placed in the single opening 29, the multi-chip package-type semiconductor device 200 having a thin structure can be presented.

[0046] In addition, since the tops of the first and the second bump electrodes 15,16, which are connected to the first and second circuit 21a, 21b, are located in the same horizontal plane, it is easy to connect the multi-chip package-type semiconductor device 200 to the external device 30 by the face-down bonding method.

[0047] The multi-chip package-type semiconductor device 200 is formed in the processes shown in FIGS. 4A-4E using a supporting member 55 shown in FIGS. 3A and 3B. First, the supporting member 55 is explained.

[0048] Referring to FIG. 3A and FIG. 3B, the supporting member 55 includes an adhesive tape 57 and a stand 56. On the top surface of the stand 56, an adhesive material 58, such as an UV tape is formed. The stand 56 is formed of a thermosetting resin. Further, the adhesive tape 57 may be formed of a UV tape. Alternatively, the stand 56 itself may be formed of a thick UV tape.

[0049] The width of the stand 56 is smaller than that of the opening 29 of an insulating substrate 22 shown in FIG. 2. Although the height (h) of the stand 56 should be lower than the thickness of the insulating substrate 22, the height (h) of the stand 56 is changed in response to a thickness of a first semiconductor chip 6a. The area of the top surface of the stand 56 is determined by the area of the back surface 81bof the second semiconductor chip 6b. That is, although the area of the top surface of the stand 56 should be smaller than that of the opening 29 because the stand 56 is inserted into the opening 29, the area of the top surface of the stand 56 should be larger than or approximately the same as the area of the back surface 81bof the second semiconductor chip 6bto avoid forming the sealing material layer on the back surface 81bof the second semiconductor chip 6b. In other words, the area of the top surface of the stand 56, which is approximately the same as the area of the opening 29 can avoid allowing the sealing material to extend to the back surface 81bof the second semiconductor chip 6b.

[0050] As described above, although the adhesive tape 57 and the adhesive material 58 are formed of the UV tape, they may be formed of a thermal volatile tape. Adhesion of these tapes is decreased by ultraviolet irradiation or heating. Therefore, the adhesive tape 57 and the adhesive material 58 are removed easily from the insulating substrate 22 and the second semiconductor chip 6bby ultraviolet irradiation or heating, and the second semiconductor chip 6bis not damaged.

[0051] The multi-chip package-type semiconductor device 200 is formed by using the supporting member 55 described above, and is explained with reference to FIGS. 4A-4E below.

[0052] As shown in FIG. 4A, the insulating substrate 22 having the main surface 22aand back surface 22bis prepared. The insulating substrate 22 includes the conductive layers 23 on the main surface 22aof the insulating substrate 22 and the internal conductive patterns 25bformed in the through holes 25a. As described above, the insulating substrate 22 further includes the opening 29 whose size is larger than that of the first and second semiconductor chips 6a, 6b; which will be placed therein later. The supporting member 55 is adhered to the back surface 22bof the insulating substrate 22 by the adhesive tape 57 wherein the stand 56 is inserted into the opening 29 from a first side at which the back surface 22bof the insulating substrate 22 is located. As described above, the width of the stand 56 is smaller than or almost the same as that of the opening 29, it is possible to insert the stand 56 in the opening 29.

[0053] Next, as shown in FIG. 4B, the second semiconductor chip 6bis placed in the opening 29 from the second side, which is opposite to the first side, and then, is fixed on the stand 56 by the adhesive material 58. In this step, since the second terminal pads 19 and a second circuit 21bare formed on the main surface 81aof the second semiconductor chip 6b, the back surface 81bof the second semiconductor chip 6bis adhered to the stand 56. Then, each second terminal pad 19 is connected to one of the conductive patterns 23 by a bonding wire 24. Then, the second semiconductor chip 6band the bonding wires 24 are encapsulated by a sealing material 10. The second semiconductor chip 6bis fixed to the insulating substrate 22 by the sealing material 10, which extended into a space between the side surface of the second semiconductor chip 6band the side surface of the insulating substrate 22. Since the area of the top surface of the stand 56 is larger than or approximately the same as the area of the back surface 81bof the second semiconductor chip 6b, the sealing material 10 cannot reach the back surface 81bof the second semiconductor chip 6bpassing through the space.

[0054] Then, as shown in FIG. 4C, the supporting member 55 is detached from the insulating substrate 22 and the second semiconductor chip 6bby the UV irradiation. According to the characteristic of the UV tape, any adhesive material does not remain on the back surface 22bof the insulating substrate 22 and on the back surface 81bof the second semiconductor chip 6b.

[0055] Referring to FIG. 4D, the insulating substrate 22 is tuned over. Then, the insulative adhesive material 7 is formed on the back surface 81bof the second semiconductor chip 6b. Then, the first semiconductor chip 6ahaving the first terminal pads 18 is prepared. The first semiconductor chip 6aof approximately the same size as the second semiconductor chip 6bis placed in the opening 29 from the first side, and then, is fixed on the back surface 81 b of the second semiconductor chip 6bby the adhesive material 7. Since the first terminal pads 18 and the first circuit 21aare already formed on the main surface 80aof the first semiconductor chip 6a, the back surface 80bof the first semiconductor chip 6ais adhered to the back surface 81bof the second semiconductor chip 6b. That is, the first and second semiconductor chips 6a, 6bhaving the same size are coupled to each other at their back surfaces 80b, 81bby the adhesive material 7, and are placed in the opening 29. Then, the third terminal pads 27, which are connected to the internal conductive patterns 25b, are formed on the back surface 22bof the insulating substrate 22. Then, the first bump electrodes 15 and the second bump electrodes 16 are formed on the first and third terminal pads 18, 27, respectively. Here, it is essential to form the tops of the first and second bump electrodes 15, 16 to be located in the same horizontal plane. Since the main surface 80aof the first semiconductor chip 6ais projected from the back surface 22b, it is necessary to formed the second bump electrode 16 larger than the first bump electrode 15 in order to locate the tops of the first and second bump electrodes 15, 16 in the same horizontal plane. However, since the size of the second bump electrode 16 may be limited because of its material characteristic, the location of the first semiconductor chip 6ais adjusted. The location of the first semiconductor chip 6ais determined by the location of the second semiconductor chip 6b, which is determined by the height of the stand 58 used in FIG. 4A. Therefore, by adjusting the height of the stand 58, the tops of the first and second bump electrodes 15, 16 can be located in the same horizontal plane.

[0056] Then, as shown in FIG. 4E, the insulating substrate 22 is tuned over again, and then, the multi-chip package-type semiconductor device 200 is connected to the external device 30 by connecting the first bump electrodes 15 and the second bump electrodes 16 to the circuit pattern 32 formed on the external device 30 by the well-know face-down bonding method.

[0057] According to the method of forming the multi-chip package-type semiconductor device 200 of second embodiment, when the first semiconductor chip 6ais projected from the insulating substrate 22, the tops of the first and second bump electrodes 15, 16 can be located in the same horizontal plane by changing the size of the first and second bump electrodes 15, 16. Accordingly, the fine connection between the multi-chip package-type semiconductor device 200 and the external device 30 can be made by the face down bonding.

[0058] Further, according to the method of forming the multi-chip package-type semiconductor device 200 of the second embodiment, the second semiconductor chip 6bis fixed to the insulating substrate 22 by the sealing material by using the support member 55 first, and then, the first semiconductor chip 6bis placed on the back surface 81bof the second semiconductor chip 6afrom the first side. Therefore, the main surfaces 80a, 81aon which the first and second circuits 21a, 21band the first and second terminal pads 18, 19 are formed, are not contacted to each other in the manufacturing process. As a result, both of the first and second circuits 21a, 21bformed on the main surfaces 80a, 81aof the first and second semiconductor chips 6a, 6bare not damaged.

[0059] FIGS. 5 and 6A-6E show a multi-chip package-type semiconductor device 300 according to a third embodiments and the successive stages of the manufacture of the multi-chip package-type semiconductor device 300, respectively. In the third embodiment, the same reference numbers in FIGS. 1A and 1B, FIG. 2, FIGS. 3A, and 3b, or FIGS. 4A-4E designate the same or similar components in FIGS. 5 and 6A-6E.

[0060] In view of the structure, as shown in FIG. 5, the differences between the second and third embodiments are that a first terminal pads 18 formed on a first semiconductor chip 6aare connected to a second conductive pattern 43 formed on a back surface 42bof a insulating substrate 42 by a second bonding wire 49, and that both of the first semiconductor chip 6aand the second bonding wire are encapsulated by a sealing material in the third embodiment. The multi-chip package-type semiconductor device 300 are formed by the process below.

[0061] In the process of manufacturing the multi-chip package-type semiconductor device 300, the support member 55 is also used. The material and other specification of the support member 55 used in this process are similar to those of the support member 55 used in the second embodiment.

[0062] Referring to the FIGS. 6A through 6E, a series of the processes of manufacturing the multi-chip package-type semiconductor device are illustrated. As shown in FIG. 6A, an insulating substrate 42 having a main surface 42aand a back surface 42cis prepared. The insulating substrate 42 includes first conductive layers 23 on the main surface 42aof the insulating substrate 42 and second conductive layers 43 on the back surface 42bof the insulating substrate 42. The insulating substrate 42 further includes an opening 29 is larger than a first and second semiconductor chips 6a, 6b. The supporting member 55 is adhered to the main surface 42aof the insulating substrate 42 by the adhesive tape 57 wherein the stand 56 is inserted in the opening 29 from a second side at which the main surface 42bof the insulating substrate 42 is located. As described in the second embodiment, the width of the stand 56 is smaller than or almost the same as that of the opening 29, it is possible to insert the stand 56 in the opening 29.

[0063] Next, as shown in FIG. 6B, the first semiconductor chip 6ais placed in the opening 29 form a first side, which is opposite to the second side, and then, is fixed on the stand 56 by the adhesive material 58. In this step, since a first terminal pads 18 and a first circuit 21aare formed on the main surface 80aof the first semiconductor chip 6a, the back surface 80bof the first semiconductor chip 6ais adhered to the stand 56. Then, each first terminal pad 18 is connected to one of the second conductive patterns 43 by a bonding wire 49. Then, the first semiconductor chip 6aand the bonding wires 49 are encapsulated by a sealing material 46. The first semiconductor chip 6ais fixed to the insulating substrate 42 by the sealing material 46, which is extended into a space between a side surface of the first semiconductor chip 6aand a side surface of the insulating substrate 42. As described in the second embodiment, since the area of the top surface of the stand 56 should be larger than or approximately the same as the area of the back surface 80bof the first semiconductor chip 6a, the sealing material 46 cannot reach the back surface 80bof the first semiconductor chip 6apassing through the space.

[0064] Then, as shown in FIG. 6C, the supporting member 55 is detached from the insulating substrate 42 and the first semiconductor chip 6aby the UV irradiation. According to the characteristic of the UV tape, any adhesive material does not remain on the main surface 42aof the insulating substrate 42 and on the back surface 80aof the first semiconductor chip 6a. In other words, the area of the top surface of the stand 56, which is approximately the same as the area of the opening 29 can avoid allowing the sealing material to extend to the back surface 81bof the second semiconductor chip 6b.

[0065] Referring to FIG. 6D, the insulating substrate 42 is tuned over. Then, an insulative adhesive material 7 is formed on the back surface 80bof the first semiconductor chip 6a. The second semiconductor chip 6bof approximately the same size as the first semiconductor chip 6ais placed in the opening 29 from the second side, and then, is fixed on the back surface 80bof the first semiconductor chip 6aby the adhesive material 7. Since a second terminal pads 19 and a second circuit are already formed on the main surface 81aof the second semiconductor chip 6b, the back surface 81bof the second semiconductor chip 6bis adhered to the back surface 80bof the first semiconductor chip 6a. That is, the first and second semiconductor chips 6a, 6bhaving the same size are coupled to each other at their back surfaces 80b, 81bby the adhesive material 7, and placed in the opening 29.

[0066] Then, as shown in FIG. 6E, each second terminal pad 19 is connected to one of the first conductive patterns 23 by a bonding wire 24. Then, the second semiconductor chip 6band the bonding wires 24 are encapsulated by sealing material 10. The second semiconductor chip 6bis fixed to the insulating substrate 42 by the sealing material 10, which enters into space between the second semiconductor chip 6band the insulating substrate 42.

[0067] According to the third embodiment, since the first and the second semiconductor chips 6a, 6b, which are stacked at their back surfaces 80b, 81b, are placed in the opening 29 of the insulating substrate 42, the second semiconductor chip 6ais not mounted on the first circuits 21aformed on the first semiconductor chip 6a. Therefore, the shape of the second semiconductor chip 6bis not restricted by the first terminal pads 18 of the first semiconductor chip 6a. As a result, the first and the second semiconductor chips 6a, 6bhaving the same size can be stacked to each other. Further, since the first and the second semiconductor chips 6a, 6b, which are stacked to each other at their back surfaces 80b, 81b, are placed in the opening 29 of the insulating substrate 22, the first circuits 21aformed on the main surface 80aof the first semiconductor chip 6aare not damaged.

[0068] Further, comparing the first embodiment, since the first and the second semiconductor chips 6a, 6b, having the same size is placed in the single opening 29, the multi-chip package-type semiconductor device 300 having a thin structure can be presented.

[0069] Moreover, since the insulating substrate 42 includes opening 29 but a recess, it is easy to make. Therefore, the cost for forming the insulating substrate 42 can be reduced.

[0070] Furthermore, according to the method of forming the multi-chip package-type semiconductor device of third embodiment, the supporting member 55 is used, and the first semiconductor chip 6ais fixed on the stand 56. Therefore, the first semiconductor chip 6acan be fixed at a desired position by changing the height of the stand 56. As described above, the first and second semiconductor chip 6a, 6bhaving not only the same size, but also the different thickness can be used. When the first and second semiconductor chip 6a, 6bhaving the different thickness are used, the location of the back surfaces 80b, 81bof the first and second semiconductor chip 6a, 6bmay not be in the middle of the opening 29 so that the distance from the main surface 42aof the insulating substrate 42 to the main surface 81aof the second semiconductor chip 6bcan be the same as that from the back surface 42bof the insulating substrate 42 to the main surface 80aof the first semiconductor chip 6b. In this case, the sealing material 10 having the uniform thickness from the center of the insulating substrate 42 can be formed. Accordingly, it is possible to avoid being the insulating substrate 42 warped.

[0071] Further, according to the method of forming the multi-chip package-type semiconductor device 300 of third embodiment, the first semiconductor chip 6ais fixed to the insulating substrate 42 by the sealing material by using the support member 55 first, and then, the second semiconductor chip 6bis placed on the back surface 80bof the first semiconductor chip 6a. Therefore, the main surfaces 80a, 81aon which the first and second circuits 21a, 21band the first and second terminal pads 18,19 are formed are not contacted to each other in the manufacturing process. As a result, both the first and second circuits 21a, 21bformed on the main surfaces 80a, 81aof the first and second semiconductor chips 6a, 6bare not damaged.

[0072] Moreover, the connection between the first terminal pads 18 and the second conductive pattern 43 are made by the bonding wires 49 in the side of the main surface 42aof the insulating substrate 42. On the other hand, the connection between the second terminal pads 19 and the first conductive pattern 23 are made by the bonding wires 24 in the side of the back surface 42aof the insulating substrate 42. Therefore, unnecessary contacts between the bonding wires 49, 24 can be avoided.

[0073] According to the third embodiment, the first conductive patterns 23 are formed on the main surface 42aof the insulating substrate 42. However, as shown in FIG. 6F, an extra conductive patterns 23a, which are used for connecting the external device, may be formed on the back surface 42bof the insulating substrate 42. In this case, internal conductive patterns 25bshould be formed in the insulating substrate 42, and the first conductive patterns 23 are connected to the extra conductive patterns 23aby the internal conductive patterns25b. According to this structure, since the extra conductive patterns 23aand the second conductive patterns 43 are formed on the single surface, the multi-chip package-type semiconductor device can be connected to an external device by a single wire bonding process.

[0074] While the present invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various other modifications of the illustrated embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. Therefore, the appended claims are intended to cover any such modifications or embodiments as fall within the true scope of the invention.