Method for plating a first layer on a substrate and a second layer on the first layer

[0002] The present invention relates to a substrate plating method and apparatus, and particularly to a substrate plating apparatus for filling pits for fine wires and the like formed in a semiconductor wafer with copper or another metal.

[0003] Conventionally, wire channels have been formed in a semiconductor wafer by first depositing a conducting layer on the wafer surface using sputtering or a similar technique. Next, the unnecessary portions of the conducting layer are removed through a chemical dry etching process with a pattern mask formed of resist or the like.

[0004] In conventional processes, aluminum (Al) or an aluminum alloy has been used to form the wire circuit. However, wiring has been made thinner to keep up with the increased complexity of semiconductor devices. The increasing current density generates increased thermal stress and higher temperatures. This causes stress-migration or electro-migration, which grow more remarkable as the layers of aluminum or the like are manufactured thinner and give rise to such disorders as wire breakage or short-circuiting.

[0005] To avoid an excessive generation of heat in the wiring, a metal having a higher conductivity such as copper is required to form the wiring. However, it is difficult to perform dry etching on copper or a copper alloy that has been deposited over the entire surface as in the process described above. An alternative process would be to first form channels for the wiring according to a predetermined pattern and then fill the channels with copper or a copper alloy. This method eliminates the process of removing unnecessary parts of the conductive layer by etching, requiring only that the surface of the wafer be polished to remove uneven areas. The method has the additional benefit of being able to form simultaneously multiple areas called plugs that connect the tops and bottoms of channels.

[0006] However, the shape of these wiring channels and plugs have a considerably high aspect ratio (the ratio of depth to width) as the width of the wiring gets smaller, making it difficult to fill the channels with an even layer of metal using sputtering In deposition. The chemical vapor deposition method (CVD) has been used for depositing various materials, but it is difficult to prepare an appropriate gas material for copper or a copper alloy. Further, when using an organic material, carbon from the material becomes mixed in with the deposition layer and increases the resistance.

[0007] Therefore, a method was proposed for performing electroless or electrolytic plating by immersing a substrate into a plating solution. With this method, it is possible to fill wire channels having a high aspect ratio with a uniform layer of metal.

[0008] When performing an electrolytic plating process, for example, generally a plating solution having a composition including copper sulfate and sulfuric acid is used. If the solution has a low concentration of copper sulfate and a high concentration of sulfuric acid, it is known that the plating solution will have high conductivity and great polarization, thereby improving throwing power and coating uniformity. In contrast, if the plating solution has a high concentration of copper sulfate and a low concentration of sulfuric acid, it is known that through the work of an additive the solution will have good leveling ability, in other words, plating will grow from the bottom of the fine pits formed in the substrate surface.

[0009] For this reason, performing a plating process using a plating solution having a composition superior in throwing power and coating uniformity to fill copper in the fine pits of a substrate having a large aspect ratio, the leveling ability of the solution is poor. The inlets of the fine pits will be blocked first before the pits are filled, thereby tending to form voids in the pits. On the other hand, using a plating solution with a composition superior in leveling ability will be inferior in throwing power and coating uniformity, resulting in unplated areas on the walls and bottoms of the fine pits.

[0010] Generally in these plating processes, a copper seed layer is formed on the bottom surface and area surrounding the fine pits of the substrate. However, when performing electrolytic plating directly on a barrier layer, such as TiN or TaN, the sheet resistance of the barrier layer is much larger than the resistance of the copper sulfate plating solution. As a result, needle-shaped crystals are formed in plating processes using copper sulfate solution, resulting in a plating layer having loose adherence.

[0011] In addition a copper pyrophosphate plating solution is also widely used because of its close adhesion due to high polarization and layered deposition property. However, copper pyrophosphate plating solution has poor leveling ability. Hence, when filling fine pits with copper in a plating process using copper pyrophosphate plating solution, the inlets to the fine pits become blocked first, thereby developing voids, as described above. Of course, it is also possible to use copper pyrophosphate plating solution as a first layer over a copper seed layer.

[0012] In view of the foregoing, it is an object of the present invention to provide a method and apparatus of plating a substrate capable of filling fine pits of channels and the like for fine wiring with copper, a copper alloy, or similar material having a low electrical resistance, such that the plating is uniform with no gaps and has a smooth surface.

[0013] These objects and others will be attained by a method for plating a substrate having a surface with fine pits formed therein, the method comprising; performing a first plating process by immersing the substrate in a first plating solution having a composition superior in throwing power; and performing a second plating process by immersing the substrate in a second plating solution having a composition superior in leveling ability.

[0014] With this method, a uniform initial plating layer without unplated areas on the side walls and bottom of the fine pits is formed in the first plating process. A surface plating layer having a smooth surface and no void is formed on top of the initial plating layer in the second plating process.

[0015] According to another aspect of the present invention, the first plating solution is a high throwing power copper sulfate plating solution for printed circuit boards and the second plating solution is a copper sulfate solution. The high throwing power copper sulfate plating solution has a low concentration of copper sulfate, a high concentration of sulfuric acid, and is therefore superior in throwing power and coating uniformity. The copper sulfate plating solution has a high concentration of copper sulfate and a low concentration of sulfuric acid and is superior in leveling ability. As a result, plating metal is uniformly deposited on the surface of the semiconductor wafer, eliminating unplated areas formed on the side and bottom surfaces of the fine pits.

[0016] According to another aspect of the present invention, the high throwing power copper sulfate plating solution has a composition of 5-100 g/l of copper sulfate and 100-250 g/l of sulfuric acid, and the copper sulfate solution has a composition of 100-300 g/l of copper sulfate and 10-100 g/l of sulfuric acid.

[0017] According to another aspect of the present invention, a method for plating a substrate having a surface with fine pits formed therein and coated with a barrier layer, comprises; performing a first plating process by immersing the substrate in a first plating solution having a composition superior in throwing power and in closely adhering to the barrier layer; and performing a second plating process by immersing the substrate in a second plating solution having a composition superior in leveling ability.

[0018] With this method, a uniform initial plating layer without unplated areas on the side walls and bottom of the fine pits covered by the barrier layer is formed in the first plating process. A surface plating layer having a smooth surface and no void is formed on top of the initial plating layer in the second plating process.

[0019] According to another aspect of the present invention, the first plating solution is a copper pyrophosphate solution for printed circuit boards and the second plating solution is a copper sulfate solution. Due to the high polarization and the layered deposition property, the copper pyrophosphate sulfate solution forms a coating in close adherence with the barrier In layer 5 formed of TiN or the like. The copper sulfate plating solution having a high concentration of copper sulfate and a low concentration of sulfuric acid is superior in leveling ability. Hence, this process forms a plating layer free of voids in the fine pits covered by the barrier layer, and the surface of the plating layer is smooth.

[0020] According to another aspect of the present invention, the copper sulfate solution has a composition of 100-300 g/l of copper sulfate and 10-100 g/l of sulfuric acid.

[0021] According to another aspect of the present invention, a substrate plating apparatus comprises a plating bath; first plating solution supplying means for supplying a first plating solution having a composition superior in throwing power to the plating bath; second plating solution supplying means for supplying a second plating solution having a composition superior in leveling ability to the plating bath; and switching means for switching on and off the plating solutions supplied from the first and second plating solution supplying means.

[0022] With this construction, both the first and second plating processes can be performed in the same apparatus, since supply of plating solution is switched between processes, from the first plating solution superior in throwing power to the second plating solution superior in leveling.

[0023] According to another aspect of the present invention, the first plating solution has a composition with qualities superior for close adherence to a barrier layer formed on the surface of the substrate. With this construction, both the first and second plating processes can be performed in the same apparatus, since supply of plating solution is switched between processes, from the first plating solution superior in adherence to the barrier layer to the second plating solution superior in leveling.

[0024] FIGS. 1A-1C are cross-sectional diagrams showing the process for manufacturing a semiconductor element according to the substrate plating method of the present invention;

[0025] FIG. 2 is a flowchart showing the process of the plating method of the preferred embodiment;

[0026] FIGS. 3A-3C are cross-sectional diagrams illustrating the process of FIG. 2;

[0027] FIGS. 4A-4B are cross-sectional diagrams illustrating leveling ability;

[0028] FIG. 5 shows the general construction of a plating apparatus according to the preferred embodiment;

[0029] FIGS. 6A-6C are cross-sectional diagrams showing the differences based on first and second comparisons to the first embodiment;

[0030] FIGS. 7A-7C are cross-sectional diagrams illustrating the process of the plating method according to the second embodiment;

[0031] FIGS. 8A-8C are cross-sectional diagrams showing the differences based on first and second comparisons to the second embodiment; and

[0032] FIG. 9 is a flowchart showing the plating process employing a variation of the plating apparatus shown in FIG. 5.

[0033] A substrate plating method and apparatus according to preferred embodiments of the present invention will be described while referring to the accompanying drawings.

[0034] A substrate plating method according to a first embodiment forms a copper plating on the surface of a semiconductor wafer in order to obtain a semiconductor device having wiring formed from the copper layer. This process is described with reference to FIGS. 1A-1C.

[0035] As shown in FIG. 1A, a semiconductor wafer W is formed of a semiconductor material 1, a conducting layer 1aformed on the top surface of the semiconductor material 1, and an SiO₂insulating layer 2 deposited on top of the conducting layer 1a. A contact hole 3 and a channel 4 are formed in the insulating layer 2 by a lithography etching technique. A barrier layer 5, such as TiN, is formed over the surfaces in the contact hole 3 and channel 4.

[0036] By performing a copper plating process on the surface of the semiconductor wafer W, the contact hole 3 and channel 4 are filled with a copper layer 6. The copper layer 6 is also deposited on top of the insulating layer 2. Next, chemical mechanical polishing (CMP) is performed to remove the copper layer 6 from the top of the insulating layer 2. This process is necessary to form the surface on the copper layer 6 filling the contact hole 3 and channel 4 to be approximately flush with the surface of the insulating layer 2. As a result, the copper layer 6 forms wiring, as shown in FIG. 1C.

[0037] Next, an electrolytic plating process for plating the semiconductor wafer W shown in FIG. 1A will be described with reference to FIG. 2. First, a preprocess is performed. In the preprocess, the semiconductor wafer W is immersed in an aqueous sulfuric acid solution to activate the semiconductor wafer W.

[0038] After washing the semiconductor wafer W, a first plating process is performed by immersing the semiconductor wafer W into a first plating solution, such as a high throwing power copper sulfate plating solution used for printed circuit boards. As shown in FIG. 3A, this process forms a uniform initial plating layer 11 over the surface of a fine pit 10 formed in the semiconductor wafer W, wherein the surface includes the bottom and side walls of the fine pit 10. Here, the high throwing power copper sulfate solution has a low concentration of copper sulfate, a high concentration of sulfuric acid, and is superior in throwing power and coating uniformity. An example composition of this solution is 5-100 g/l of copper sulfate and 100-250 g/l of sulfuric acid.

[0039] Since the plating solution has a low concentration of copper sulfate and a high concentration of sulfuric acid, the conductivity of the solution is high and the polarization is great, thereby improving throwing power. As a result, plating metal is uniformly deposited on the surface of the semiconductor wafer W, eliminating unplated areas formed on the side and bottom surfaces of the fine pit 10.

[0040] After again washing the semiconductor wafer W, a second plating process is performed by immersing the semiconductor wafer W into a second plating solution, such as a copper sulfate plating solution for decorative uses. As shown in FIGS. 3B and 3C, this process forms a plating layer 12 having a flat surface on the surface of the initial plating layer 11. Here, the copper sulfate plating solution has a high concentration of copper sulfate and a low concentration of sulfuric acid and is superior in leveling ability. An example composition of the solution is 100-300 g/l of copper sulfate and 10-100 g/l of sulfuric acid.

[0041] Here, leveling ability defines a quality describing the degree of smoothness on the plating surface. With good leveling ability, it is possible to obtain a plating layer 15ahaving a flat surface, as shown in FIG. 4A, even when a depression 14 is formed in the surface of the semiconductor wafer W. With a poor leveling ability, however, a plating layer 15b, as shown in FIG. 4B, is obtained. Here, the shape of the depression 14 formed in the surface of the semiconductor wafer W is reflected in the plating layer 15b.

[0042] Hence, when using a plating solution having superior leveling ability, film at the inlet to the fine pit 10 grows slow, as shown in FIG. 3B. This slow growth can prevent the generation of voids, thereby filling the fine pit 10 with a uniform layer of copper plating having no gaps. Moreover, it is possible to achieve a smooth surface on the plating.

[0043] Subsequently, the semiconductor wafer W is washed and dried to complete the plating process. This process achieves a plating layer 13 having a flat surface and free of voids. The fine pit 10 contains no unplated areas on its bottom or sidewalls.

[0044] FIG. 5 shows the construction of a plating apparatus suitable for the plating process described above.

[0045] The plating apparatus is provided with a plating bath 20; a first plating solution supplying section 22afor supplying a first plating solution 21 into the plating bath 20; and a second plating solution supplying section 22bfor supplying a second plating solution 23 into the plating bath 20.

[0046] The first plating solution supplying section 22aincludes a pump 24afor pumping first plating solution 21 into the plating bath 20; a shut-off valve 25adisposed upstream from the pump 24a; and a timer 26afor opening and closing the shut-off valve 25a.

[0047] Similarly, the second plating solution supplying section 22bincludes a pump 24bfor pumping second plating solution 23 into the plating bath 20; a shut-off valve 25bdisposed upstream from the pump 24b; and a timer 26bfor opening and closing the shut-off valve 25b.

[0048] In addition, a wash water supply tube 27 and a discharge tube 28 are connected to the plating bath 20 for introducing wash water into the plating bath 20 and discharging wash water out of the plating bath 20, respectively. A pump 29 is connected to the tube 28.

[0049] As described above, a semiconductor wafer W having undergone a preprocess, is inserted into the plating bath 20. Wash water is introduced into the plating bath 20 and the semiconductor wafer W is washed. Next, the shut-off valve 25ais opened according to the timer 26a. The first plating solution 21 is supplied into the plating bath 20, and the first plating process is performed. After a fixed time has elapsed, the shut-off valve 25ais closed. Wash water is again introduced into the plating bath 20 for washing the semiconductor wafer W. Subsequently, the shut-off valve 25bof the second plating solution supplying section 22bis opened according to timer 26b. The second plating solution 23 is supplied into the plating bath and the second plating process is performed. Accordingly, it is possible to perform both the first and second plating processes consecutively using the same apparatus.

[0050] In the example described above, a timer is used for switching the supply of plating solution on and off. However, it is obvious that any means capable of performing this process can be used.

[0051] In the example described above, the same processing tank is used for performing the first plating process, the second plating process, and the washing processes. However, these processes can be performed using separate baths for each process. As shown in FIG. 9, for example, multiple baths can be provided, wherein the plating process is performed by immersing the semiconductor wafer W into each bath in order according to each step of the process.

[0052] In the first embodiment, the fine pit 10 having a width of 1.0 μm or less is formed on the semiconductor wafer W. An aqueous solution having 100 g/l of sulfuric acid is maintained at a temperature of 50° C. A preprocess is performed by immersing the semiconductor wafer W into the aqueous solution for 15 seconds. Subsequently, the first plating process is performed with the first plating solution and, after washing the semiconductor wafer W, the second plating process is performed using the second plating solution. The semiconductor wafer W is then washed and dried.

[0053] In Here, the composition of the first plating solution is as follows.

[0054] The composition of the second plating solution is as follows.

[0055] The conditions for the plating processes, described below, are the same for both processes.

[0056] This process forms the plating layer 13 free of voids in the fine pit 10, as shown in FIG. 6A. No unplated areas are developed in the fine pit 10.

[0057] (First Comparison)

[0058] In a first comparison to the first embodiment, a semiconductor wafer W having undergone the same preprocess described above is plated using only the first plating solution. As shown in FIG. 6B, a void 30 is formed in the plating layer 13 within the fine pit 10.

[0059] (Second Comparison)

[0060] In a second comparison to the first embodiment, a semiconductor wafer W having undergone the same preprocess described above is plated using only the second plating solution. As shown in FIG. 6c, an unplated area 31 exists in a bottom corner of the fine pit 10.

[0061] Next, a second embodiment of the present invention will be described.

[0062] As shown in FIG. 1A, a semiconductor wafer W is formed of a semiconductor material 1, a conducting layer 1aformed on the top surface of the semiconductor material 1, and an SiO₂insulating layer 2 deposited on top of the conducting layer 1a. A contact hole 3 and a channel 4 are formed in the insulating layer 2 by a lithography etching technique. A barrier layer 5, such as TiN, is formed over the surfaces in the contact hole 3 and channel 4.

[0063] First, a preprocess is performed. In the preprocess, the semiconductor wafer W is immersed in an aqueous sulfuric acid solution to activate the semiconductor wafer W. After washing the semiconductor wafer W, a first plating process is performed by immersing the semiconductor wafer W into a first plating solution, such as a copper pyrophosphate solution. As shown in FIG. 7A, this process forms a uniform initial plating layer 11 over the surface including the barrier layer 5. The barrier layer 5 covers the bottom and side walls of a fine pit 10 formed in the semiconductor wafer W.

[0064] Here, the copper pyrophosphate sulfate solution forms a layered deposition providing superior close adherence with the barrier layer 5. Hence, this process forms an initial plating layer 11ahaving a throwing power and prevents the generation of unplated areas on the barrier layer 5 covering the fine pit 10.

[0065] After washing the semiconductor wafer W, a second plating process is performed by immersing the semiconductor wafer W into a second plating solution, such as a copper sulfate plating solution. As shown in FIGS. 7B and 7C, this process forms a plating layer 12 having a flat surface on the surface of the initial plating layer 11a. Here, the copper sulfate plating solution has a high concentration of copper sulfate and a low concentration of sulfuric acid and is superior in leveling ability. An example composition of the solution is 100-300 g/l of copper sulfate and 10-100 g/l of sulfuric acid.

[0066] In the second embodiment, the fine pit 10 having a width of 1.0 μm or less is formed on the semiconductor wafer W. The barrier layer 5 covers the fine pit 10. An aqueous solution having 100 g/l of sulfuric acid is maintained at a temperature of 50° C. A preprocess is performed by immersing the semiconductor wafer W into the aqueous solution for 15 seconds. Subsequently, the first plating process is performed with the first plating solution and, after washing the semiconductor wafer W, the second plating process is performed using the second plating solution. The semiconductor wafer W is then washed and dried.

[0067] Here, the composition of the first plating solution is as follows.

[0068] The conditions for the plating process are as follows.

[0069] The composition of the second plating solution is as follows.

[0070] The conditions for the plating process are as follows.

[0071] This process forms a plating layer 14 free of voids in the fine pit 10, as shown in FIG. 8A. No unplated areas are developed on the barrier layer 5 within the fine pit 10.

[0072] (First Comparison)

[0073] In a first comparison to the first embodiment, a semiconductor wafer W having undergone the same preprocess described above is plated using only the first plating solution. As shown in FIG. 8B, a void 30 is formed in the plating layer 14 within the fine pit 10.

[0074] (Second Comparison)

[0075] In a second comparison to the first embodiment, a semiconductor wafer W having undergone the same preprocess described above is plated using only the second plating solution. As shown in FIG. 8C, an unplated area 31 exists on the barrier layer 5 in a bottom corner of the fine pit 10.

[0076] In the first plating process of the present invention described above, a uniform initial plating layer without unplated areas on the side walls and bottom of the fine pit 10 is formed. In the second plating process of the present invention, a surface plating layer having a smooth surface and no void is formed on top of the initial plating layer. Accordingly, fine pits formed in the substrate, such as fine channels for wiring, can be filled with a copper, copper alloy, or other material having low electrical resistance without gaps in the metal plating and with an level surface.

[0077] The present invention is a plating process capable of forming embedded wiring layers and the like in semiconductor wafers and can be applied to the fabrication of LSI chips and other semiconductor devices.