Receiver capable of selecting optimal voltage controlled oscillator

[0002] 1. Field of the Invention

[0003] The present invention relates to receivers, and more specifically to a receiver for down-converting an inputted signal via an antenna and then demodulating the converted signal.

[0004] 2. Description of the Background Art

[0005] Conventionally, in some cases, a receiver down-converts a signal S inputted from outside to a signal with an intermediate frequency band (hereinafter referred to as IF band). Down-conversion can be realized by mixing the inputted signal S (frequency f_S) with a local oscillation output V_O(frequency f_O) in a mixer inside the receiver.

[0006] The local oscillation output V_Ois conventionally generated by a voltage controlled oscillator (hereinafter referred to as VCO) having a circuitry constitution as shown in FIG. 11. The VCO of FIG. 11 is structured of discrete components, comprising a surface acoustic wave (SAW) resonator 111, a variable capacitance diode 112 and other components. Note that FIG. 11 also shows an equivalent circuit of the SAW resonator 111. The variable capacitance diode 112 is connected in parallel to the SAW resonator 111. With the capacity of the variable capacitance diode 112 adjusted and further with a predetermined control voltage V_Capplied to the VCO, the VCO generates the local oscillation output V_Ohaving variable frequency.

[0007] The SAW resonator 111 is expensive and large in size, and its peripheral circuits are structured of discrete components. It is therefore difficult to downsize the VCO and construct it at low cost, and furthermore know-how for mounting these components is required. Against such background, the VCO has come to be constituted on an integrated circuit. FIG. 12 shows a circuit diagram of a VCO constituted on an integrated circuit. As compared with the VCO of FIG. 11, the VCO of FIG. 12 is different in that it takes an integrated circuit form and that an LC oscillator 121 is substituted for the SAW resonator 111.

[0008] Assume that a large number of ICs including the VCOs of FIG. 12 are manufactured under certain conditions. For each of the VCOs, a characteristic of the frequency f_Oof the local oscillation output V_Owith respect to the control voltage V_C(hereinafter referred to as f_Ovs. V_Ccharacteristic) is measured. The f_Ovs. V_Ccharacteristic curve has a linear region and a saturation region. Furthermore, the f_Ovs. V_Ccharacteristic curves disperse with a constant deviation from a design target of the VCOs (refer to a double-headed arrow in FIG. 13). Such dispersion is hereinafter referred to as manufacturing dispersion. Due to this manufacturing dispersion, the saturation region of the f_Ovs. V_Ccharacteristic curve is within a receive band B in some cases. As a result, the receiver cannot down-convert the inputted signal S correctly. It is therefore ideal that each VCO manufactured under the same conditions does not have manufacturing dispersion, which is however difficult in reality. The receive band B is a frequency band which the receiver including the VCOs has to receive and also with which the above signal S is sent out.

[0009] For this reason, the following method has been considered. A plurality of VCOs with different f_Ovs. V_Ccharacteristic curves from each other are integrated in an IC. When the control voltage V_Cof the same level is applied, the plurality of VCOs generate the local oscillation output V_Owith a different frequency f_O, respectively. A VCO control portion is placed on the periphery of each of such VCOs. The VCO control portion has to select one VCO whose f_Ovs. V_Ccharacteristic curve reliably covers the receive band B from among the plurality of VCOs. Further, this selecting processing is preferably carried out at high speed.

[0010] Therefore, an object of the present invention is to provide a receiver for selecting an appropriate VCO at high speed. This object is achieved by the following aspects. Further, each aspect has unique technical effects as described below.

[0011] A first aspect of the present invention is directed to a receiver for subjecting an inputted signal via an antenna to down-conversion and then demodulating the converted signal, comprising:

[0012] a plurality of voltage controlled oscillators (hereinafter referred to as VCOs), each provided with a common control voltage and generating a local oscillation output having a different frequency according to the control voltage;

[0013] a PLL circuit for generating the control voltage based on the local oscillation output fed back from each of the VCOs and a reference signal having a reference frequency;

[0014] a mixer for mixing frequencies of the inputted signal via the antenna and the local oscillation output from each of the VCOs, and performing the down-conversion; and

[0015] a VCO control portion for testing each of the VCOs in a test mode to be executed in advance, and controlling switching of the VCOs in a receive mode of receiving the inputted signal via the antenna;

[0016] in the test mode, the VCO control portion

[0017] detecting whether the PLL circuit locks using the local oscillation output from each of the VCOs or not as sequentially switching and activating the VCOs, and determining one appropriate VCO based on a detected result;

[0018] in the receive mode, the VCO control portion

[0019] selectively activating the VCO determined in the test mode, and providing a local oscillation output of the VCO f or the mixer.

[0020] In the first aspect, in the test mode, the appropriate VCO is selected for use in the receive mode. In this test mode, the VCO control portion sequentially switches and activates the VCOs to determine an optimal VCO based on the detected result as to whether the PLL circuit locks using the local oscillation output from each VCO. Therefore, in the receive mode, the mixer performs down-conversion using the local oscillation output from the VCO with which the PLL circuit reliably locks. This allows the receiver according to the first aspect to select an appropriate VCO for the above down-conversion.

[0021] According to a second aspect, in the first aspect, the VCO control portion holds the detected result in a first table as pattern data, refers to a second table into which the appropriate VCO for each assumed pattern is written, and determines the appropriate VCO corresponding to the pattern data held in the first table.

[0022] In the second aspect, the VCO control portion determines the optimal VCO corresponding to the pattern data stored in the first table referring to the second table. Previously written into the second table are assumed patterns and their corresponding optimal VCOs. This allows the receiver according to the second aspect to select the optimal VCO corresponding to the detected result.

[0023] According to a third aspect, in the first aspect, the second table is configured based on manufacturing dispersion of the VCOs.

[0024] In accordance with the third aspect, the second table is configured based on the above manufacturing dispersion. This allows the receiver according to the third aspect to select the optimal VCO irrespective of manufacturing dispersion of the VCOs.

[0025] According to a fourth aspect, in the first aspect, the PLL circuit includes a programmable divider for dividing the fed-back local oscillation output using a predetermined dividing ratio set by the VCO control portion, and generates a control voltage based on a local oscillation output divided by the programmable divider and the reference signal; and

[0026] in the test mode, the VCO control portion sets a reference dividing ratio with which each of the VCOs can generate a local oscillation output having a frequency within a band in which the inputted signal is included as the predetermined dividing ratio.

[0027] In accordance with the fourth aspect, since the reference dividing ratio as described above is set in the programmable divider, it is possible to let the PLL circuit lock according to the inputted signal.

[0028] According to a fifth aspect, in the fourth aspect, the reference dividing ratio is a dividing ratio with which each of the VCOs can generate a local oscillation output having a center frequency of the band.

[0029] In the fifth aspect, as evident from the above, the reference dividing ratio is set based on a center frequency of the above band, that is, an average value, and PLL circuit can thus lock at the highest speed. This allows the receiver to execute the test mode in the shortest time.

[0030] According to a sixth aspect, in the first aspect, the VCO control portion stores information of the VCO determined in the test mode executed last time; and

[0031] when executing the test mode again, the VCO control portion first tests the stored information of the VCO and determines again that the VCO is an optimal VCO when the PLL circuit locks using the local oscillation output from the VCO.

[0032] In accordance with the sixth aspect, when it is determined again that the VCO first tested is the optimal one at the time of executing the test mode again, the VCO control portion makes a transition to the receive mode. This can reduce the time for a transition from the test mode to the receive mode.

[0033] According to a seventh aspect, in the first aspect, the PLL circuit and each of the VCOs are integrated in a same circuit.

[0034] In accordance with the seventh aspect, the above integration in a circuit allows reduction in size and cost of the receiver. Further, unlike when discrete components are used, know-how about mounting the components is not required for manufacturing the receiver.

[0035] An eighth aspect is directed to a receiver for subjecting a signal inputted via an antenna to down-conversion and then demodulating the converted signal, comprising:

[0036] a plurality of voltage controlled oscillators (hereinafter referred to as VCOs), each provided with common control voltage and generating a local oscillation output having a different frequency according to the control voltage;

[0037] a PLL circuit for generating the control voltage based on the local oscillation output fed back from each of the VCOs and a reference signal having a reference frequency;

[0038] a mixer for mixing frequencies of the inputted signal via the antenna and the local oscillation output from each of the VCOs, and performing the down-conversion; and

[0039] a VCO control portion for testing each of the VCOs in a test mode to be executed in advance, and controlling switching of the VCOs in a receive mode of receiving the signal inputted via the antenna;

[0040] in the test mode, the VCO control portion

[0041] detecting whether the PLL circuit locks using the local oscillation output from each of the VCOs as sequentially switching and activating the VCOs, and when a value of the control voltage generated by the PLL circuit is within a predetermined range, determining which one of the VCOs provided with the control voltage is an appropriate VCO;

[0042] in the receive mode, the VCO control portion

[0043] selectively activating the VCO determined in the test mode, and providing a local oscillation output of the VCO for the mixer.

[0044] In the eighth aspect, in the test mode, the optimal VCO is selected for use in the receive mode. In this test mode, the VCO control portion sequentially switches and activates the VCOs to determine an optimal VCO based on the detection result as to whether the PLL circuit locks using the local oscillation output from each VCO or not and based on whether the control voltage value which the PLL circuit generates using the local oscillation output is within a predetermined range or not. On detecting the VCO which satisfies these two conditions, the VCO control portion determines that this VCO is the optimal one. Therefore, in some cases, the VCO control portion does not activate all VCOs. This allows the receiver according to the eighth aspect to execute the test mode at higher speed than the receiver according to the first aspect and to make a transition to the receive mode. Furthermore, in the receive mode, the mixer performs down-conversion using the local oscillation output from the VCO with which the PLL circuit reliably locks. This allows the receiver according to the eighth aspect to select an appropriate VCO for the above down-conversion from among the plurality of VCOs.

[0045] According to a ninth aspect, in the eighth aspect, the predetermined range includes only one value of the control voltage which is provided when each of the VCOs generates a local oscillation output having a same frequency.

[0046] In the ninth aspect, the control portion determines an optimal VCO based on the above predetermined range, and therefore only the optimal VCO can be selected.

[0047] According to a tenth aspect, in the eighth aspect, the PLL circuit includes a programmable divider for dividing the fed-back local oscillation output using a predetermined dividing ratio set by the VCO control portion, and generates a control voltage based on a local oscillation output divided by the programmable divider and the reference signal; and

[0048] in the test mode, the VCO control portion sets a reference dividing ratio with which each of the VCOs can generate a local oscillation output having a frequency within a band in which the inputted signal is included as the predetermined dividing ratio.

[0049] According to an eleventh aspect, in the tenth aspect, the reference dividing ratio is a dividing ratio with which each of the VCOs can generate a local oscillation output having a center frequency of the band.

[0050] According to a twelfth aspect, in the eighth aspect, the VCO control portion stores information of the VCO previously determined in the test mode executed last time; and

[0051] when executing the test mode again, the VCO control portion first tests the stored information of the VCO and determines again that the VCO is an optimal VCO when the PLL circuit locks using the local oscillation output from the VCO.

[0052] According to a thirteenth aspect, in the eighth aspect, the PLL circuit and each of the VCOs are integrated in a same circuit.

[0053] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

[0054] FIG. 1 shows the block structure of a receiver according to first to fourth embodiments of the present invention,

[0055] FIG. 2 shows frequency f_Ovs. control voltage V_Ccharacteristics of a VOC 1₁lto a VOC 1₃;

[0056] FIG. 3 is a flow chart showing the procedure of a test mode of the first embodiment;

[0057] FIG. 4 shows a first table TA_Sand a second table TA_R;

[0058] FIGS. 5a, 5a′, 5b, 5b′, 5cand 5c′ are diagrams for describing the relation between the f_Ovs. VC characteristics of the VOC 1₁to the VOC 1₃, and the first and second tables TA_Sand TA_R;

[0059] FIG. 6 is a flow chart showing the procedure of a test mode of the second embodiment;

[0060] FIGS. 7aand 7bare diagrams for describing V_CAand V_CBin the second embodiment;

[0061] FIG. 8 is a flow chart showing the procedure of a test mode of the third embodiment;

[0062] FIG. 9 is a diagram for describing n_OPTstored in memory 32 of the third embodiment;

[0063] FIG. 10 is a flow chart showing the procedure of a test mode of the fourth embodiment;

[0064] FIG. 11 shows an example of structure of a conventional VCO including an SAW resonator;

[0065] FIG. 12 shows an example of structure of another conventional VCO including an LC resonator; and

[0066] FIG. 13 shows f_Ovs. V_Ccharacteristic curves of the VCOs of FIG. 12.

[0067] FIG. 1 is a block diagram showing the structure of a receiver according to first to fourth embodiments of the present invention. In FIG. 1, the receiver includes a plurality of (three, in FIG. 1) VCOs, VCO 1₁to VCO 1₃, to be controlled, a phase locked loop (PLL) circuit 2, a microcomputer 3, a VCO switching circuit 4, a buffer amplifier 5, an antenna 6, an RF amplifier 7 and a mixer 8. Preferably, the VCO 1₁to VCO 1₃, the PLL circuit 2, the VCO switching circuit 4, the buffer amplifier 5, the RF amplifier 7 and the mixer 8 are integrated inside an integrated circuit.

[0068] The PLL circuit 2 includes a programmable divider 21, a reference frequency oscillator 22, a phase comparator 23, a lock detector 24 and a low pass filter (LPF) 25. The microcomputer 3 includes a receive control portion 31, memory 32 and an A/D converter 33. The microcomputer 3 and the VCO switching circuit 4 construct a VCO control portion.

[0069] Described next are f_Ovs. V_Ccharacteristics (described above) of VCO 1₁to VCO 1₃referring to FIG. 2. In the graph of FIG. 2, the lateral axis represents the frequency f_Oof the local oscillation output, and the horizontal axis represents the control voltage V_C.

[0070] A receive band B is a receive frequency band of the receiver and also a frequency band within which a signal S transmitted from outside to the receiver is included. More specifically, when the signal S is within an L band (1.45 to 1.49 [GHz]), for example, of the receive band B is within approximately 1.45 to 1.49 [GHz]. A center frequency F_VCis a center of the receive band B. A minimum frequency F_VMINis a minimum frequency of the receive band B, while a maximum frequency F_VMAXis its maximum frequency. Under such conditions, the VCO 1₁to VCO 1₃are designed under a design target as described below.

[0071] The VCO 1₂is designed so as to generate a local oscillation output V_O2having the center frequency F_VCwhen a control voltage V_CCis applied from the PLL circuit 2. The VCO 1₂is also designed so as to generate the local oscillation output V_O2with the minimum frequency F_VMINand the maximum frequency F_VMAXwhen control voltages V_C1and V_C2are applied, respectively. Furthermore, in consideration of manufacturing dispersion, the VCO 1₂is generally designed so that its local oscillation frequency band is approximately not less than twice as wide as the receive band B. The oscillation frequency band of the VCO 1₂is preferably within from F_VC−B to F_VC+B. The VCO 1₂is designed so as to generate the local oscillation output V_O2with a center frequency F_VC−B when a control voltage V_C1is applied and with a center frequency F_VC+B when a control voltage V_C2is applied, respectively. Therefore, the f_Ovs. V_Ccharacteristic of the VCO 1₂becomes as shown by a one-dot-chain line in FIG. 2. The f_Ovs. V_Ccharacteristic curve is shaped linearly within the oscillation frequency band of the VCO 1₂, while nonlinearly (or in the saturation regions) outside this band.

[0072] The VCO 1₁and the VCO 1₃are designed with reference to the f_Ovs. V_Ccharacteristic of the VCO 1₂. Specifically, as shown in FIG. 2, when the above signal S is of the L band (described above), the VCO 1₁and the VCO 1₃are designed so as to have f_Ovs. V_Ccharacteristic shifted by approximately B/2 to the low frequency side and the high frequency side, respectively, as compared with the f_Ovs. V_Ccharacteristic of the VCO 1₂. The f_Ovs. V_Ccharacteristic curves of the VCO 1₁and the VCO 1₃are shown by a dotted line and a two-dot-chain line, respectively, in FIG. 2. Each of these f_Ovs. V_Ccharacteristic curves also has a linear region and a saturation region. The VCO 1₁and the VCO 1₃are designed as described above.

[0073] Referring to FIG. 2, it can be seen that each of the VCO 1₁to VCO 1₃oscillates different frequencies f_VO1to f_VO3, respectively, when the control voltage V_Cis constant within the range of V_CMIN<V_C<V_CMAX.

[0074] The f_Ovs. V_Ccharacteristic curves may be shifted as a whole in an arrow direction A or B with respect to the above design target due to manufacturing dispersion.

[0075] Furthermore, each VCO is provided with a VCO number. This VCO number is uniquely provided in advance for each of the plurality of VCOs in order to identify each VCO. In this description, the VCO 1₁to the VCO 1₃are provided with VCO numbers “1” to “3”, respectively.

[0076] FIG. 3 is a flow chart showing the procedure of a test mode to be executed by the receiver according to the first embodiment. A program for realizing this procedure is previously stored in ROM (not shown) and the like within the microcomputer 3. Note that flow charts of FIGS. 6, 8 and 10, which will be described later, show the procedure of a test mode according to the second, third and fourth embodiments, respectively, and a program for realizing the procedure is also previously stored in ROM and the like.

[0077] Described below is operation of the receiver of the first embodiment based on FIGS. 1 to 3. Note that the receivers according to the first and third embodiments do not use the A/D converter 33.

[0078] The receive control portion 31 starts the test mode immediately after the receiver is powered on. The receive control portion 31 then sets a VCO number “n” to an initial number “1” (step S301) and thereby selects the VCO 1₁to be tested.

[0079] The receive control portion 31 then sends out a signal Sel (step S302) to notify the VCO switching circuit 4 of the selected VCO 1. The signal Sel has three types: Sel₁, Sel₂and Sel₃, which are signals for notifying selection of the VCO 1₁, VCO 1₂and VCO 1₃, respectively. At this time, Sel₁is sent out.

[0080] Based on the type of the inputted Sel, the VCO switching circuit 4 recognizes the selected VCO 1 (step S303), and outputs a signal V_Bfor activating the VCO 1 to be tested (step S304, S311 or S313). The signal V_Balso has three types: V_B1, V_B2and V_B3, which are signals for activating the VCO 1₁, VCO 1₂and VCO 1₃, respectively. At this time, the VCO switching circuit 4 recognizes that the VCO 1₁has been selected, and therefore sends out V_B1(step S304). As a result, at this time, the VCO 1₁is activated (step S305), while the VCO 1₂and the VCO 1₃are not.

[0081] The receive control portion 31 sends out Sel in step S302, and then a signal N_typafter any one of the VCOs 1 starts being active (step S306) to set a dividing ratio of the programmable divider 21. N_typis a signal preferably for setting a dividing ratio with which the VCO 1₁to the VCO 1₃can generate the local oscillation outputs V_O1to V_O3with the center frequency F_VC, respectively, in consideration that the PLL circuit 2 can lock at high speed. It is to be noted that N_typis not restricted as described above, but may be a signal for setting a dividing ratio with which the VCO 1₁to the VCO 1₃can generate the local oscillation outputs V_O1to V_O3, respectively, with any frequency within the range of F_VMINto F_Vmax.

[0082] The PLL circuit 2 starts being active when N_typis set in the programmable divider 21 and any of the VCOs 1 starts operation.

[0083] Specifically, inputted in the programmable divider 21 is a local oscillation output V_Ogenerated by the currently active VCO 1. The programmable divider 21 divides the inputted local oscillation output V_Ousing the dividing ratio N_typ. The reference frequency generator 22 outputs a reference signal RS having a predetermined reference frequency F_REF. Both of the divided local oscillation output V_Oand the reference signal RS are inputted to the phase comparator 23 and the lock detector 24. The phase comparator 23 compares phases between the inputted local oscillation output V_Oand the reference signal RS, and outputs the obtained result to the LPF 25. Based on the inputted result, the LPF 25 generates a signal indicating an instantaneous phase difference between the local oscillation output V_Oand the reference signal RS as a direct-current control signal V_Cby low pass filtering, and outputs to the active VCO 1. The PLL circuit 2 controls the oscillation frequency f_VOof the VCO 1 by the control signal V_C1so that the oscillation frequency f., matches the frequency F_REF. This tracking is herein referred to as “the PLL circuit 2 locks”. For this locking, V_Chas to satisfy a conditional equation V_CMIN<V_C<V_CMAX(1). In the course of tracking, the local oscillation output V_Ogenerated by the active VCO 1 is fed back to the programmable divider 2.

[0084] The lock detector 24 also compares the phases between the inputted local oscillation output V_Oand the signal RS. The obtained result has a voltage level correlating with the control voltage V_C. The lock detector 24 determines whether the voltage level of the result satisfies the above conditional equation (1), and generates a signal L for notifying the receive control portion 31 of the determination result. The signal L has two types. When the voltage level satisfies the conditional equation (1), the lock detector 24 generates a signal L₁indicating that the PLL circuit 2 locks, and outputs to the receive control portion 31. On the other hand, when the voltage level does not satisfy the conditional equation (1), the lock detector 24 generates a signal L₂indicating that the PLL circuit 2 does not lock, and outputs to the receive control portion 31.

[0085] With the above described signal L inputted, the receive control portion 311 determines whether the PLL circuit 2 locks using the oscillation frequency output generated by the active VCO 1 according to the type of signal L (step S307), and writes the determination result as a status into a first table TA_Sas shown in FIG. 4 (step S308). The first table TA_Sof FIG. 4 is previously provided in the memory 32. The first table TA_Sis configured so that a status is written for each VCO 1. For example, when the VCO 1₁is selected and the PLL circuit 2 locks, 1 is written into an appropriate field on the first table TA_SOn the other hand, when the PLL circuit 2 does not lock, 0 is written into

[0086] The receive control portion 31 next determines whether n=n_max(step S309), where n_MAXis a maximum value of the VCO number “n”, which is “3” in the first embodiment. When n≠n_MAX, the receive control portion 31 determines that one or more VCOs 1 to be tested still remain, and the procedure advances to step S310. On the other hand, when n=n_MAX, the receive control portion 31 determines that no VCO 1 to be tested remains, and the procedure advances to step S315.

[0087] Since n=“1” at this moment, the receive control portion 31 updates “n” to “n+1” (step S311), and selects the VCO 1₂which is the VCO 1 with the next VCO number “2” provided. In this case, steps S302→S303→S311→S312 of FIG. 3 are sequentially executed. In this procedure, Sel₂and V_B2are outputted (steps S302 and S311), and as a result only the VCO 1₂is activated (step S312). The receive control portion 31 then executes steps S306 to S308 to write the status of the VCO 1₂into the first table TA_S(step S308).

[0088] Next, since n=2 at this moment, the receive control portion 31 updates “n” to “n+1” (step S311), and then sequentially executes steps S302→S303→S313→S314. In this procedure, Sel₃and V_B3are outputted (steps S302 and S313), and as a result only the VCO 1₃is activated (step S314). The receive control portion 31 then executes steps S306 to S308 to write the status of the VCO 1₃into the first table TA_S(step S308).

[0089] The receive control portion 31 next executes step S309. Since n=n_MAX(=3) at this moment, the procedure advances to step S315. As described above, the receive control portion 31 sets the above predetermined dividing ratio N_typin the programmable divider 21, and determines whether the PLL circuit 2 locks as to the VCO 1₁to VCO 1₃in sequence. Based on the determination result, the receive control portion 31 then writes the status of the VCO 1¹to VCO 1₃into the first table TA_S. As a result, three-digit binary information (0 or 1) is created in the first table TA_S. The pattern of the binary information, that is, pattern data, is any one of “1, 1, 1”, “1, 1, 0” or “0, 1, 1”, as described later. Note that the pattern data represents the status of the VCO 1¹, VCO 1₂and VCO 1₃, sequentially fro the left value.

[0090] In addition, a second table TA_Ras shown in FIG. 4 is previously provided for the memory 32. Previously written in the second table TAR are combinations of each pattern and the optimal VCO 1 for each case. There are three cases: the pattern “1, 1, 1” for a case 1; “1, 1, 0” for a case 2; and “0, 1, 1” for a case 3.

[0091] Note that no other pattern exists, because, in consideration of manufacturing dispersion of the VCO 1₁, VCO 1₂and VCO 1₃, three f_Ovs. V_Ccharacteristic curves are shifted within only a predetermined range (by the degree of several percent of F_VC) to the high frequency side or the low frequency side (refer to FIG. 2). Consequently, for example, as to the VCO 1₁, VCO 1₂and VCO 1₃, the saturation regions of any two of the f_Ovs. V_Ccharacteristic curves do not fall into the receive band B at the same time. It is therefore not necessary to consider other patterns such as 0, 0, 1.

[0092] Also previously written in the second table TA_Ris the optimal VCO 1 to be used by the receiver for down-converting the signal S from outside for each pattern. That is, in the pattern of the case 1, the VCO 1₂is the optimal VCO 1. When the pattern data such as in the case 1 is obtained, the PLL circuit 2 locks using the local oscillation output generated in all of the VCOs 1. The f_Ovs. V_Ccharacteristic curve of each of the VCOs 1 is, as shown in FIG. 5a, as the design target. In this case, referring to FIG. 5a, it can be seen that the linear region of the f_Ovs. V_Ccharacteristic curve of the VCO 1₂most reliably covers the receive band B, and therefore the VCO 1₂is the optimal VCO 1 (refer to a dotted row of FIG. 5a′).

[0093] In the case 2, the VCO 1₃is the optimal VCO 1. When the pattern data such as in the case 2 is obtained, the PLL circuit 2 locks using the local oscillation output generated in the VCO 1₂or the VCO 1₃. At this time, as compared with the case shown in FIG. 5a, the f_Ovs. V_Ccharacteristic curves are shifted as a whole to the low frequency side by the frequency B due to manufacturing dispersion, as shown in FIG. 5b. In this case, the linear region of the f_Ovs. V_Ccharacteristic curve of the VCO 1₃most reliably covers the receive band B, and therefore the VCO 1₃is the optimal VCO 1 (refer to a dotted row of FIG, 5b′).

[0094] Furthermore, in the case 3, the VCO 1₁is the optimal VCO 1. When the pattern data such as in the case 3 is obtained, the PLL circuit 2 locks using the local oscillation output generated in the VCO 1₁or the VCO 1₂. At this time, as compared with the case shown in FIG. 5a, the f_Ovs. V_Ccharacteristic curves are shifted as a whole to the high frequency side by the frequency B, as shown in FIG. 5c. In this case, the linear region of the f_Ovs. V_Ccharacteristic curve of the VCO 1₁most reliably covers the receive band B, and therefore the VCO 1₁is the optimal VCO 1 (refer to a dotted row of FIG. 5c′).

[0095] The receive control portion 31 determines n=n_MAXin step S309, and then determines the optimal VCO 1 referring to the second table TA_R(step S315). The pattern data created in the first table TA_S(refer to FIG. 4) matches any one of the patterns of the case 1 to case 3 in the second table TA_R. The receive control portion 31 retrieves the case which matches the created pattern data and the optimal VCO 1 for the case.

[0096] Described next is operation of the receive control portion 31 in step S315 more specifically. When the created pattern data matches the case 1₁the receive control portion 31 determines that the VCO 1₂is the optimal VCO 1 (refer to the dotted row of FIG. 5a′). When the created pattern data matches the case 2, the receive control portion 31 determines that the VCO 1₃is the optimal VCO 1 (refer to the dotted row of FIG. 5b′). When the created pattern data matches the case 3, the receive control portion 31 determines that the VCO 1₁is the optimal VCO 1 (refer to a dotted row of FIG. 5c′).

[0097] The receive control portion 31 next sends out Sel_OPT(step S316) to notify the VCO switching circuit 4 of the optimal VCO 1 determined in step S315. Sel_OPThas tree types, like Sel. The VCO switching circuit 4 determines the type of the inputted Sel_OPTto recognize the optimal VCO 1 (step S317). The VCO switching circuit 4 then outputs V_B1, V_B2or V_B3as described above in order to activate the optimal VCO 1 (step S304, S311 or S313). As a result, of the VCO 1₁, VCO 1₂and VCO 1₃, the determined optimal VCO 1 is activated (step S305, S312 or S314). The receive control portion 31 thus ends the test mode.

[0098] When the above test mode ends, the receiver starts a receive mode. In the receive mode, the predetermined signal S (frequency f_S) coming from outside is inputted to the antenna, and the inputted signal S is amplified by the RF amplifier 7. The amplified signal S is inputted to the mixer 6. Also inputted to the mixer 6 is the local oscillation output V_O(frequency f_VO) from the optimal VCO 1 determined in the test mode. The mixer 6 down-converts the inputted signal S with the local oscillation output. Also in the receive mode, the PLL circuit 2 controls the oscillation frequency f_VOof the determined VCO 1 by the control signal V_Cgenerated in the above described manner, so that the oscillation frequency f_VOwhich is fed back and then divided by the programmable divider 21 matches the frequency f_REF.

[0099] As described above, according to the receiver of the first embodiment, the receive control portion 31 determines in step S307 whether the PLL circuit 2 locks for each VCO 1. In step S308, the receive control portion 31 writes the determination result as the status into the first table TA_S(refer to FIG. 4). The receive control portion 31 then determines in step S315 the optimal VCO 1 referring to the second table TA_Rand the first table TA_S.

[0100] Described next is a receiver according to a second embodiment of the present invention. The structure of the receiver is shown in FIG. 1 and its description is omitted herein.

[0101] FIG. 6 is a flow chart showing the procedure of a test mode to be executed by the receiver according to the second embodiment. Note that the flow chart of FIG. 6 includes some steps which are the same as those in the flow chart of FIG. 3. Therefore, the corresponding steps are provided with the same step numbers as in FIG. 3, and their description is omitted. Described below is operation of the receiver based on FIGS. 1 and 6.

[0102] In FIG. 6, the procedure before step S601 is the same as the procedure up until step S307 in FIG. 3. At the end of step S307, the receive control portion 31 determines whether the PLL circuit 2 locks using the local oscillation output generated in the active VCO 1 (step S307).

[0103] When determining that the PLL circuit 2 does not lock (step S601), the receive control portion 31 determines that the active VCO 1 cannot be the optimal VCO 1₁and updates “n” to “n+1” (step S310), selecting the VCO 1 with the next VCO number provided, and the procedure advances to step S302.

[0104] On the other hand, when determining that the PLL circuit 2 locks (step S601), the receive control portion 31 activates the A/D converter 33. As a result, the control voltage V_Coutputted from the LPF 25 is inputted to the A/D converter 33. The A/D converter 33 subjects the control voltage V_Cto A/D conversion, measuring and digitizing the control voltage V_C1and then sends out the result to the receive control portion 31.

[0105] The receive control portion 31 next determines whether the value of the inputted control voltage V_Csatisfies a conditional equation V_CA<V_C<V_CB(2) (step S603). V_CAand V_CBof the conditional equation (2) are now described referring to FIGS. 7aand 7b. As described above, when N_typis set in the programmable divider 21, each of the VCOs 1 generates the local oscillation output V_Ohaving the oscillation frequency F_VC. At this time, however, the control voltages V_Capplied to the VCOs 1 are different from each other: V_CCis applied to the VCO 1₂, V_C2to the VCO 1₁and V_C1to the VCO 1₃. V_CA<V_C<V_CBcovers a range smaller than V_CMIN<V_C<V_CMAXin which the the PLL circuit 2 reliably locks, and the range does not include the plurality of control voltages V_Cof the VCOs 1, as shown in FIG. 7a. That is, in FIG. 7a, V_CA<V_C<V_CBis represented by a dotted area, and only the control voltage V_Cof the VCO 1₂is included in this range. V_CAand V_CBare thus determined. Furthermore, manufacturing dispersion of the VCOs are considered for determining V_CAand V_CB.

[0106] When the above value does not satisfy the conditional equation (2) in step S603, the receive control portion 31 determines that the active VCO 1 is not the optimal one, updates “n” to “n+1” (step S310), and then the procedure advances to step S302 in order to determine whether the VCO 1 with the next VCO number is the optimal one or not.

[0107] On the other hand, when the above value satisfies the conditional equation (2), the receive control portion 31 determines in step S603 that the active VCO 1 is the optimal one (step S604).

[0108] In FIG. 6, the procedure after step S604 is the same as the procedure from step 316 and thereafter in FIG. 3.

[0109] According to the above described test mode, when each VCO 1 has the f_Ovs. V_Ccharacteristic as the design target, as evident from FIG. 7a, the VCO 1₂is selected as the optimal VCO 1. However, as compared with FIG. 7a, when the f_Ovs. V_Ccharacteristics of the VCOs 1 are shifted as a whole to the low frequency side due to manufacturing dispersion (refer to FIG. 7b), the VCO 1₃is selected as the optimal VCO 1 in some cases. Note that, since it is clear from the above description that the VCO 1₁is selected as the optimal VCO 1 in some cases when the f_Ovs. V_Ccharacteristics of the VCOs 1 are shifted to the high frequency side, its illustration in particular is omitted herein.

[0110] As described above, according to the receiver of the second embodiment, as in the first embodiment, an optimal VCO 1 is determined. The receiver according to the first embodiment determines whether the PLL circuit 2 locks as to all VCOs 1. However, the receiver of the second embodiment determines in sequence whether the PLL circuit 2 locks for each VCO 1, and once the optimal VCO 1 is determined, the mixer 8 can immediately perform down-converting of the signal S with the determined optimal VCO 1. This increases the speed of the test mode. Described next is operation of a receiver according to a third embodiment of the present invention. The structure of the receiver is shown in FIG. 1 and its description is omitted herein.

[0111] FIG. 8 shows a flow chart showing the procedure of a test mode to be executed by the receiver according to the third embodiment. Note that the flow chart of FIG. 8 includes some steps which are the same as those in the flow chart of FIG. 3. Therefore, the corresponding steps are provided with the same step numbers as in FIG. 3, and their description is omitted. Described below is operation of the receiver based on FIGS. 1 and 8.

[0112] Step S315 of FIG. 8 is the same as step S315 of FIG. 3. That is, the receive control portion 31 determines n=nmx in step S309, and then determines the optimal VCO 1 referring to the first table TA, and the second table TA_R(step S315). The receive control portion 31 then sends out Sel_OPTto notify the VCO switching circuit 4 of the optimal VCO 1 selected in step S315, and writes the VCO number of the optimal VCO 1 as “n_OPT” into a field 101 (refer to FIG. 9) previously provided in the memory 32 (step S86). Written into this field 101 is “1”, “2” or “3”.

[0113] After that, the receiver executes steps S317→S304→S305, steps S317→S311→S312 or steps S317→S313→S314 in sequence, and then step S84. In step S84, the receive control portion 31 determines whether the PLL circuit 2 locks with the optimal VCO 1 active in step S307. Note that, when the receive control portion 31 executes step S84 immediately after determining the optimal VCO 1, such as when steps S315→S86→S317→S304→S305 are executed in sequence, the PLL circuit 2 locks as a matter of course, and therefore the receive control portion 31 ends the test mode. The receiver then starts the receive mode. After that, the receiver is powered off as required.

[0114] The receiver is powered on again as required. The receive control portion 31 starts the test mode immediately after the power-on, first taking out the VCO number “n_OPT” of the optimal VCO 1 determined last time from the field 101 in the memory 32 and setting the initial value of the VCO number “n” to “n_OPT” (step S81). The receive control portion 31 next sends out Sel_OPT(step S82) to notify the VCO switching circuit 4 of the preceding optimal VCO 1 set in step S81. The receive control portion 31 then sends out N_typ(step S83) to set the dividing ratio of the programmable divider 21.

[0115] After that, the receiver executes steps S317→S304→S305, steps S317→S311→S312 or steps S317→S313→S314 in sequence according to the value of “n_OPT” stored in the field 101, and the receive control portion 31 then determines whether the PLL circuit 2 locks with the preceding optimal VCO 1 active (step S84). Unlike the above case, it is not sure that the PLL circuit 2 reliably locks when the preceding optimal VCO 1 is activated, because its circuit constant may change from the initial constant by secular changes of the IC. That is why step S84 is required. The receive control portion 31 ends the test mode when the PLL circuit 2 locks in S84.

[0116] As described above, according to the receiver of the third embodiment, as in the first embodiment, an optimal VCO 1 is determined. Furthermore, at the time of powering-on the receiver again, when the PLL circuit 2 locks using the preceding optimal VCO 1 active, the receive control portion 31 continues to use this VCO 1. In this way, unlike in the first embodiment, in some cases, the receiver of the third embodiment does not have to execute processing such as writing the status into the first table TA_Sand determining the optimal VCO 1 by comparison of the first table TA_Sand the second table TA_R. This allows reduction in time between power-on of the receiver and the receive mode, as compared with the first embodiment.

[0117] When the PLL circuit 2 does not lock, the receive control portion 31 starts in step S84 the same test mode as that of the first embodiment. However, at this time, it is not required to activate again the VCO 1 with the number corresponding to “n_OPT” stored in the field 101 and determine whether the PLL circuit 2 locks. Therefore, the receive control portion 31 executes step S85 and does not activate the VCO 1 with the above VCO number “n_OPT” this time. This increases the speed of the test mode.

[0118] Described next is a receiver according to a fourth embodiment of the present invention. The structure of the receiver is shown in FIG. 1₁and its description is omitted.

[0119] FIG. 10 is a flow chart showing the procedure of the test mode to be executed by the receiver according to the fourth embodiment. Note that the flow chart of FIG. 10 includes some steps which are the same as those in the flow charts of FIGS. 6 and 8. Therefore, the corresponding steps are provided with the same step numbers as in FIGS. 6 and 8, and their description is simplified. Described below is operation of the receiver based on FIGS. 1 and 10.

[0120] Step S604 of FIG. 10 is the same as step S604 of FIG. 6. That is, when the measured result of the control voltage V_Cobtained from the A/D converter 33 satisfies the above conditional equation (2), the receive control portion 31 determines that the active VCO 1 is the optimal one(step S604). The receive control portion 31 then writes “n_OPT” into the field 101 (refer to FIG. 9) in the memory 32 (step S86). After that, the receiver executes Steps S317→S304→S305, steps S317→S311-S312 or steps S317→S313→S314 in sequence according to the selected VCO 1.

[0121] As in the third embodiment, the receive control portion 31 next checks to determine whether the PLL circuit 2 locks with the determined optimal VCO 1 active (step S84), and ends the test mode. The receiver then starts the receive mode. After that, the receiver is powered off as required.

[0122] The receiver is powered on again as required. The receive control portion 31 executes steps S81 to S83 immediately after the power-on, as in the third embodiment. After that, the receiver executes steps S317→S304→S305, steps S317→S311→S312 or steps S317→S313→S314 in sequence according to the value of “n_OPT” stored in the field 101. The receive control portion 31 then executes step S84 as in the third embodiment, and when determining that the PLL circuit 2 locks, decides to continue to use the preceding optimal VCO for down-conversion.

[0123] As described above, according to the receiver of the fourth embodiment, as in the second embodiment, an optimal VCO 1 is determined at high speed, and furthermore, in the same manner as that in the third embodiment, the time between power-on of the receiver and the receive mode is reduced.

[0124] In step S84, the receive control portion 31 starts the same test mode as in the second embodiment when the PLL circuit 2 does not lock, and the same step S85 in the third embodiment increases the speed of the test mode.

[0125] While the invention has been described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is understood that numerous other modifications and variations can be devised without departing from the scope of the invention.