System for providing electrostatic discharge protection for high-speed integrated circuits

[0002] This is a continuation of application Ser. No. 09/488,940 filed on Jan. 21, 2000.

[0003] 1. Field of the Invention

[0004] The present invention is directed to electrostatic discharge protection for electronic circuits; more particularly, the invention is directed to electrostatic discharge protection for high-speed integrated circuits, i.e., integrated circuits handling signals having frequencies higher than electrostatic discharge transients.

[0005] 2. Background of the Related Art

[0006] Advances in integrated circuit development continue to increase the density of circuit components that can be fabricated in an integrated circuit (IC) chip. In conjunction with this advance in miniaturization, critical dimensions of the IC such as minimum conductor-to-conductor spacing and layer thicknesses also have been reduced. In particular, insulating layers within the IC structure have become thinner, making ICs more susceptible to electrostatic discharge (ESD) pulses. The pulses are passed to the IC circuit from an input or output pin, and if not properly diverted could deliver a brief but highly destructive charge to the IC circuitry.

[0007] As is known in the art, ESD protection circuits can be fabricated in the ICs. Typically, these circuits are disposed on the input and output pads of the ICs and pass normal input signals therethrough while diverting ESD pulses as shown in FIG. 1. Here, an input or output bonding pad 10 of an IC is connected to an internal circuit 20 to be protected from ESD pulses via a conductor 30 (as used herein, “input/output bonding pad” denotes that the bonding pad may be used for receiving input signals, providing output signals, or both). Desired signals pass in one or both directions between the bonding pad 10 and the internal circuit 20. Were the IC to have no ESD protection, an ESD pulse appearing at the bonding pad 10 would be conducted via conductor 30 to the internal circuit 20, possibly damaging or destroying it by, e.g., shorting through one or more oxide layers in the IC. However, ESD protection circuit 40 is activated by the relatively high voltage levels (relative to the IC's internal supply voltage) of the ESD pulses and establishes a low-resistance conductive path between conductor 30 and the ground connection to shunt the ESD pulse away from the internal circuit 20.

[0008] As one of ordinary skill in the art will recognize, in practice most protected circuits are equipped with not only one ESD protection circuit 40 between conductor 30 and system ground or V_ss, but also with another between conductor 30 and a positive source of potential, such as V_DD.

[0009] This allows the ESD pulse to be discharged either through the V_ssor V_DDpad. However, FIG. 1 shows only a single ESD device 40 in the interests of simplicity and ease of explanation.

[0010] A typical ESD device 40 as described above is shown in FIG. 2. Here, an N-channel MOS transistor 50 is connected between conductor 30 and V_ss. A resistor 70 is connected between the gate of transistor 50 and V_ss. A capacitor 60 (which may be a parasitic capacitance of transistor 50 or a separate component) is connected between conductor 30 and the gate of transistor 50. Transistor 50 has a parasitic bipolar mode of operation designated by transistor 50′. The transistor 50 is very wide with a short channel length, e.g., 300 μm wide by 0.5 μm long, to be capable of efficiently shunting the current due to an ESD event (the current due to an ESD event is proportional to the amount of static charge deposited on the IC, and the current is typically between a few tenths of an ampere and a few amperes). By effectively choosing the values of capacitor 60 and resistor 70, the gate of transistor 50 will rise to a voltage of about 1 volt when an ESD event occurs and the voltage on node A rises above a trigger voltage of about 4.0 to 7.5 volts, depending on the IC fabrication technology in use. When the transistor 50 is turned on by such an ESD event, bipolar conduction through transistor 50′ will begin and continue until the voltage on node A falls below the trigger voltage level.

[0011] While this arrangement is workable in some applications, the ESD device 40 typically presents a relatively large capacitive loading 40′ (on the order of a few picofarads) to the bonding pad 10 and internal circuit 20. This limits the maximum frequency of desired signals which can be exchanged between bonding pad 10 and internal circuit 20.

[0012] Prior art attempts at ameliorating this effect have reduced the size of the ESD protection transistor to lessen the capacitive loading to the IC; however, this necessarily reduces the level of protection afforded by the ESD protection circuit. As the frequency of signals processed by the IC increases, the ESD protection transistor becomes too small to be effective.

[0013] It is an object of the present invention to overcome the above shortcomings of the prior art.

[0014] It is another object of the present invention to provide a circuit for ESD protection which minimizes the capacitive loading on the inputs and outputs of the circuit which it protects.

[0015] It is a further object of the present invention to provide a circuit for ESD protection which is particularly useful with circuits processing high frequency signals.

[0016] It is still another object of the present invention to provide a circuit for ESD protection which provides effective ESD protection in high-frequency environments.

[0017] It is yet another object of the present invention to provide a circuit for ESD protection which provides effective ESD protection for circuits processing signals at frequencies above those of ESD pulses.

[0018] The above objects are achieved according to a first aspect of the present invention by providing an ESD protection circuit which uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while isolating its capacitive load on the main circuit when presented with desired signals which are higher in frequency than ESD pulses. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires.

[0019] These and other objects, features and advantages of the present invention are better understood by reading the following detailed description of the preferred embodiment, taken in conjunction with the accompanying drawings, in which:

[0020] FIG. 1 shows a basic ESD-protected integrated circuit according to the prior art;

[0021] FIG. 2 is a schematic diagram of a typical ESD protection circuit used in the circuit of FIG. 1;

[0022] FIG. 3 shows an ESD-protected integrated circuit according to a first preferred embodiment of the present invention as used in an ESD protection scheme to ground;

[0023] FIG. 4 is a graph showing impedance characteristics of an inductor in the first embodiment with respect to ESD pulses and higher-frequency desired signals;

[0024] FIG. 5 shows an effective circuit of the first embodiment;

[0025] FIG. 6 shows resonance characteristics of the circuit of the first embodiment;

[0026] FIG. 7 shows a planar spiral inductor suited to fabrication in an integrated circuit for use in the first embodiment;

[0027] FIG. 8 is a cross-sectional diagram of the inductor of FIG. 7 taken along line VIII-VIII therein;

[0028] FIG. 9 shows an ESD-protected integrated circuit according to a variation of the first embodiment as used in an ESD protection scheme to both the power supply (V_DD) and ground (V_ss);

[0029] FIG. 10 shows an ESD protection circuit according to another variation of the first embodiment as used in an ESD protection scheme to both V_DDand V_ss;

[0030] FIG. 11 shows an ESD protection circuit according to a second preferred embodiment of the present invention as used in an ESD protection scheme to both the power supply and ground;

[0031] FIG. 12 shows an effective circuit of the circuit of the second embodiment;

[0032] FIG. 13 shows an ESD protection circuit according to a third preferred embodiment of the present invention as used in an ESD protection scheme to the ground; and

[0033] FIG. 14 shows implementation of the inductor in the third embodiment.

[0034] A basic ESD-protected circuit 100 is shown in FIG. 3. This circuit is similar to the prior art circuit of FIG. 1 in that it includes a bonding pad 10 connected to an internal circuit 20 via a conductor 30, with an ESD protection circuit 40 between the conductor 30 and V_ss. However, in the first embodiment, an inductor 110 is connected in series between the conductor 30 and the ESD protection circuit 40 via another conductor 35.

[0035] Collectively, the inductor 110 and the ESD protection circuit 40 form an ESD protector. It should be noted that although FIG. 3 shows an ESD protector having the inductor 110 connected to the conductor 30 and the ESD protection circuit 40 connected to V_ss, the invention is not so limited, and the ESD protector may have an “inverted” configuration in which the ESD protection circuit 40 is connected to the conductor 30 and the inductor 110 is connected to V_ss.

[0036] As shown in FIG. 4, the impedance of an inductor is directly proportional to the frequency of the signal passing therethrough. Thus, through proper selection of the inductance of inductor 110, it will appear as a low-impedance link between conductor 30 and ESD protection circuit 40 at relatively low frequencies such as those of ESD pulses, and as a high-impedance link between conductor 30 and ESD protection circuit 40 at relatively high frequencies such as those of signals desired to be processed or output by the internal circuit 20. In this way, the inductor 110 effectively acts as a “switch”, connecting conductor 30 to ESD protection circuit 40 and allowing the protection circuit 40 to perform its shunting function when the inductor 110 is presented with a relatively low frequency pulse such as an ESD pulse, and disconnecting conductor 30 from ESD protection circuit 40 to effectively eliminate the capacitive load of the protection circuit 40 when the inductor 110 is presented with a relatively high frequency pulse such as signals which are desired to be processed or have been processed by the internal circuit 20.

[0037] For example, consider an ESD-protected circuit on an IC 100 according to the first embodiment which processes high-frequency radio waves. In this case, the typical frequency of a desired signal might be on the order of several gigahertz. In contrast, the highest significant frequency component in an ESD pulse is typically on the order of 100 MHz. In this case, the value of the inductor 110 can be selected to pass signals at 100 MHz and below to the ESD protection circuit 40 while blocking signals at, e.g., 1 GHz and higher from reaching the ESD protection circuit 40.

[0038] The method for selection of the proper inductance for use in the embodiment will be understood as follows. The impedance of the circuit 100 as seen by signals applied to input/output pad 10 can be modeled by the circuit of FIG. 5. Setting L as the inductance of inductor 110, C_pas the capacitance of the parasitic capacitor 40′ formed by ESD protection circuit 40, and C_inas the effective capacitance of the internal circuit 20 (depicted in FIG. 5 as a single transistor for simplicity), with ω being the angular frequency of the input signal, the admittance of the inductor 110 is $\frac{1}{\mathrm{j\omega }L},$

[0039] the admittance of the parasitic capacitor 40′ is jωC_p, and the admittance of the internal circuit 20 capacitance is jωC_in. Then, the admittance Y looking in from input/output pad 10 is $\begin{array}{cc}\begin{array}{c}Y=\mathrm{j\omega }{C}_{\mathrm{in}}+\mathrm{j\omega }{C}_p//\frac{1}{\mathrm{j\omega }L}\\ =\mathrm{j\omega }{C}_{\mathrm{in}}+\frac{\mathrm{j\omega }{C}_p\frac{1}{\mathrm{j\omega }L}}{\mathrm{j\omega }{C}_p+\frac{1}{\mathrm{j\omega }L}}\\ =\mathrm{j\omega }{C}_{\mathrm{in}}+\frac{\mathrm{j\omega }{C}_p}{1-{\omega }^2{\mathrm{LC}}_p}\\ =\mathrm{j\omega }\left(C_{\mathrm{in}}+\frac{C_p}{1-{\omega }^2{\mathrm{LC}}_p}\right)=\mathrm{j\omega }{C}_{\mathrm{eff}}\mathrm{where}\\ C_{\mathrm{eff}}=C_{\mathrm{in}}+\frac{C_p}{1-{\omega }^2{\mathrm{LC}}_p}·\end{array}& \left(1\right)\end{array}$

[0040] From this, one can see that a plot of the effective capacitance C_effversus frequency ω has a shape similar to that shown in FIG. 6. As can be seen in the Figure, there is a resonance at a frequency ω_Rwhich causes the denominator of Equation 1 to go to 0, i.e.,

[0041] 1−ω_R²LC_p=0

[0042] or $\begin{array}{cc}{\omega }_R=\frac{1}{\sqrt{{\mathrm{LC}}_p}}& \left(2\right)\end{array}$

[0043] One can also see that on the low side of the resonance frequency ω_R, the effective capacitance C_effapproaches C_eff=C_p+C_in, and on the high side of the resonance frequency ω_R, the resonance frequency C_effasymptotically approaches the value C_eff=C_in. Since the parasitic capacitance C_pof the ESD protection circuit 40 is generally a factor of five or more greater than that of the effective input capacitance of the internal circuit 20, e.g., about 3 pF versus 0.5 pF, it is preferable that the inductance L of the inductor 110 is selected so that high frequency signals coHF to be processed by the internal circuit 20 fall well to the right of ω_Rto minimize the effective capacitive loading; that is, ω_R>>ω_HF; practically, say,

[0044] ω_HF=5ω_R  (3)

[0045] so that C_eff→C_in.

[0046] For a desired frequency band centering at ω_HF=2π(2.5×10⁹) radisec and C_p=3 pF, for example, from Equations (3) and (2),

[0047] ω_HF=5ω_R

[0048] $2\pi \times 2.5\times {10}^9=5\frac{1}{\sqrt{L\left(3\times {10}^{-12}\right)}};$

[0049] thus,

[0050] To make use of a smaller on-chip inductor to conserve space, a lesser multiple such as ω_HF=3 ω_Rmight be used, in which case L=12.2 nH.

[0051] The inductor 110 can be fabricated in the IC 100 in several ways. One is to use the inherent inductance of chip bonding wires, as will be described in greater detail below. Another is to form an inductor in the IC 100 itself. FIG. 7 shows the top view of an on-chip planar spiral inductor of this type, and FIG. 8 is a cross-section of the inductor 110 taken through the thickness of the IC 100. By selecting the number N of inductor turns, the width w of the inductor trace 115, the thickness t of the inductor trace 115, the space s between inductor turns, as well as the inner diameter id and the outer diameter od of the inductor, an appropriate inductance can be selected for inductor 110 to match the loading capacitance of the ESD protection circuit 40. Further details may be found in Yue, “On-Chip Spiral Inductors for Silicon-Based Radio-Frequency Integrated Circuits”, Technical Report No. ICL 98-087, Stanford University PhD. Dissertation, incorporated herein by reference.

[0052] As shown in FIG. 9, the conductor 35 is a dedicated conductor connecting the inductor 110 to the ESD protection circuit 40; however, to minimize the size and wiring complexity of the circuit, the conductor 35 may be a system bus line such as the V_DDline or any other similar connection higher in potential than V_ss.

[0053] Similar to the prior art circuit shown in FIG. 1, the version of the first embodiment shown in FIG. 3 provides ESD protection between the input/output pad 10 and ground. A more typical implementation of the embodiment is shown in FIG. 9, where as before in an IC 100a, a bonding pad 10 is connected to an internal circuit 20 to be protected by a conductor 30, with an ESD protector formed by inductor 110 and ESD protection circuit 40 in series between the conductor 30 and V_ss. This version of the embodiment, however, also includes another ESD protector formed by inductor 110aconnected to an ESD protection circuit 40a(presenting a capacitive load 40a′), the series combination of which connects the conductor 30 to V_DD. Thus, while the ESD protector formed by the combination of inductor 110 and ESD protection circuit 40 can protect internal circuit 20 from ESD pulses with respect to V_ss, the ESD protector formed by the combination of inductor 110aand ESD protection circuit 40 a can protect internal circuit 20 from ESD pulses with respect to V_DD. In both cases, higher-frequency desired signals are passed to the internal circuit 20.

[0054] Calculation of appropriate inductances L for the inductors 110 and 110aare substantially similar to the process described above.

[0055] In another variation of the first embodiment shown in FIG. 10, in an IC chip 100bthe second ESD protection circuit 40 a is connected to the inductor 110 of the ESD protector not at node A on its bonding pad-internal circuit side; rather, the second ESD protection circuit 40 a is connected to the inductor 110 on the same side as the first ESD protection circuit 40. This arrangement has an effect similar to the above in that when the ESD pulse appears between the bonding pad 10 and V_ss, it is transmitted via conductor 30 through inductor 110 and ESD protection circuit 40 to V_ss; when the ESD pulse appears between the bonding pad 10 and V_DD, it is transmitted via conductor 30 through inductor 110 and ESD protection circuit 40ato V_DD. Again, higher-frequency desired signals are passed to the internal circuit 20. In this way, the variation of the first embodiment shown in FIG. 10 can achieve effects similar to those provided by the variation shown in FIG. 9 while requiring the use of only one inductor 110.

[0056] The calculation of an appropriate inductance value for inductor 110 is similar to that of the first embodiment above; however, when determining the effective impedance looking in from the input/output pad 10, the parasitic capacitance 40a′ of the ESD protection circuit 40 a will appear in parallel with the parasitic capacitance 40′ of the ESD protection circuit 40, resulting in $C_{\mathrm{eff}}=\frac{2C_p}{1-2{\omega }^2{\mathrm{LC}}_p}·$

[0057] FIG. 11 shows a third preferred embodiment of the present invention in which the ESD protection circuits 40 and 40aare connected directly to conductor 30, and thus to input/output pad 10 and internal circuit 20, rather than connecting through inductor 110. Inductor 110 is connected to conductor 30 and to a voltage reference VRF which may be at any potential other than V_ss.

[0058] Selection of the inductance of inductor 110 is developed as follows. Similar to the first embodiment, the effective circuit seen from the input/output pad 10 of the third embodiment is shown in FIG. 12 (in the Figure, V_REFand V_ssare shown as high-frequency grounds). The admittance of the circuit, then, is $Y=\mathrm{j\omega }{C}_{\mathrm{in}}+\mathrm{j\omega }{C}_p+\mathrm{j\omega }{C}_p+\frac{1}{\mathrm{j\omega }L}=\mathrm{j\omega }\left(C_{\mathrm{in}}+2C_p-\frac{1}{{\omega }^{2}L}\right)=\mathrm{j\omega }{C}_{\mathrm{eff}}$

[0059] Therefore, for this embodiment $\begin{array}{cc}{C}_{\mathrm{eff}}=C_{\mathrm{in}}+2C_p-\frac{1}{{\omega }^{2}L}& \left(4\right)\end{array}$

[0060] and the parasitic load of the ESD protection circuit can be minimized by attempting to choose a value for L which cancels out the C_pcomponent. That is, assuming the values and frequencies of the first embodiment apply here, $2\left(3\times {10}^{-12}\right)=\frac{1}{{\left(2.5\times {10}^9\right)}^{2}L}$

[0061] or L=26.7 nH.

[0062] It should be noted that although in the first embodiment one objective in choosing the inductance L was to place the high frequency signals to be processed ω_HFfar to the right of the resonant frequency ω_Ron the graph of FIG. 6, this embodiment does not exhibit the same type of transfer characteristic, the same consideration is not present. Rather, as noted above, the main consideration is to choose L to cancel the parasitic capacitances C_pof the ESD protection circuits 40 and 40a.

[0063] FIG. 13 shows a third preferred embodiment of the present invention which is particularly suited to implementation of the inductor 110 using bonding wire inductance as mentioned above. Here, inductor 110 is not connected between the conductor 30 and the ESD protection circuit 40; rather, it is connected between the bonding pad 10 and another bonding pad 10aon the IC chip 100d. The bonding pad 10ais connected via a conductor 30ato the ESD protection circuit 40.

[0064] In this embodiment, when an ESD pulse appears at bonding pad 10, it is transmitted through inductor 110, bonding pad 10aand conductor 30ato the ESD protection circuit 40 which 20 shunts the pulse to V_ss. In this way, the impedance of the inductor 110 can compensate for the characteristic capacitance 40′ of the ESD protection circuit 40 while passing higher frequency desired signals to the internal circuit 20 generally as described above in connection with the first embodiment.

[0065] Similarly, if an ESD pulse appears at bonding pad 10a, it will be shunted to V_ssby the ESD protection circuit 40; however, inductor 110 will not be included in this signal path, and the capacitance 40′ of ESD protection circuit 40 will not be compensated for ESD pulses appearing on bonding pad 10a. Thus, in this embodiment bonding pad 1 Oa should be used for transmitting and receiving desired signals which have lower frequencies and for which such compensation is not necessary in connection with circuit 20awhich may or may not be part of the same functional circuit as circuit 20. Additionally, circuit 20aneed not be provided at all.

[0066] Calculation of an appropriate inductance for the inductor 110 is substantially the same as in the first embodiment described above.

[0067] FIG. 14 shows another way of implementing the embodiment of FIG. 13 using bonding wire inductors. Here, the inductor 110′ connecting bonding pads 10aand 10bis primarily formed by two bonding wires 85 and 90 connected to an IC package pin 95. One bonding wire 90 is connected to bonding pad 10a, while the other bonding wire 85 is connected to an auxiliary bonding pad 10b. The auxiliary bonding pad 10bis electrically connected to bonding pad 10 by an on-chip interconnection 80. In this way, the inherent inductance of the bonding wires 85 and 90 (typically 1 nH per millimeter of wire) provide the necessary inductance to form inductor 110′ compensating for the capacitance of ESD protection circuit 40. As above, circuit 20amay or may not be part of the same functional circuit as circuit 20 and need not even be used.

[0068] The use of inductive bonding wires instead of an on-chip inductor to form the inductor 110′ provides lower series resistance for the inductor and consequent lower loss at radio frequencies. It also consumes less space on the IC chip 100d. However, unlike the on-chip inductor, the bonding wire arrangement requires additional bonding pads (for the auxiliary bonding pads 10aand 10b) and sometimes additional package pins. Also, it should be noted that although the bonding wire arrangement has been disclosed in connection with this embodiment, one of ordinary skill in the art will recognize that it is readily applicable to the other embodiments disclosed herein. Further, one of ordinary skill will readily recognize that this embodiment may be implemented using on-chip inductors as well. Additionally, implementations other than those above are possible; for example, the embodiment of FIGS. 13 and 14 may be equipped with an additional ESD protection circuit connected to conductor 30a, and the embodiment of FIG. 11 can be used with only one ESD protection circuit 40.

[0069] The present invention has been described above in connection with a preferred embodiment thereof, however, this has been done for purposes of illustration only, and the invention is not so limited. Indeed, variations of the invention will be readily apparent to those skilled in the art and also fall within the scope of the invention.