Low noise and low offset bipolar input amplifiers

[0002] This application claims priority to U.S. Provisional Patent Application No. 60/220,234 to Ochi, filed Jul. 21, 2000, which is hereby incorporated by reference herein.

[0003] The present invention relates to input amplifiers, and more particularly, to input amplifiers that have low noise and low offset output signals and are compatible with standard submicron CMOS processes.

[0004] An input amplifier is a type of amplifier that may be used as an input stage for circuit applications such as an operational amplifier or a comparator. FIG. 1 illustrates prior input amplifier 10 comprising transistors made from standard submicron CMOS processes. Input voltage V_INis applied to the bases of PNP bipolar junction transistors (BJTs) Q_L1and Q_L2. BJTs Q_L1and Q_L2comprise a differential pair amplifier, with a bias current (equal to I) from current source I1 and a single ended output at the gate of n-channel MOSFET M3. The emitters of BJTs Q_L1and Q_L2are coupled to a current mirror circuit comprising n-channel MOSFETs M1 and M2. The drain of M2 is coupled to the gate of transistor M3. Transistor M3 is a common-source amplifier that provides voltage gain to the input signal to produce output voltage V_OUTat the drain of M3. Transistor M3 is biased from current source I2, at a current equal to I.

[0005] FIGS. 3A-3B illustrates top down and cross sectional layout views, respectively, of PNP BJTs Q_L1and Q_L2. BJTs Q_L1and Q_L2are each lateral PNP BJTs that may be fabricated using standard submicron CMOS process steps that are used to fabricate p-channel MOSFETs. Each of BJTs Q_L1and Q_L2includes a parasitic vertical PNP BJT, Q_S1and Q_S2, respectively, as shown in FIGS. 1 and 3A-3B. The lateral PNP BJTs (Q_L1and Q_L2) and their parasitic vertical PNP BJTs (Q_S1and Q_S2) share the same base and emitter semiconductor regions, but have different collector semiconductor regions as shown in FIGS. 3A-3B. Lateral BJTs Q_L1and Q_L2each have a collector terminal coupled to a P+ collector region 32 that surrounds a P+ emitter region 31 as shown in FIGS. 3A-3B. Vertical BJTs Q_S1and Q_S2each have a collector terminal coupled to a P+ region 33 that is tied to the P-substrate region of the device, which is grounded. FIG. 3C illustrates a schematic of the lateral and vertical PNP BJTs of FIGS. 3A-3B.

[0006] Referring to FIG. 1, a current equal to I/2 flows through each of transistors Q_L1and Q_L2when V_INequals zero, assuming that no current flows into transistors Q_S1, and Q_S2. Transistor M3 is sized by design so that it has a channel width-to-length (W/L) ratio that is 2 times the channel W/L ratio of n-channel MOSFETs M1 and M2. The W/L ratio of transistor M3 relative to the W/L ratio of transistors M1 and M2 determnines the current through transistor M3. Thus, when I/2 flows through each of transistors M1 and M2, a current equal to I flows through M3, causing V_OUTto be accurate with a low signal-to-noise ratio.

[0007] However, a significant parasitic current i_EQS1and i_EQS2does flow into the emitters of parasitic transistors Q_S1and Q_S2. The parasitic current causes the current through transistors M1 and M2 to be less than I/2. Because the current through transistor M3 is still I, V_DSof M1 and V_DSof M2 are no longer equal and the circuit is unbalanced, causing an offset voltage with respect to the amplifier inputs or an inaccurate V_OUT. Therefore, transistors Q_S1, and Q_S2cause prior art amplifier 10 to have a systematic offset voltage at V_OUT.

[0008] It would therefore be desirable to provide a CMOS compatible input amplifier that improves upon prior art input amplifier 10 by reducing output offset to provide a more accurate amplified signal V_OUT.

[0009] The present invention comprises an input amplifier circuit that provides a low input offset voltage amplified output signal. Input amplifiers of the present invention include a differential pair of transistors that may be fabricated using standard CMOS process steps. Each transistor in the differential pair includes a parasitic transistor that reduces the current through the associated differential pair transistor.

[0010] The differential pair has a single ended output coupled to the input of a second amplifier such as a MOSFET. The current through the second amplifier determines the output signal V_OUT. The second amplifier is coupled to a third transistor which also includes a parasitic transistor. The third transistor provides a bias current to the second amplifier that is proportional to the current through the differential pair transistors. By providing a proportional current to the second amplifier, input amplifiers of the present invention output an accurate, low input offset voltage amplified signal V_OUT.

[0011] FIG. 1 is a schematic of a prior art input amplifier;

[0012] FIG. 2 is a schematic of a low input offset voltage, CMOS compatible input amplifier in accordance with the principles of the present invention;

[0013] FIGS. 3A-3B illustrate top down and cross sectional views of a lateral and vertical PNP bipolar junction transistors fabricated using standard submicron CMOS process steps; and

[0014] FIG. 3C illustrates a schematic of a lateral and vertical PNP bipolar junction transistors fabricated using standard submicron CMOS process steps.

[0015] Input amplifier 20 shown in FIG. 2 is an embodiment of the present invention. Input amplifier 20 includes differential pair lateral PNP BJTs Q_L1and Q_L2, parasitic vertical PNP BJTs Q_S1, and Q_S2, bias current sources I1 and I2, current mirror MOSFETs M1 and M2, and output MOSFET M3, as discussed above with respect to prior art input amplifier 10.

[0016] Input amplifier 20 also includes lateral PNP bipolar transistor Q_L3as shown in FIG. 2 and its associated parasitic vertical PNP bipolar transistor Q_S3. Lateral BJT Q_L3may be formed using standard submicron CMOS process steps that are used to form p-channel MOSFETs. Top down and cross sectional layout views of an embodiment of transistors Q_L3and Q_S3are shown in FIGS. 3A-3B. Transistors Q_L3and Q_S3share the same base and emitter semiconductor regions, but have different collector semiconductor regions. The collector of vertical PNP BJT Q_S3is tied to the P-substrate, which is grounded. The collector of lateral PNP BJT Q_L3is coupled to the drain of MOSFET M3 and V_OUT. The gate terminals of vertical PNP BJTs Q_S1, Q_S2, and Q_S3are biased so that the parallel PMOS devices are kept off.

[0017] The forward current gain β of a bipolar junction transistor equals the collector current divided by the base current (β=I_C/I_B). The forward current gain β varies slightly with the collector-emitter voltage V_CEacross the BJT in forward active mode. The collector-emitter voltages across transistors Q_S1and Q_S2are the same, and therefore, the current gain β of transistors Q_S1and Q_S2are the same. The collector-emitter voltages across transistors Q_L1and Q_L2are substantially the same, and therefore, the current gain β of transistors Q_L1and Q_L2are substantially the same.

[0018] It can be assumed that V_CEof transistor Q_L3is substantially the same as V_CEof transistor Q_L2, and that V_CEof transistor Q_S3is substantially the same as V_CEof transistor Q_S2, as can be seen in FIG. 2. Therefore, the ratio of the current gain of transistor Q_L3to the current gain of transistor Q_S3is the substantially equal to the current gain ratio of transistor Q_L2to transistor Q_S2, as shown in the following equation: $\begin{array}{cc}\frac{{\beta }_{\mathrm{QL3}}}{{\beta }_{\mathrm{QS3}}}\approx \frac{{\beta }_{\mathrm{QL2}}}{{\beta }_{\mathrm{QS2}}}& \left(1\right)\end{array}$

[0019] Any differences in V_CEbetween Q_S3and Q_S2as well as differences in V_CEbetween Q_L3and Q_L2are generally small enough so as not to introduce a significant error term into the circuit performance such that equation (1) generally applies. A cascode circuit may be coupled in series between Q_L2and M2 to independently adjust the collector voltage of Q_L2so that the β ratios shown in equation (1) are as close as possible.

[0020] In circuit 20, both current sources I1 and I2 provide a bias current equal to I. A first portion of current I from current source I2 flows through transistor Q_L3and a second portion of current I from current source I2 flows through transistor Q_S3. Transistors Q_L3and Q_S3have base-emitter junction areas that are two times the base-emitter junction areas of transistors Q_L1/Q_S1and transistors Q_L2/Q_S2in the embodiment of FIG. 2. Transistors Q_L3and Q_S3have the same current density as transistors Q_L2and Q_S2, respectively, as long as their current gains 13 satisfy equation (1).

[0021] As long as equation (1) remains valid, the current through transistor Q_L3is substantially equal to two times the current through transistor Q_L1and two times the current through transistor Q_L2, because a proportional amount current I is diverted through parasitic vertical transistors Q_S1/Q_S2/Q_S3. Therefore, even when the current i_EQL1and i_EQL2through transistors Q_L1and Q_L2varies from I/2, the current i_EQL3through transistor Q_L3is proportionally larger than i_EQL1and i_EQL2, according to the base-emitter junction ratios of transistors Q_L1/Q_L2/Q_L3.

[0022] The base currents i_bQS3and i_bQL3flow out of the bases of transistors Q_S3and Q_L3and into the drain of transistor M3. Base currents i_bQS3and i_bQL3introduce an error term that causes some distortion in output signal V_OUT. However, the distortion in V_OUTintroduced by these base currents is small if the current gain β of transistors Q_L3and Q_S3is relatively high during forward active mode (e.g., 100). The lateral PNP BJT shown in FIGS. 3A-3B, for example, typically has a current gain in the range of 100-200. The vertical PNP BJT shown in FIGS. 3A-3B, for example, typically has a current gain of 500.

[0023] Input amplifier circuit 20 provides an amplified output signal V_OUTat the drain of M3 that has a low input offset voltage, a higher signal-to-noise ratio, and that is more accurate and more predictable than the output signal of prior art amplifier circuit 10. Input amplifier 20 also has a more predictable gain, which makes it easier to compensate.

[0024] In further embodiments of the present invention, the currents of current sources I1 and I2 may have any suitable ratio besides one-to-one. For example, current source I2 may output a current that is 100 times the current of current source I1. In this embodiment, M3 has a channel W/L ratio that is ₂₀₀times the W/L ratio of M1 and M2. Also, Q_L3has a base-emitter junction area that is 200 times the base-emitter junction area of transistors Q_L1and Q_L2.

[0025] In another embodiment of the present invention, PNP BJTs Q_L1, Q_L2, and Q_L3may be replaced with NPN bipolar junction transistors. In this embodiment, each of the three NPN BJTs have a parasitic NPN bipolar junction transistor that shares the same base and emitter semiconductor regions, but have different collector regions. The emitters of the NPN BJTs in the differential pair are coupled to current source I1, and the emitter of the third NPN BJT is coupled between M3 and current source I2.

[0026] Input amplifiers may also have a differential pair amplifier with two n-channel or two p-channel field effect transistors (FETs) (e.g., MOSFETs fabricated using Gallium Arsenide technology) instead of two bipolar junction transistors. Thus, in a further embodiment of the present invention, BJTs Q_L1and Q_L2may be replaced with two n-channel or two p-channel FETs. In a differential pair with two p-channel FETs, each p-channel FET in the differential pair would include a parasitic p-channel FET that shares its gate and source regions, but has a different drain region. The sources of a differential pair of p-channel FETs are coupled to I1.

[0027] In a differential pair with two n-channel FETs, each n-channel FET in the differential pair would include a parasitic n-channel FET that shares its gate and source regions, but has a different drain region. The sources of a differential pair of n-channel FETs are coupled to I1.

[0028] The parasitic FETs draw current away from current mirror M1/M2. To mitigate this problem, an additional FET can be coupled between current source I2 and M3. The source of an additional n-channel FET is coupled to I2, and the source of an additional p-channel FET is coupled to 12. The additional FET also has a parasitic FET which draws current away from M3 in the same proportion that the parasitic FETs in the differential pair draw current away from M1 and M2. The additional FET has a channel W/L ratio that is sized with respect to the W/L of the FETs in the differential pair according to the current ratio current sources I1 and I2 and the sizing of transistor M3 relative to transistors M1 and M2, as with the embodiment of FIG. 2.

[0029] While the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosure, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope of the invention as set forth. Therefore, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments and equivalents falling within the scope of the claims.