Temperature-dependent reference generator

[0002] The present invention relates generally to reference generator circuits, and more particularly relates to a temperature-dependent reference generator suitable for large temperature-variation applications.

[0003] In the design of various analog and digital circuits, it is often necessary to establish a temperature-independent bias reference within the circuit. This stable bias reference can be either a voltage or a current, although voltage references are most often employed because they are generally easier to interface with other functional sub-circuits. In the case of a voltage reference, the primary emphasis is not on low output impedance, as it is in the case of a voltage source, but rather emphasis is on the temperature stability of the voltage level.

[0004] The basic principle of temperature compensation typically involves the use of two temperature-dependent sources, each source having a predictable and opposite polarity temperature drift. One or both sources are then scaled by a temperature-independent scale factor such that when the two temperature-dependent sources are added together, the effects of the two opposite polarity temperature drifts are made to substantially cancel. The resulting reference source will thus ideally exhibit a nominally zero temperature coefficient (TC) voltage or current level.

[0005] Current source circuits having an output which is proportional to absolute temperature (I_PTAT) are well known and widely used for temperature compensation and temperature sensing to obtain either temperature-dependent or temperature-independent biasing. However, since I_PTATis only proportional to absolute temperature, the maximum current variation that can be generated at any given temperature T is ΔT/T_nom, where ΔT is the temperature range of operation, in degrees Kelvin (K), and T_nomis the nominal operating temperature in degrees K. Thus, for example, at 300 degrees K, an I_PTATCurrent source can have a maximum current variation of 33% in a range from 300 degrees K to 400 degrees K. In many temperature compensation and temperature sensing applications, however, a current variation greater than the absolute temperature variation is required.

[0006] Accordingly, there exists a need for a reference source capable of providing an output having a temperature variation greater than the absolute temperature variation.

[0007] The present invention provides a temperature-dependent reference generator having an output variation greater than an absolute temperature variation. Using the reference generator described herein in accordance with the present invention, circuits having a relatively high temperature dependency can be easily compensated. Moreover, the reference generator is suitable for temperature sensing with large temperature dependency without requiring a high supply voltage.

[0008] In accordance with one aspect of the invention, a reference generator having a temperature-dependent output variation that is greater than an absolute temperature variation includes a first source and a second source, the first source generating an output proportional to absolute temperature (PTAT). The second source generates an output having a temperature coefficient less than or equal to zero. The reference generator further includes a subtraction circuit coupled to the first and second sources, the subtraction circuit subtracting the output of the second source from the PTAT output and generating the temperature-dependent output having a variation greater than an absolute temperature variation.

[0009] In accordance with another aspect of the invention, a method of generating a temperature-dependent reference output having a variation greater than an absolute temperature variation comprises the steps of generating a first output having a variation that is proportional to absolute temperature (PTAT) and generating a second output, the second output having a temperature coefficient that is less than or equal to zero. The method further includes the step of subtracting the second output from the first output to generate the temperature-dependent reference output having a variation greater than an absolute temperature variation.

[0010] These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0011] FIG. 1A is a graphical representation illustrating a current proportional to absolute temperature (PTAT) and a temperature-independent current, in accordance with one aspect of the invention.

[0012] FIG. 1B is a graphical representation illustrating an offset PTAT current corresponding to a subtraction of the temperature-independent current from the PTAT current in FIG. 1A, in accordance with the present invention.

[0013] FIG. 2 is a schematic diagram illustrating a temperature-dependent reference source, formed in accordance with one aspect of the present invention.

[0014] FIG. 3A is a graphical representation illustrating a PTAT current and a negative temperature coefficient current, in accordance with another aspect of the invention.

[0015] FIG. 3B is a graphical representation illustrating an offset PTAT current corresponding to a subtraction of the negative temperature coefficient current from the PTAT current in FIG. 3A, in accordance with the present invention.

[0016] FIG. 4 is a schematic diagram illustrating a temperature-dependent reference source, formed in accordance with another aspect of the present invention.

[0017] The present invention will be explained below in the context of an illustrative temperature-dependent current reference circuit. However, it should be understood that the present invention is not limited to any particular type of reference circuit. Rather, the invention is more generally applicable to any suitable reference circuit in which it is desirable to generate an output having a variation greater than an absolute temperature variation. Moreover, although implementations of the present invention are described herein using npn bipolar junction transistor (BJT) devices and p-type metal oxide semiconductor (MOS) devices, it is to be appreciated that the present invention is not limited to such devices, and that other suitable devices, such as, but not limited to, pnp BJT devices and/or n-type MOS devices, may be similarly employed, with or without modifications to the circuit, as understood by those skilled in the art.

[0018] A current proportional to absolute temperature, I_PTAT, may be expressed as I_PTAT=aT, where a represents a temperature coefficient and T represents absolute temperature in degrees Kelvin (° K.). A change in current proportional to absolute temperature, ΔI_PTAT, with respect to a given nominal current, I_nom, may be expressed as a ratio $\frac{\Delta I_{\mathrm{PTAT}}}{I_{\mathrm{nom}}}=\frac{\Delta T}{T_{\mathrm{nom}}},$

[0019] where ΔT represents an operational temperature range (in ° K.) and T_nomrepresents nominal temperature (in ° K.). In order to obtain a current variation (ΔI/I_nom) which is greater than the absolute temperature variation (ΔT/T_nom), a current source may be formed, in accordance with the invention, which includes an offset temperature coefficient to generate an output current I_OUT=I_PTAT−I₀, where I₀is a current having a temperature coefficient less than or equal to zero.

[0020] FIG. 1A depicts a graph of current versus temperature, in degrees K, illustrating a current proportional to absolute temperature (I_PTAT) superimposed on the same axis as a temperature-independent constant current having a value I₀. As shown in FIG. 1A, by way of example only, current I_PTAThas a value of I₁at 300° K. and I₂at 400° K. Let ΔI_PTAT=I₂−I₁represent the absolute value of current variation over the temperature range of 300° K. to 400° K. In the example of FIG. 1A, the current value of I_PTATis equal to I₀at 200° K. With reference now to FIG. 1B, an offset current proportional to absolute temperature, I_OPTAT, is graphically displayed in terms of output current I_OUTvalue verses temperature, where I_OUT=I_PTAT−I₀, as previously stated. As shown in FIG. 1B, by way of example only, current I_OPTAThas a value of zero (which corresponds to I_PTAT−I₀) at 200° K., I₃at 300° K. and I₄at 400° K., where I₃=I₁−I₀and I₄=I₂−I₀. It can be easily shown that although the relative quantities |I₂−I₁| and |I₄−I₃| are equal, the current variation (ΔI/I_nom) of I_OPTATwill be greater than the current variation of I_PTATsince, by definition, the value of I_OPTATwill be less than the value of I_PTATfor any given temperature. For example, with reference to FIG. 1A, the current variation of I_PTATin the temperature range of 300° K. to 400° K. will only be 33 percent. By contrast, the current variation of I_OPTATin the same temperature range will be approximately 100 percent, depending upon the value of the constant current I₀.

[0021] FIG. 2 illustrates a circuit for implementing a temperature-dependent reference having an output variation greater than the absolute temperature variation, formed in accordance with one aspect of the invention. The illustrative reference circuit 200 includes a proportional to absolute temperature (PTAT) current source 202, a constant current source 204 and a subtraction circuit 206 operatively coupled to the PTAT current source 202 and the constant current source 204 for generating the temperature-dependent output current I_OPTAT.

[0022] The PTAT current source 202 may be implemented as at least a portion of a bandgap reference circuit. The principle of the bandgap reference is well known and will therefore only be discussed briefly herein. A core of the bandgap reference circuit relies on two BJT transistors Q1 and Q2 (or, alternatively, two groups of transistors) operating at different current densities. This difference in current density will cause a difference between a base-emitter voltage (V_BE) of the two transistors Q1, Q2. Transistor Q2 is preferably connected in a diode configuration (i.e., base and collector terminals coupled together), and the base terminals of each transistor Q1, Q2 are connected together at node 208. An emitter terminal of transistor Q2 is connected to a negative voltage supply, which may be ground. An emitter terminal of transistor Q1 is coupled to ground through a series-connected resistor R1.

[0023] A collector current flowing through transistor Q1 is ideally made equal to a collector current flowing through transistor Q2 by way of, for example, a simple current mirror comprising a pair of p-type metal-oxide-semiconductor (MOS) devices M1 and M2 operatively coupled to transistors Q1 and Q2, respectively, each transistor M1, M2 having a predetermined width-to-length (W/L) ratio associated therewith. Other suitable current mirror or biasing arrangements are similarly contemplated by the present invention, as will be understood by those skilled in the art. In the illustrative reference circuit 200, the current mirror includes a diode-configured (i.e., gate and drain terminals coupled together) transistor M1 which is connected such that a gate terminal of transistor M1 is coupled to a gate terminal of transistor M2 at node 210 and a source terminal of each transistor M1, M2 is coupled to a positive voltage supply, which may be VDD. Drain terminals of each transistor M1, M2 are coupled to collector terminals of corresponding transistors Q1, Q2, respectively.

[0024] As previously stated, the collector current flowing through transistor Q1 is ideally equal to the collector current flowing through transistor Q2, which is facilitated by making the W/L ratios of transistors M1 and M2 identical. In order to generate a difference in base-emitter voltage (ΔV_BE) between the two transistors Q1, Q2, the current density of transistor Q1 is preferably made to be greater than the current density of transistor Q2. Since the two transistors Q1, Q2 will have equal collector currents, a voltage ΔV_BE(corresponding to the difference between the base-emitter voltages of transistors Q2 and Q1) will be dropped across resistor R1. The difference in the base-emitter voltages of the two transistor Q1, Q2 is related directly to a ratio of emitter areas A1 and A2 of the transistors Q1 and Q2, respectively, and can be calculated (at least to a first order) by the following equations: $\begin{array}{cc}\Delta V_{\mathrm{BE}}=V_{\mathrm{BE},\mathrm{Q2}}-V_{\mathrm{BE},\mathrm{Q1}}=V_T·\ln \left[\frac{I_{\mathrm{C2}}}{I_{\mathrm{C1}}}·\frac{\mathrm{A1}}{\mathrm{A2}}\right]& \left(1\right)\\ \Delta V_{\mathrm{BE}}=\frac{\mathrm{kT}}{q}·\ln \left[\frac{\mathrm{A1}}{\mathrm{A2}}\right]& \left(2\right)\end{array}$

[0025] where V_T, which is proportional to temperature, is often referred to as thermal voltage and is approximately 26 millivolts (mV) at 25 degrees Celsius (C), k is Boltzman's constant (approximately 1.381×10⁻²³Joules/degree Kelvin), T is temperature in degrees Kelvin (° K.), and q is electron charge (approximately 1.6×10⁻¹⁹coulomb). By selecting an appropriate value for resistor R1, a current proportional to absolute temperature (PTAT) I_PTATis generated which biases transistor Q2, such that $\begin{array}{cc}\mathrm{Iptat}=\frac{\mathrm{kT}}{q}·\frac{\ln \left[\frac{\mathrm{A1}}{\mathrm{A2}}\right]}{\mathrm{R1}}& \left(3\right)\end{array}$

[0026] By way of example only, if transistor Q1 is made to have an emitter area ten times larger than that of transistor Q2, a voltage ΔV_BEof approximately 60 mV will appear across resistor R1. Using equation (3) above, the current I_PTATflowing through transistor Q2, and likewise through transistors M1 and M2 accordingly, can be determined for a selected bias resistor R1.

[0027] As observed in equation (1) above, rather than scaling the emitter areas A1, A2 of transistors Q1, Q2, respectively, as previously described, the emitter areas of the these two transistors can be made substantially equal to each other and instead the collector currents I_C1, I_C2of the two transistors Q1, Q2, respectively, may be scaled accordingly, such as by an appropriate selection of W/L ratios for the two transistors M1, M2. For example, by making the W/L ratio of transistor M2 ten times larger than transistor M1, the drain current of transistor M2 (which is equal to the collector current of transistor Q2) will be ten times larger than the drain current of transistor M1 (which is substantially equal to the collector current of transistor Q1) to provide a voltage drop ΔV_BEacross resistor R1 consistent with that described above (i.e., about 60 mV).

[0028] With continued reference to FIG. 2, the illustrative temperature-dependent reference circuit 200 includes the constant current source 204 which operatively generates a constant output current I₀that is substantially independent of temperature. In accordance with one aspect of the invention, the temperature-independent current I₀is preferably generated by summing a weighted portion of the PTAT current generated by PTAT current source 202, which has a predictable positive temperature coefficient, with a matching current having an equally predictable but opposite (i.e., complinentary-PTAT) temperature coefficient, whereby the resulting current will exhibit a temperature coefficient that is substantially zero.

[0029] As understood by those skilled in the art, a base-emitter voltage V_BEof a BJT device has a well-defined temperature coefficient (TC) of approximately −2 mV/degree Celsius (° C.). This voltage is preferably generated by a BJT transistor Q5 which, in the illustrative constant current source 204, has an emitter terminal connected to ground. A p-type MOS transistor M3 is coupled to transistor M1 in a mirror arrangement, with a source terminal of transistor M3 connected to the positive supply VDD and a gate terminal of transistor M3 coupled to the gate terminal of transistor M1, whereby a current I3 generated by transistor M3 is a scaled version of the PTAT current generated by the PTAT current source 202, e.g., I3=m·I_PTAT. The scaling factor m between the current I_PTATand the current I3 is determined primarily by the W/L ratios of the two transistors M1, M3, respectively (i.e., $\left(i.e.,m=\frac{{\left(W/L\right)}_{\mathrm{M3}}}{{\left(W/L\right)}_{\mathrm{M1}}}\right).$

[0030] A drain terminal of transistor M3 is coupled to a collector terminal of transistor Q5 such that the mirrored current I3 from transistor M3 is preferably used to bias transistor Q5 to a predetermined operating point.

[0031] A resistor R2 connected across the base and emitter terminals of transistor Q5 operatively converts the base-emitter voltage of transistor Q5 (V_BE,Q5) to a complimentary-PTAT current I_CPTAThaving a predefined negative temperature coefficient, whereby Icptat=V_BE,Q5/R2 (assuming the base current of transistor Q5 is negligible). This current I_CPTATis preferably passed through a transistor Q4, which has an emitter terminal connected to the junction of the base terminal of transistor Q5 and resistor R2 at node 214 and a base terminal connected to the junction of the collector terminal of transistor Q5 and the drain terminal of transistor M3 at node 216.

[0032] A scaled version of the PTAT current is preferably provided to the constant current source 204 by way transistor Q3 which is operatively coupled to transistor Q2 in a mirror arrangement. Specifically, an emitter terminal of transistor Q3 is connected to ground and a base terminal of transistor Q3 is connected to the base terminal of transistor Q2 at node 208. Preferably, the emitter area of transistor Q3 is k times the size of the emitter area of transistor Q2. Thus, transistor Q3 will generate a PTAT current that is k times the value of I_PTAT, i.e., k·I_PTAT, where the scale factor k is a number greater than zero. A collector terminal of transistor Q3 is coupled to a collector terminal of transistor Q4 at node 218, whereby the current k·I_PTATis operatively summed with the current I_CPTATto generate the output current I₀. The scale factor k and resistor R2 are preferably selected so as to make the two currents k·I_PTATand I_CPTAT, which have opposite polarity temperature coefficients, substantially equal to each other. In this manner, the temperature coefficient of the resulting output current I₀will be substantially zero, as previously stated.

[0033] As discussed above, in order to generate a current having a variation greater than the absolute temperature variation, a constant temperature-independent current is preferably subtracted from a PTAT current, in accordance with the invention. These two currents are generated by the PTAT current source 202 and the constant current source 204, respectively, as previously described. In order to perform the subtraction operation, subtraction circuit 206 is included in the illustrative reference circuit 200.

[0034] With continued reference to FIG. 2, the subtraction circuit 206 preferably includes a p-type MOS transistor M4 which is coupled to transistor M1 in a current mirror arrangement. Specifically, a source terminal of transistor M4 is connected to the positive supply VDD and a gate terminal of transistor M4 is coupled to the gate terminal of transistor M1 at node 210. The PTAT current generated by transistor M4 is designed to be larger than the constant temperature-independent current I₀from constant current source 204 in at least a predetermined temperature range of interest. Consequently, the current I_PTATmirrored from PTAT current source 202 is operatively weighted by an appropriate scale factor n. The scale factor n is selected by sizing the W/L ratios of the two transistors M1 and M4, such that n= $n=\frac{{\left(W/L\right)}_{\mathrm{M4}}}{{\left(W/L\right)}_{\mathrm{M1}}}.$

[0035] The current generated by transistor M4 will then be n·I_PTAT.

[0036] A drain terminal of transistor M4 is coupled to the collector terminal of transistor Q4 to form a subtraction node at 212. A current sink comprising BJT transistors Q6 and Q7 is operatively coupled to the subtraction node 212 to provide a return path for a resulting current I_OPTATwhich is an offset version of the PTAT current. Specifically, a collector terminal of transistor Q6 and a base terminal of transistor Q7 are connected to subtraction node 212, a collector terminal of transistor Q7 is connected to the positive supply VDD, and an emitter terminal of transistor Q7 is connected to a base terminal of transistor Q6 to form an output node 220. An emitter terminal of transistor Q6 is coupled to ground through a series-connected resistor R3. A resistor R4 is connected between output node 220 and ground and provides a return current path of the emitter current flowing from transistor Q7 in the event that output node vbb remains unloaded.

[0037] Since the PTAT current n·I_PTATflows into subtraction node 212 and constant current I₀, which is less than n·I_PTAT, flows out of node 212, the resulting offset current I_OPTATflowing into transistor Q6, and thus through resistor R3, by definition, will be I_OPTAT=n·I_PTAT−I₀, which, as previously discussed, exhibits a current variation over a given temperature range that is greater than the absolute temperature variation (see e.g., FIG. 1B). This current I_OPTATcan be converted into a voltage vbb at output node 220 which will be the sum of the base-emitter voltage of transistor Q6 and the voltage drop across resistor R3. Thus, output voltage vbb=V_BE,Q6+(loptat·R3). The current I_OPTATmay be mirrored by presenting voltage vbb to a similar current source circuit, as will be appreciated by those skilled in the art.

[0038] With reference now to FIGS. 3A and 3B, it can be shown that the constant current I₀which is subtracted from the PTAT current I_PTATis not necessarily required to be independent of temperature to provide an offset PTAT current having a variation which is greater than the absolute temperature variation. Rather, in accordance with another aspect of the invention, as long as the current I₀possesses a temperature coefficient that is zero or less, the resulting offset PTAT current I_PTAT−I₀will have a variation that is greater than the absolute temperature variation over a given temperature range.

[0039] Specifically, FIG. 3A illustrates a graph of two current components of interest, namely, the PTAT current I_PTATand the constant current I₀superimposed on the same set of axes (e.g., current I versus temperature in degrees K). As shown, the PTAT current possesses a positive temperature coefficient and the constant current possesses a negative temperature coefficient. When the constant current I₀is subtracted from the PTAT current I_PTATan offset current I_OPTAT=I_PTAT−I₀results, as illustrated in FIG. 3B, which exhibits a larger variation, as compared to when the constant current I₀is independent of temperature (see e.g., FIG. 1B), than the absolute temperature variation.

[0040] FIG. 4 depicts an exemplary reference circuit 400 for implementing a temperature-dependent reference having an output which varies greater than the absolute temperature variation, formed in accordance with another aspect of the invention. The illustrative reference circuit 400 includes a PTAT current source 202, a negative temperature coefficient (TC) current source 402 and a subtraction circuit 206 operatively coupled to the PTAT current source 202 and the negative TC current source 402 for generating the temperature-dependent output current I_OPTAT. It is to be appreciated that the PTAT current source 202 may be implemented in a manner consistent with that described above in connection with FIG. 2 for generating the PTAT current I_PTAT.

[0041] The negative TC current source 402 generates an output current I₀which, unlike the constant current source 204 shown in FIG. 2 (which possesses a substantially zero temperature coefficient), exhibits a complimentary PTAT or negative temperature coefficient. As discussed above, a well known quantity having a predictable negative temperature coefficient is the base-emitter voltage of a typical BJT device. This voltage may be easily converted to a corresponding current by presenting the base-emitter voltage V_BEacross a resistor. This complementary PTAT current I_CPTATmay be generated in a manner consistent with the constant current source 204 described herein above and depicted in FIG. 2.

[0042] As previously stated, the base-emitter voltage is preferably generated by BJT transistor Q5 which has an emitter terminal connected to ground. A p-type MOS transistor M3 coupled to transistor M1 in a mirror configuration provides a current I3 for biasing transistor Q5 to a predetermined operating point. Specifically, a source terminal of transistor M3 is connected to the positive supply VDD and a gate terminal of transistor M3 is coupled to the gate terminal of transistor M1 at node 210, whereby the current I3 is a scaled version of the PTAT current generated by the PTAT current source 202, e.g., I3=m·I_PTAT. The scaling factor m between the current I_PTATand the current I3 will be determined primarily by the W/L ratios of the two transistors M1, M3, respectively (i.e., $\left(i.e.,m=\frac{{\left(W/L\right)}_{\mathrm{M3}}}{{\left(W/L\right)}_{\mathrm{M1}}}\right).$

[0043] A drain terminal of transistor M3 is coupled to a collector terminal of transistor Q5 for presenting the mirrored current I3 to transistor Q5.

[0044] A resistor R2 connected across the base and emitter terminals of transistor Q5 operatively converts the base-emitter voltage of transistor Q5 (V_BE,Q5) to a complimentary-PTAT current I_CPTAThaving a predefined negative temperature coefficient, whereby I_CPTAT=V_BE,Q5/R2 (assuming the base current of transistor Q5 is negligible). This current I_CPTATis preferably passed through a transistor Q4, which has an emitter terminal connected to the junction of the base terminal of transistor Q5 and resistor R2 at node 214 and a base terminal connected to the junction of the collector terminal of transistor Q5 and the drain terminal of transistor M3 at node 216. A collector terminal of transistor Q4 forms an output 218 of the negative TC current source 402. The output current I₀flowing into the output 218 is substantially equal to the current I_CPTAT, assuming the base current flowing into the base terminal of transistor Q4 is negligible.

[0045] It is to be appreciated that since the temperature coefficient of the output current I₀is not required to be zero in this illustrative embodiment of the invention, a positive temperature coefficient current (e.g., I_PTAT) is not required to be summed with current I_CPTAT. Therefore, BJT transistor Q3 (see FIG. 2), which formally supplied a weighted PTAT current to be added to the complementary PTAT current I_CPTAT, has been omitted in the negative TC current source circuit 402.

[0046] With continued reference to FIG. 4, the subtraction circuit 206 is preferably implemented in a manner consistent with that previously described in connection with FIG. 2. Specifically, transistor M4 is coupled to transistor M1 in the PTAT current source 202 in a current mirror configuration for supplying a scaled PTAT current n·I_pTAT. As discussed above, the scale factor n is preferably selected so that the scaled PTAT current n·I_PTATis always larger than the current I₀in at least a desired temperature range of operation. Scale factor n is preferably selected by sizing the W/L ratios of the two transistors M1 and M4, such that $n=\frac{{\left(W/L\right)}_{\mathrm{M4}}}{{\left(W/L\right)}_{\mathrm{M1}}}.$

[0047] The output 218 of the negative TC current source 402 is coupled to the drain terminal of transistor M4 to form a subtraction node at 212 whereby the negative TC current I₀, which is essentially the current I_CPTAT, is subtracted from the PTAT current n·I_PTATto generate the offset PTAT current I_OPTATshown in FIG. 3B.

[0048] A current sink comprised of BJT transistors Q6 and Q7 and resistors R3 and R4 is operatively coupled to the subtraction node 212 to provide a return path for the current I_OPTAT, as previously described. Since the PTAT current n·I_PTATflows into subtraction node 212 and current I₀, which is less than n·I_PTATin the temperature range of interest, flows out of node 212, the resulting offset current I_OPTATflowing into transistor Q6, and thus through resistor R3, by definition, will be I_OPTAT=n·I_PTAT−I₀, which, as discussed herein above, exhibits a current variation over a given temperature range that is greater than the absolute temperature variation (see e.g., FIG. 3B). Furthermore, compared to the illustrative circuit implementation depicted in FIG. 2, the reference circuit of FIG. 4 consumes less power due, at least in part, to the omission of transistor Q3.

[0049] The offset PTAT current I_OPTATcan be converted into a voltage vbb at output node 220 which will be the sum of the base-emitter voltage of transistor Q6 and the voltage drop across resistor R3. Thus, output voltage vbb=V_BE,Q6+(I_OPTAT·R3). This voltage vbb may be used as a reference output preferably by first buffering the voltage. The current I_OPTATmay be subsequently mirrored by presenting voltage vbb to a corresponding current source circuit, as will be appreciated by those skilled in the art.

[0050] It is to be appreciated that the reference generators described herein may be fabricated on a semiconductor as an integrated circuit device. Using the techniques described herein in accordance with the present invention, circuits having a relatively high temperature dependency can be easily compensated. Moreover, the reference circuits are suitable for temperature sensing with large temperature dependency without requiring a high supply voltage.

[0051] Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention.